JPH1185514A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor with which immediate data in the instruction of a fixed bit length can be read and the internal data of a bit length suitable for an object electronic system can be handled without changing the design of a control part or environment for programming. SOLUTION: An instruction decoder 18 fetches an instruction from an instruction memory 11 and generates a signal for control. Besides, when the fetched instruction is an instruction for continuously writing immediate data into the same register in a register file 15, a continuous write detection part 19 turns a write position control signal (e) into logic 1. When the immediate data are outputted from a selector 13b, a data write position change part 20 of a pipeline register 21b fetches the immediate data while changing the setting position according to the write position control signal (e). The immediate data, which reach the bit length of internal data, are written through an arithmetic logic computing element 16 and a selector 13c into the register file 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing a change in a development environment and a change in a circuit design when providing an information processing apparatus having an optimum scale by changing a bit width of a data path. The present invention relates to an information processing apparatus which is greatly affected by a change in width and which simplifies handling of immediate data.

[0002]

2. Description of the Related Art As a conventional information processing apparatus, for example,
"Computer Configuration and Design" (Jhon L. Hen
nessy, David A. By Paterson,
FIG. 3 shows the configuration. This information processing apparatus includes a data path 3 and a control unit 4
The data path 3 includes a data transfer path and various functional blocks disposed between the data transfer paths, that is, a program counter 10, an instruction memory 11, adders 12a and 12b, selectors 13a, 13b and 13c, and a sign extension. Circuit 14, register file 15, arithmetic logic unit 16, data memory 17, pipeline register 2
1a, 21e, 21c, and 21d, and provides a desired operation to data used for processing. The control unit 4 includes the instruction decoder 40 and the pipeline register 2
1a, 21e, 21c, and 21d, and generates a control signal group for selecting a data transfer path in the data path 3 and a control signal group for selecting a function of each functional block. Things.

[0003] The pipeline registers 21a, 21e, 2
As shown in FIG. 3, 1c and 21d are partly included in the data path 3 and the other part is included in the control unit 4, and repeat the operation of latching the input value at predetermined intervals. The instruction memory 11 holds an instruction to be executed by the information processing device, and outputs an instruction corresponding to an address given from the program counter 10. The instruction output from the instruction memory 11 is stored in the pipeline register 21 every predetermined period.
a.

An instruction decoder 40 controls a control signal a, according to an instruction fetched into the pipeline register 21a.
b, c, d, f ', g ", h", i "', j"', and k "'. Of the control signals generated by the instruction decoder 40, the signals f ', g" , H ", i"',
j ″ ′ and k ″ ′ are taken into the pipeline register 21e at predetermined intervals, and the signals f, g ′,
Output as h ', i ", j" and k ".

The program counter 10 uses the value selected by the selector 13a as the address of the next instruction,
It is taken in at predetermined intervals. The selector 13a outputs the output of the adder 12a or the adder 12a in accordance with the control signal a which is the output select signal generated by the instruction decoder 40.
Select one of the outputs of b. The adder 12a adds a predetermined constant value, for example, 1 to the value of the program counter 10.
And its output is connected to one input of the selector 13a. The output of the adder 12a is taken into the pipeline register 21a at predetermined intervals. Adder 12
b adds the output value of the adder 12a fetched by the pipeline register 21a and the output of the sign extension circuit 14.
The output of the adder 12b is connected to the other input of the selector 13a.

[0006] Immediate data indicated at a predetermined bit position in the instruction output from the instruction memory 11 is fetched into the pipeline register 21a at predetermined intervals, and then input to the sign extension circuit 14. As described later, the bit length of the immediate data is determined by the data width handled by the adder 12b, that is, the instruction memory 11 handled by the program counter 10.
Is shorter than the address bit length. Therefore, the sign extension circuit 14 performs a sign extension operation on the immediate data, and extends the bit length to a length that can be handled by the adder 12b.

[0007] The register file 15 is composed of a plurality of registers for temporarily holding various data necessary when the information processing apparatus performs processing, and has two output ports Rs1 and Rs2. Register file 1
5 outputs to the output port Rs1 the value held by the register specified by the read register select signal c generated by the instruction decoder 40 from among the plurality of registers, and outputs the value specified by the read register select signal d. Is output to the output port Rs2.

The selector 13b has a register file 15
Of the output port Rs2 and the output of the sign extension circuit 14 are selected and output according to the select signal b. The values of the output ports Rs2 and Rs1 of the register file 15 and the output of the selector 13b are taken into the pipeline register 21e at predetermined intervals.

[0009] One input of the arithmetic and logic unit 16 is connected to the value of the output port Rs1 of the register file 15 taken into the pipeline register 21e. The other input of the arithmetic and logic unit 16 is connected to the output value of the selector 13b taken into the pipeline register 21e. The bit length of the data handled by the arithmetic and logic unit 16 is determined by the adders 12a and 12b and the program counter 1
0 is the same as the bit length of the data to be handled. The arithmetic and logic unit 16 performs various arithmetic and logical operations on the two input data and outputs the result. At this time, the operation to be performed is specified by the function selection signal f output from the pipeline register 21e.

The output of the arithmetic and logic unit 16 is taken into the pipeline register 21c at predetermined intervals, and the value of the output port Rs2 of the register file 15 is sent to the pipeline register 21c via the pipeline register 21e. At a predetermined cycle. Further, a control signal g ′ output from the pipeline register 21e,
h ′, i ″, j ″ and k ″ are further taken into the pipeline register 21c at predetermined intervals, and the signals g, h,
Output as i ', j' and k '.

The data memory 17 stores various data generated when the information processing apparatus performs processing.
It is a readable and writable memory. The data memory write signal h output from the pipeline register 21c indicates whether or not to write data to the data memory 17. When the signal h indicates writing, the output value from the output port Rs2 of the register file 15 via the pipeline register 21e and the pipeline register 21c is written to the data memory 17. At this time, the address of the writing destination is given by the output value of the arithmetic and logic unit 16 via the pipeline register 21c.

The data memory read signal g output from the pipeline register 21c indicates whether data is to be read from the data memory 17. When the signal g indicates a read operation, the arithmetic logic unit 16 in the data memory 17 via the pipeline register 21c
The data stored at the address corresponding to the output value is output from the data memory 17. The output data from the data memory 17 and the output value of the arithmetic and logic unit 16 via the pipeline register 21c are further taken into the pipeline register 21d. The control signals i ′, j ′ and k ′ are stored in the pipeline register 21d.
And output as control signals i, j and k, respectively.

One input of the selector 13c is connected to the output value of the data memory 17 via the pipeline register 21d, and the other input is connected to the arithmetic logic via the pipeline register 21c and the pipeline register 21d. The output value of the computing unit 16 is connected. Selector 1
3c selects and outputs one of the two input data according to the select signal k output from the pipeline register 21d. The output of the selector 13c is connected to the data input of the register file 15.
The register write signal j is a signal for instructing whether or not to write to the register file 15, and the write register select signal i is
These are signals for designating a register into which data is written, and are output from the pipeline register 21d. The output of the selector 13c is written into the register file 15 at a predetermined timing according to the register write signal j and the write register select signal i.

Next, the operation of the above information processing apparatus will be described. First, the flow of the operation is shown in the flowchart of FIG. In step 101, an instruction fetch operation for reading an instruction from the instruction memory 11 is performed. Step 102
Then, the instruction is decoded by the instruction decoder 40, a signal group for control is generated, and an instruction decode / operand fetch operation for reading desired data from the register file 15 or immediate data in the instruction is performed. In step 103, the arithmetic and logic unit 16 performs an operation for performing a desired operation. In step 104, the data memory 1
7 to perform a memory access operation for reading and writing. In step 105, a register write operation for writing to the register file 15 is performed. The five types of operations from step 101 to step 105 are executed by so-called pipeline processing, which is divided by the pipeline registers 21a, 21e, 21c, and 21d, and is continuously performed in parallel at predetermined intervals.

The data width handled by the information processing apparatus, that is, adders 12a and 12b, register file 1
5, a specific operation will be described by taking as an example a case where the bit lengths of the arithmetic logic unit 16, the data memory 17, and the like are set to 32 bits. FIG. 5 shows an example of an instruction executed by the information processing apparatus, that is, an instruction held in the instruction memory 11 that handles immediate data. This instruction is 32 bits long, and its bit position is changed from b0 to b0 from the LSB side to the MSB side.
If b31, 1 from bit b0 to bit b15
Six bits are an immediate field to which immediate data is given. Also, 5 bits from bit b16 to bit b20 are a first operand field,
The first operand rt is the bit b21 to the bit b2
Five bits up to 5 are a second operand field, and are provided with a second operand rs. The opcode indicating the function of the instruction is given by a 6-bit opcode field from bit b26 to bit b31.

One of the instructions of this form includes, for example, the first
Of the 32-bit length first register output from the output port Rs1 of the register file 15 and the value of the immediate data given by the 16-bit length immediate field specified by the operand field of There is an instruction for performing a process of writing the result of the addition to a desired register in the register file 15 specified by the second operand field, and this instruction is called an add immediate instruction (add immediate).
In this add-immediate instruction, the 16-bit immediate data is converted into 32-bit data by the sign extension circuit 14, and the arithmetic and logic unit 16 performs the operation.

One of the instructions in the form shown in FIG. 5 includes an immediate field in the upper 16 bits of a second 32-bit register in the register file 15 indicated by an operand (rt) field. Write the immediate data of 16-bit length given by, load upper immediate (load upper immediate)
ate) instruction.

For example, in the register file 15, 32
A 32-bit immediate data "1010 0000 0011 1101 00" is stored in a desired bit-length register Rn.
001001 0000 0000 "(hexadecimal" A
03D 0900 ″), the immediate data processing instruction, that is, the add immediate instruction and the load upper immediate instruction, is used as follows. The value of the register Rn is cleared to 0 as an initial state. First, “A03D” (1) is added to the upper 16 bits of the register Rn by a load upper immediate instruction.
Hexadecimal notation) and write the following add immediate instruction.
The value of the register Rn and the immediate data "090
The result of addition with 0 "(hexadecimal notation) is again stored in the register Rn.
Write to. As a result, the hexadecimal number “A” is stored in the register Rn.
03D 0900 "has been written.

As described above, in a conventional information processing apparatus such as a RICS processor, a fixed instruction length is used to simplify a control unit and improve processing performance. Is shorter than the bit length of the internal data handled by the information processing device. Since it is difficult to efficiently assign the maximum data width of internal data to immediate data in an instruction while keeping the instruction length moderate, when handling immediate data with the maximum data width, multiple instructions are generally used. Used.

[0020]

However, in recent years,
Since the circuit scale and cost of electronic devices used in automobiles and the like are increasing, the information processing device of the vehicle-mounted electronic system and peripheral dedicated circuits are integrated into semiconductor chips to achieve high reliability, miniaturization and low cost. There is a strong demand to move forward. It is known that, as the area of a semiconductor chip increases, the yield in the manufacturing process exponentially deteriorates, which greatly affects the cost. Therefore,
In order to reduce the area of a semiconductor chip, it is required to reduce the size of an information processing device as much as possible.

One of the major factors affecting the scale of an information processing apparatus is the bit length of internal data handled by the information processing apparatus. The bit length of this internal data depends on the precision and resolution of the data to be processed by the target electronic system.
It is desirable to set the minimum bit length while satisfying the required specifications of the electronic system. For example, when the electronic system to be applied is sufficient with 16-bit internal data, it is not preferable in terms of cost to use the above-described conventional information processing apparatus that handles 32-bit internal data. It is better to use a low-cost information processing apparatus that handles 16-bit internal data.

However, the 16-bit information processing device differs from the aforementioned 32-bit information processing device not only in the bit length of the internal data to be handled, but also in its instruction form. "Nikkei Electronics, NO.568"
FIG. 6 shows an example of this instruction form described in (Issue 1992.11.23). This instruction is one of an instruction set having a fixed length of 16 bits, and is an instruction for taking immediate data into a desired register in a register file.

Eight bits from bit b0 to bit b7 are an immediate field, to which immediate data is given. Bits b8 to b11 are an operand field, in which an operand of a register for capturing immediate data is specified. Bits 12 to b15 are an opcode field, and the opcode of this instruction is given. In the instruction form shown in FIG. 6, the immediate data to be handled is
8 bits, 16 bits as internal data of the information processing device
When handling immediate data of bits, for example, upper and lower 8 bits are respectively divided and taken in.

In an on-vehicle electronic equipment system or the like, it is desirable that the instruction set be in a common form while the information processing apparatus of the optimum scale is selected according to the electronic system to be applied, from the viewpoint of not lowering the development efficiency. . For example,
It is desirable that the instruction format is fixed to a 16-bit length as shown in FIG. 6 and the instruction set itself is also fixed.

However, in the conventional information processing apparatus, as described above, one instruction handles only immediate data having a length less than the bit length of the internal data. The configuration is such that a dedicated command is provided to set the immediate data a plurality of times. Therefore, for example, in order to change the bit length of the internal data handled by the information processing device to 32 bits without changing the 16-bit instruction described above, it is necessary not only to change the data path but also to add a dedicated instruction. It is necessary to change the design of the control unit by adding to the above, and to change various environments for programming.

In general, the data path of an information processing apparatus has a very regular configuration, so that it is relatively easy to expand and reduce the bit length, while the control section has the most complicated configuration. In addition, there is a problem that the design change of the control unit requires a large number of man-hours and increases the development cost. Further, changing the various environments for programming also has a problem that an increase in bugs and an increase in the number of steps of the programming work are caused due to inexperience in the programming work.

The present invention has been made in view of the above-described conventional problems, and even when the bit length of immediate data handled by one instruction is fixed to a predetermined number of bits, information processing by adding a new instruction is performed. Immediate data can be read without changing the design of the control unit of the device or changing various environments for programming, and handle internal data having a necessary and sufficient bit length according to the target electronic system. It is an object of the present invention to provide an information processing device capable of performing the following.

[0028]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a control unit for decoding a given instruction and generating a control signal, and executing a process in accordance with the control signal generated by the control unit. And a control unit, wherein the control unit detects a continuous writing operation of a processing result based on the immediate data in a writing area specified by the same operand. A data write position change unit that switches a write position in a write area according to the number of continuous writes based on a detection result of the continuous write detection unit; and a data write position change unit. It is assumed that a data writing means for writing the processing result based on the immediate data in the writing area in accordance with the result of the change in.

The data write position change unit counts the number of times a write operation is continuously performed on the write area specified by the same operand based on the detection result of the continuous write detection unit. In a given instruction, process multiple registers that have the same bit length as the bit length of immediate data that can be directly specified, and register that captures the processing result based on the immediate data according to the counting result in the counting unit. A selector for selecting for each bit portion of the result;
It is preferable to have a write signal generation unit that generates a write enable signal for the register selected by the selection unit.

[0030]

When the processing result of the immediate data is successively written to the area specified by the same operand, the writing position in the specified area is changed according to the number of times of continuation. Since there is no need to specify the write position by an instruction, a dedicated instruction for each write position is not required. For that purpose, to add new instructions or change the instruction set,
Even if the bit length of the immediate data handled by one instruction is fixed to a predetermined number of bits without redesigning the control unit of the information processing device or changing various programming environments,
Internal data having a necessary and sufficient bit length can be handled according to the target electronic system.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to examples. FIG. 1 is a diagram showing the configuration of the present embodiment that handles 32-bit internal data. The input instruction set is
It has a fixed length of 16 bits and is in the form of an instruction for handling immediate data. The data path 1 includes a data transfer path for giving a desired operation to data used for processing and various functional blocks interposed therebetween. That is, the program counter 10, instruction memory 11, adders 12a and 1
2b, selectors 13a, 13b and 13c, sign extension circuit 14, register file 15, arithmetic logic unit 1
6, the data memory 17, and the pipeline registers 21a, 21b, 21c and 21 interposed therebetween.
d.

The control unit 2 generates a control signal group for selecting a data transfer path in the data path 1 and a control signal group for selecting a function of each functional block. 18 and the pipeline register 21
a, 21b, 21c, and 21d. The pipeline register 21b is provided with a data write position changing unit 20 instead of a normal register that takes in the output from the selector 13b. Other configurations are
This is the same as the pipeline register 21e shown in FIG.
When the immediate data is output from the selector 13b, the data writing position changing unit 20 changes and sets the setting position of the immediate data as needed.

The instruction decoder 18 has a continuous write detection unit 19, and similarly to the instruction decoder 40 shown in FIG. 3, control signal groups a, b, c, d, f ', g ", h",
i ″ ′, j ″ ″, and k ″ ″ are generated, and further, the continuous write detection unit 19 generates a write position control signal e. In the continuous write detection unit 19, the fetched instruction processes the immediate data. This is an instruction to write to a predetermined register in the register file 15. When an instruction of this function is fetched continuously and operands for specifying the write destination are the same, that is, continuous writing to the same register is specified. At this time, the write position control signal e is set to ethical 1, otherwise, it is set to logic 0. The write position control signal e controls the write position of the data write position changing unit 20.

FIG. 2 shows the configuration of the data write position changing unit 20. Based on the 8-bit registers 25a, 25b, 25c, and 25d and the write position control signal e, the data write position changing unit 20 continuously performs a write operation on the write area specified by the same operand. A counting unit 26 that counts the number of times the data is processed and outputs a select signal se; 23 and 2
4 and a write signal generation unit 27 that generates write enable signals we0, we1, we2, and we3 for the registers selected by the selectors 22, 23, and 24.

The select signal s output from the counter 26
e is connected to the selection signal inputs of the selectors 22, 23, and 24 and to the write signal generation unit 27. The write enable signal we3 is applied to the write enable input of the register 25a, the write enable signal we2 is applied to the write enable input of the register 25b, the write enable signal we1 is applied to the write enable input of the register 25c, and the write enable signal we0 is applied.
Are respectively connected to the write enable inputs of the register 25d.

The select signal se is a signal indicating the number of times that the write position control signal e generated by the continuous write detecting section 19 has a logic 1 continuously. That is, the select signal se becomes 0 when immediate data is not continuously written to the same register in the register file 15, and becomes 1 when immediate data is written to the same register twice in succession. If it continues three times, it becomes 2, and if it lasts four times, it becomes 3. When writing to the same register continues, the select signal se returns to 0, and repeats counting as 1, 2, and 3.

The selector 22 is an 8-bit 4-to-1 selector and has four 8-bit inputs from a 0th input to a 3rd input. The selector 22 outputs a select signal s
Data having the same input number as the value of e is output. The most significant 8 bits (b31 to b24) of the 32-bit output of the selector 13b are connected to the 0th input, the next 8 bits (b23 to b16) are connected to the 1st input, and the next 8 bits are further connected.
The bits (b15 to b8) are connected to the second input, and the least significant 8 bits (b7 to b0) are connected to the third input.

Similarly, the selector 23 has an 8-bit 3to
This is a 1 selector and has three 8-bit inputs from the 0th input to the 2nd input. The selector 23 outputs data of an input number having the same value as the value of the select signal se. However, the output when the value of the select signal se is 3 is arbitrary. Of the 32-bit output of the selector 13b,
Except for the most significant 8 bits (b31 to b24), the next 8 bits
The bits (b23 to b16) are connected to the 0th input, the next 8 bits (b15 to 8) are connected to the 1st input, and the least significant 8 bits (b7 to b0) are connected to the 2nd input. .

Similarly, the selector 24 is an 8-bit 2to
It is a 1 selector and has two 8-bit inputs, a 0th input and a 1st input. The selector 24 outputs the 0th input data when the select signal se is 0, and outputs the 1st input data when the select signal se is 1. When the select signal se is 2 or 3, the output is arbitrary. Selector 1
In the 32-bit output of 3b, except for the upper 16 bits (b31 to b16), the next 8 bits (b15 to b15)
8) is connected to the 0th input, and the least significant 8 bits (b7 to b
0) is connected to the first input.

The write enable signals we3, we2, we1, and we0 output from the write signal generation unit 27 are signals for controlling whether to write data into the registers 25a, 25b, 25c, and 25d, respectively. Switching is performed according to the value of the select signal se. The write enable signal we0 permits writing only when the value of the select signal se is 0. We1 is the select signal se
Is permitted only when the value of is 0 or 1. w
e2 permits writing only when the value of the select signal se is 0, 1 or 2. We3 is the select signal se
Always allow writing, regardless of the value of. Register 2
The outputs of 5a, 25b, 25c and 25d are connected to one data input of arithmetic logic unit 16 as a 32-bit data signal. The data path 1 constitutes an execution unit of the invention, and the selectors 22, 23 and 24, the registers 25a, 25b, 25c and 26d, the counting unit 26 and the write signal generation unit 27 constitute a data write position changing unit. I do. In particular, selectors 22, 23 and 24
Constitutes a selection unit. Also, the pipeline register 21
d and the selector 13c constitute the data writing means of the present invention.

Next, regarding the operation of this embodiment, immediate data "A03D0900" of 32 bits (in hexadecimal notation)
Is written in the register R2 in the register file 15. First, as a first instruction, an instruction of the form shown in FIG. 6 is used, and b7 to b0 are converted to a binary number “0000 000”.
The least significant byte of the immediate data is given as "0" (hexadecimal "00"), the register R2 is shown as b11 to b8 as the binary number "00010", and the immediate data load (immediate data The instruction decoder 18 which has fetched the first instruction via the pipeline register 21a outputs a code corresponding to the processing to the selector 13b as a select signal b to the selector 13b. Generate a control signal for selecting.

At this time, the sign extension circuit 14
Immediate data part b7 to b0 in the instruction of "000000"
Thus, the selector 13b outputs all bits of "0". Since the continuous immediate data writing to the same register is not performed, the write position control is performed. The signal e is
It is logic 0, and the value of the select signal se is 0. Therefore, writing to the data write position changing unit 20 is performed to the registers 25a, 25b, 25c, and 25d, and the binary numbers “0000 0000” are respectively provided.
Is written.

The output of the data write position changing unit 20 is:
As shown in FIG. 1, it is connected to one data input of the arithmetic and logic unit 16 and at this time,
Of the data write position change unit 2
It is instructed so that the output of 0 is used as it is as the output of the arithmetic and logic unit. Accordingly, the immediate data of the least significant byte given by the first instruction is taken in the pipeline register 21c as the output of the arithmetic and logic unit 16 in the next cycle in a sign-extended form, and further in the next cycle. , Are taken into the pipeline register 21d.

Select signal k for selector 13c
Instructs to output the immediate data of the least significant byte given by the first instruction and taken into the pipeline register 21d at this time. Further, in the next cycle, the output of the selector 13c is written to the register file 15. At this time, the register select signal i for writing to the register file 15 indicates the register R2, and the register write signal j for writing. With the above flow, the least significant byte of the desired immediate data is written into the register R2.

Next, the 32-bit immediate data "A03D"
A second instruction for writing a value of the second byte from the lower end of “0900” (hexadecimal number), that is, a binary number “0000 1001” at a predetermined position will be described. , And the write destination operand are exactly the same as the first instruction, and only the provided immediate data is different, that is, in the instruction form shown in FIG.
The second byte immediate data (binary "000") is stored in b7 to b0.
0 1001 "), and b11 to b8 are binary numbers" 0
010 "(register R2), a code corresponding to the same immediate data load processing as the first instruction is given to the operation codes b15 to b12.

The second instruction is fetched into the pipeline register 21a following the first instruction, and
8 given. In the second instruction, as in the first instruction, the select signal b specifies that the selector 13b passes the output of the sign extension circuit 14. Therefore, the 32-bit immediate data "0000 0000 0000 000" obtained by sign-extending the 8-bit immediate data "0000 1001" in the second instruction is output to the output of the selector 13b.
0 0000 0000 0000 1001 "is output.

Since the writing of immediate data to the same register R2 is going to be performed continuously, the signal e becomes logic 1
, And the value of the select signal se becomes 1. Therefore, writing to the data write position changing unit 20 is performed to the registers 25a, 25b, and 25c. At this time,
Since the selector 22 selects the third byte (b23 to b16) from the lower end of the output of the selector 13b, the binary number "0000 0000" is written in the register 25a. Further, since the selector 23 selects the second byte (b15 to b8) from the lower end of the output of the selector 13b, the register 25b stores the binary number "0000 0000".
0 "is written.

Further, the selector 24 is the selector 1
Since the least significant byte (b7 to b0) of the output of 3b is selected, the binary number “0000 10” is stored in the register 25c.
01 "is written. Since the select signal se is not 0, the write enable signal we0 does not permit writing, so that no data is written to the register 25d and the first
The binary number "0000 0000" written by this instruction is held. At this stage, the output of the data write position change unit 20 is a binary number “0000 0000 000”.
0 0000 0000 1001 0000 000
0 ", and the value up to the lower two bytes of the 32-bit immediate data to be written to the register R2 is given in a sign-extended form. Thereafter, the processing proceeds exactly in the same manner as in the first instruction, and the lower order is stored in the register R2. Immediate data of 2 bytes is written in a form extended to 32 bits.

Next, the 32-bit immediate data "A03D"
The third instruction for writing the value of the third byte from the bottom of 0900 ”(in hexadecimal notation), that is, the binary number“ 0011 1101 ”, at a predetermined position is composed of an instruction form, an operation code, and a destination operand. It is exactly the same as the first and second instructions, and only the provided immediate data is different, that is, b7 to b0 in the instruction form shown in FIG.
Is the third byte of immediate data (binary number “0011 110
1 "), and a code corresponding to the same immediate data load processing as the first and second instructions is given to the operation codes of binary" 0010 "(register R2) and b15 to b12 to b11 to b8.

The third instruction is fetched into the pipeline register 21a following the first and second instructions, and supplied to the instruction decoder 18. In the third instruction, as in the first and second instructions, the selector signal b specifies that the selector 13b passes the output of the sign extension circuit 14. Therefore, the 8-bit immediate data "0011 1101" in the third instruction is sign-extended to the output of the selector 13b to provide the 32-bit immediate data "0000 0000 0".
000 0000 0000 0000 0011 1
101 "is output.

Since the writing of immediate data to the same register R2 is about to be performed more continuously, the write position control signal e keeps the logic 1 and the select signal s
The value of e is 2. Therefore, writing to the data write position changing unit 20 is performed only for the registers 25a and 25b. At this time, the selector 22 outputs the second byte from the lower end of the output of the selector 13b (b15 to b8).
Is selected, the register 25a stores the binary number “0”.
000 0000 ”is written.
3 is the least significant byte (b8 to b8) of the output of the selector 13b.
Since 0) is selected, the binary number “0011 1101” is written in the register 25b.

Since writing to the registers 25c and 25d is not permitted by the write permission signals we0 and we1, no writing is performed, and the first and second registers are respectively performed.
The binary number “0000 1001” and the binary number “0000 0000” written by this instruction are held.
At this stage, the output of the data write position change unit 20 is:
Binary "0000 0000 0011 1101 0
000 1001 0000 0000 ", which is the lower 3 bits of the 32-bit immediate data to be written to the register R2.
The value up to the byte is given in sign-extended form. Thereafter, the processing proceeds in exactly the same way as the first and second instructions, and the immediate data of the lower three bytes is written into the register R2 in a form sign-extended to 32 bits.

32-bit immediate data "A03D 090"
0 ”(hexadecimal notation), the value of the fourth byte (most significant byte) from the bottom, that is, the binary number“ 1010 0000 ”
Is exactly the same as the first, second, and third instructions in the form of the instruction, the operation code, and the write destination operand, and only the given immediate data is different. That is, in the instruction form shown in FIG.
4th byte immediate data (binary "1010
0000 "), and binary numbers" 001 "are assigned to b11 to b8.
0 "(register R2), a code corresponding to the same immediate data load processing as the first, second, and third instructions is given to the operation codes b15 to b12.

The fourth instruction is fetched into the pipeline register 21a following the first, second, and third instructions, and supplied to the instruction decoder 18. In the fourth instruction, as in the first, second, and third instructions, the select signal b specifies that the selector 13b passes the output of the sign extension circuit 14. Therefore, the 8-bit immediate data "1010 0000" in the fourth instruction is sign-extended to the output of the selector 13b, and the 32-bit immediate data "0000 000" is output.
0 0000 0000 0000 0000 101
0 0000 "is output.

Since the writing of immediate data to the same register R2 is about to be performed more continuously, the write position control signal e keeps the logic 1 and the select signal s.
The value of e is 3. Therefore, writing to the data write position changing unit 20 is performed only for the register 25a. At this time, since the selector 22 has selected the least significant byte (b8 to b0) of the output of the selector 13b,
In the register 25a, the binary number "1010 0000"
Is written.

Since writing is not permitted to the registers 25b, 25c, and 25d by the write permission signals we0, we1, and we2, no writing is performed, and the binary numbers written by the first, second, and third instructions, respectively, are used. 0011 1101 "," 0000 1001 ",
“0000 0000” is held. At this stage, the output of the data write position change unit 20 is binary “1010 0000 0011 1101 0000”.
1001 0000 0000 "and register R
2 is provided with 32-bit immediate data to be written.
Thereafter, the processing proceeds in exactly the same manner as the first, second, and third instructions, and 4-byte, that is, 32-bit immediate data is written to the register R2.

In this embodiment, the control section 2 is provided with a continuous write detecting section 19 for detecting continuous write to a write area designated by the same operand, and a count for counting the number of times a write operation is continuously performed. Section 26, four registers 25a, 25b, 25c and 25d, and a selector 2 for selecting a register for taking in the processing result for each bit portion of the processing result according to the counting result of the counting section 26.
2, 23 and 24 and registers 25a, 25b, 25
By providing a data write position changing unit 20 including a write signal generation unit 27 for generating a write permission signal for writing to c and 25d in the data path 1, a processing result by immediate data is continuously designated by the same operand. When writing to an area to be written, the writing position in the specified area is changed according to the number of consecutive times, so that there is no need to specify the writing position with an instruction, and a dedicated instruction for each writing position is not required. .

Therefore, without redesigning the control unit of the information processing apparatus and changing various programming environments for adding new instructions and changing the instruction set, the immediate data of one instruction can be handled. Even when the bit length is fixed to a predetermined number of bits, the immediate data is read, the read immediate data is connected to the bit length of the internal data handled by the information processing device, and written in the area specified by the operand. be able to. In this embodiment, the information processing apparatus handles 32-bit internal data. However, the present invention is not limited to this. The internal data having a bit length that is a multiple of the bit number of the immediate data in the instruction is used. Should be fine. For example, when the information processing apparatus is changed to one that handles internal data having a length of 24 bits, the control unit 2 shown in FIG. 1 does not need to make any change, and changes the bit width of each component of the data path unit. , 24 bits.

If the data path section is designed in advance with basic blocks in units of 8 bits, in a 32-bit configuration, the basic blocks are connected by 4 blocks, and
In the case of the 4-bit configuration, the configuration may be made by connecting three blocks. The configuration can be similarly changed to a 16-bit or 8-bit configuration. The data write position changing unit is also 8
If the configuration is made in units of bits, for example, when changing to a 24-bit configuration, it is only necessary to delete the selector 22 and the register 25a. It can be easily changed to a 16-bit configuration or an 8-bit configuration. Since these bit width changes do not affect the instruction system at all, there is no need to change the design of the control unit or change various programming environments. In this embodiment, the pipeline processing is performed.
It is also possible to execute by non-pipeline processing.

[0060]

As described above, according to the information processing apparatus of the present invention, the control unit is provided with the continuous write detection unit for detecting the continuous write to the write area specified by the same operand. A counting unit that counts the number of times that a write operation is continuously performed, a plurality of registers, and a selection unit that selects a register that captures a processing result for each bit portion of the processing result in accordance with the counting result in the counting unit; By providing a data write position change unit in the execution unit, which is composed of a write signal generation unit that generates a write enable signal to the register, the processing result by immediate data can be continuously written in the write area specified by the same operand. When writing to, the write position in the specified write area is changed according to the number of consecutive times. That need is not, a dedicated instruction of each writing position becomes unnecessary.

For this purpose, the re-design of the control unit of the information processing apparatus for the addition of a new instruction or the change of the instruction set, and the change of the immediate data to be handled by one instruction without changing various programming environments. Even if the bit length is fixed to a predetermined number of bits, the immediate data is read, the read immediate data is connected to the bit length of the internal data handled by the information processing device, and the data is stored in the write area specified by the operand. It is possible to provide an information processing device that can write and can handle internal data having a necessary and sufficient bit length according to a target electronic system, and to reduce the size and cost of an electronic device incorporating the information processing device. Can proceed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a data write position changing unit.

FIG. 3 is a diagram showing a configuration of a conventional example.

FIG. 4 is a flowchart showing a flow of an operation of a conventional example.

FIG. 5 is an explanatory diagram of an instruction form.

FIG. 6 is an explanatory diagram of an instruction form.

[Explanation of symbols]

1, 3 Data path 2, 4 Control unit 10 Program counter 11 Instruction memory 12a, 12b Adders 13a, 13b, 13c, 22, 23, 24 Selector 14 Sign extension circuit 15 Register file 16 Arithmetic and logical operation unit 17 Data memory 18, 40 instruction decoder 19 continuous write detection unit 20 data write position change unit 21a, 21b, 21c, 21d, 21e pipeline register 25a, 25b, 25c, 25d register 26 counting unit 27 write signal generation unit

Claims (2)

[Claims] 1. An information processing apparatus comprising: a control unit that decodes a given instruction and generates a control signal; and an execution unit that executes a process in accordance with the control signal generated by the control unit. The control unit has a continuous write detection unit that detects that a processing result based on the immediate data is continuously written to a write area specified by the same operand, and the execution unit includes: Based on the detection result of the continuous write detection unit, according to the number of consecutive writes, a data write position change unit that switches the write position in the write area, according to the change result in the data write position change unit An information processing apparatus comprising: a data writing unit that writes a processing result based on the immediate data in the writing area. 2. The data write position change unit, based on a detection result of the continuous write detection unit, determines the number of times that a write operation is continuously performed on a write area performed by the same operand. A counting unit for counting,
In a given instruction, a plurality of registers having the same bit length as the bit length of the immediate data that can be directly specified, and a register for capturing a processing result based on the immediate data in accordance with the counting result in the counting unit are provided. 2. The information processing apparatus according to claim 1, further comprising: a selection unit that selects each bit portion of the processing result; and a write signal generation unit that generates a write enable signal for a register selected by the selection unit.