JPH118371A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen customizing process by providing element units or connecting holes reaching these units from the chip top face, filling a conductive material in the holes with exposing part of each unit in the hole, to thereby bring the element units into an electrical continuity with wiring units located above them or adjacent wiring units. SOLUTION: Conductors fill connecting holes 21 and different phase wiring connecting holes 23, to bring a first layer wiring 2 into continuity with a diffusion 92 through the holes 21 and the wiring 2 into continuity with a second layer wiring 3 through the holes 23. Nondoped polysilicon 4' controls the depth of the holes 23. W fills the connection holes 21-24. The holes 22 connect the first layer wirings, and nondoped polysilicon 4 controls the depth of the holes 22. The holes 24 connect second layer wirings 3. Polysilicon 5 controls the depth of the holes 24. Thus it is possible to customize, by changing only the masks for the connection holes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device having a basic cell region in which basic cells are arranged in an array in a chip.

[0002]

2. Description of the Related Art As seen in a gate array, a plurality of wiring process customizing masks have been created based on the result of arrangement and wiring corresponding to a desired circuit, and a customizing process has been performed after a contact through hole.

[0003]

In such a prior art, a large number of customization masks and a large number of customization processes require an increase in development costs and a delivery time of one week or more of prototypes.

[0004]

In order to solve the above-mentioned problems, a semiconductor integrated circuit device according to the present invention has an element unit group provided on a semiconductor chip and a wiring unit group provided thereon. The element unit group and the wiring unit group are insulated from each other, the wiring units are also insulated from each other, and electrical continuity between an arbitrary element unit and a wiring unit located above the arbitrary element unit is determined from the chip upper surface. A connection hole reaching an arbitrary element unit is provided at a position where a part of the wiring of the wiring unit located above is exposed in the connection hole, and is taken by embedding a conductive material in the connection hole. The electrical continuity between each other is achieved by providing a wiring connection hole reaching the wiring unit from the upper surface of the chip at a position where a part of the adjacent wiring unit is exposed in the wiring connection hole, and embedding a conductive material in the wiring connection hole. Taking Wherein the wiring unit is composed of two or more mutually insulated wiring layers, and the electrical continuity between the mutually insulated wiring layers is formed by a different-layer wiring connection hole reaching the wiring unit from the upper surface of the chip. A part of wiring layers insulated from each other is provided at a position exposed to each of the different-layer wiring connection holes, and is taken by embedding a conductive material in the different-layer wiring connection holes. When opening the connection hole, the wiring connection hole and the hetero-phase wiring connection hole between the element unit group and the lowermost wiring layer at the position where the connection hole may be taken, the etching rate of the protective film and the interlayer film may be lower than the etching rate. An insulating material or a high resistance material having a low etch rate is provided.

[0005]

In the semiconductor integrated circuit device configured as described above, since only the connection holes, the wiring connection holes, and the different-phase wiring connection holes are customized, the pattern of the wiring layer can be the same even in different logic circuits. .

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described in detail. FIG. 1 shows an example of a wiring unit according to the present invention.

The first layer wiring 2, the second layer wiring 3 insulated from the first layer 3, the non-doped polysilicon 4, which is lower in etch rate than the interlayer film located below the first layer wiring and is almost an insulator, and 4 'is made of non-doped polysilicon 5 provided between the first layer wiring and the second layer wiring.
FIG. 2 shows that the wiring units of the present invention are arranged in two rows and two columns,
This figure shows the positional relationship between the first and second wiring connection holes 22, the second wiring connection holes 24, and the different-phase wiring connection holes 23 between the first and second layers. FIG. 9 is a cross-sectional view taken along the line AA ′ in FIG. 2. A conductor is embedded in each of the connection hole 21 and the out-of-phase wiring connection hole 23. And the out-of-phase wiring connection hole 23
Indicates electrical continuity between the first layer wiring and the second layer wiring. The depth of the out-of-phase wiring connection hole 23 is controlled by the non-doped polysilicon 4 'provided. Connection holes 21, 22,
Tungsten is simultaneously buried in 23 and 24 by using a blanket W-CVD method and etch back. In the future, a method of filling aluminum with lower resistance is conceivable. FIG. 10 shows a cross section taken along the line BB ′ in FIG.
The depth of the first-layer wiring connection hole 22 is controlled by the non-doped polysilicon 4 provided. FIG. 11 shows a cross section taken along the line CC ′ in FIG. 2, and the second-layer wirings 3 are connected to each other by the second-layer wiring connection holes 24, and the second-layer wiring connection holes 2 are formed.
The depth 4 is controlled by non-doped polysilicon 5.

FIG. 7 shows an element unit 71. P type diffusion region 73, N type diffusion region 74, polysilicon gate 72, N
It comprises a diffusion region (guard ring) 75 and a P-type diffusion region (guard ring) 76. FIG. 8 shows an element unit 7
This is an example in which 1 is arranged in 3 rows and 6 columns. Such an element unit group is used for a gate array or an embedded ASIC.

FIG. 3 shows a pattern on a library of a two-input NAND in a conventional example, and FIG. 4 shows an actual use example of a two-input NAND. Second-layer wirings 41, 42, and 43 provided by automatic arrangement wiring and the like are connected to the respective inputs and outputs of the two-input NAND through through-holes 44, and are connected to the inputs and outputs of the other arranged libraries. Form a circuit.

FIG. 5 shows a wiring unit 1 according to the present invention as an element unit 71.
This is an example of the arrangement above. A second-layer wiring 51 is arranged on the VDD wiring 31 and the VSS wiring 32. FIG. 6 is a diagram obtained by replacing the conventional example shown in FIG. 4 with the present invention shown in FIG. VDD connection hole 61 and VSS connection hole 62
Has the same structure as the connection hole 21 and supplies a potential to the element.

[0011]

According to the semiconductor integrated circuit device of the present invention, customization only requires changing the mask of the connection hole, which leads to a reduction in development costs. The customization process becomes extremely short, and the delivery time can be remarkably reduced to about 2 to 3 days. In addition, since all of the connection holes selectively opened from the upper surface of the chip are filled with the conductor, there is an effect that a decrease in long-term reliability can be suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a wiring unit of the present invention.

FIG. 2 is an explanatory view of the arrangement of wiring units according to the present invention.

FIG. 3 is a diagram showing an example of a pattern in a conventional two-input NAND library.

FIG. 4 is a diagram showing a wiring example for a conventional two-input NAND.

FIG. 5 is a diagram showing an arrangement example of wiring units with respect to element units according to the present invention.

FIG. 6 is a diagram in which the conventional example of FIG. 4 is replaced with the present invention.

FIG. 7 is a diagram showing a conventional element unit.

FIG. 8 is a diagram showing a conventional arrangement in element units.

FIG. 9 is a sectional view taken along line A-A ′ of FIG. 2 of the present invention.

FIG. 10 is a sectional view taken along the line B-B ′ in FIG. 2 of the present invention.

FIG. 11 is a sectional view taken along the line C-C ′ in FIG. 2 of the present invention.

[Explanation of symbols]

1: wiring unit 2: first-layer wiring 3: second-layer wiring 4, 4 ': non-doped polysilicon below the first-layer wiring 5: non-doped polysilicon below the second-layer wiring 21: first-layer Connection hole between wiring and diffusion (or gate / poly) 22: Wiring connection hole for connecting first layer wiring 23: Out-of-phase wiring connection hole for connecting first layer wiring and second layer wiring 24: Second layer Wiring connection holes for connecting the wirings 31: VDD power supply wiring 32: VSS power supply wiring 33: 2-input NAND output pin (first-layer wiring) 34: diffusion contact 34 ': gate contact 35: 2-input NAND input pin 41, 42 : Connection wiring to the input pin of the 2-input NAND (second-layer wiring) 43: Connection wiring to the output pin of the 2-input NAND (second-layer wiring) 44: Through hole 51: 2 provided on the power supply wiring Layer wiring 6 , 61 ′: power supply connection hole 71: element unit 72: polysilicon gate 73: P-type diffusion region 74: N-type diffusion region 75: N-type diffusion region (guard ring) 76: P-type diffusion region (guard ring) 91: semiconductor substrate 92: diffusion region 93: silicon dioxide

Claims (3)

[Claims] 1. A semiconductor integrated circuit device having an element unit group disposed on a semiconductor chip, comprising: a wiring unit group disposed on the element unit group; The unit group is insulated, the wiring units are also insulated from each other, and the electrical continuity between the arbitrary element unit and the wiring unit located above the arbitrary element unit is set to a connection hole reaching the arbitrary element unit from the upper surface of the chip. A part of the wiring of the wiring unit located above is provided at a position exposed in the connection hole and is taken by embedding a conductive material in the connection hole. A wiring connection hole reaching the wiring unit is provided by providing a part of the adjacent wiring unit at a position where each of the adjacent wiring units is exposed in the wiring connection hole and embedding a conductive material in the wiring connection hole. Body integrated circuit device. 2. The wiring unit is composed of two or more mutually insulated wiring layers, and the electrical continuity between the mutually insulated wiring layers is established by connecting different layer wiring connection holes reaching the wiring unit from the upper surface of the chip. 2. The semiconductor integrated circuit according to claim 1, wherein a part of the insulated wiring layer is provided at a position exposed in each of the different-layer wiring connection holes, and is taken by embedding a conductive material in the different-layer wiring connection holes. Circuit device. 3. The connection hole and the wiring connection between the element unit group and the lowermost wiring layer at a position where the wiring connection hole according to the above item 1 and the out-of-phase wiring connection hole according to the above item 2 may be taken. 3. The insulating material according to claim 1, wherein an insulating material or a high-resistance material having a lower etching rate than an etching rate of the protective film and the interlayer film when the hole and the hetero-phase wiring connection hole are formed is provided. Semiconductor integrated circuit device.