JPH118364A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form fin-like lower electrodes which are composed of first-third conductive films while avoiding short-circuit, etc., to ensure insulation, as designed by preventing a first insulation film from corrosion, using a third (second) insulation film and first conductive film and etching off the second (third) insulation film. SOLUTION: Storage node electrodes 22 of memory capacitors are formed with polycrystalline Si films 14, 16 having intricate fin-like internal structures, sidewalls 19 are formed to increase the surface area of the electrode 22 in a narrow plane, Si oxide films 13, 15 in a lower electrode pattern 17 are wet etched off, while an Si nitride film 20 and polycrystalline Si film 12 are used as an etch stopper for preventing a planarized film 10 from being corroded by an etching liq., thereby suppressing the short circuit of bit lines embedded in the film 10 with upper wirings. Thus it is possible to sufficiently insulate the storage node electrodes 22 and form them as designed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and is particularly suitable for application to a semiconductor memory device having a memory capacitor such as a DRAM.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor devices have been progressing. Accordingly, in a DRAM which is a typical semiconductor memory device, a lower electrode (storage node electrode) and an upper electrode (cell plate electrode) are made of a dielectric material in order to increase the effective memory cell capacity of the memory capacitor. A so-called stack type memory capacitor which is arranged to face through a film is widely used. In such a memory capacitor, the capacity of the memory cell is determined by the facing area of the storage node electrode and the cell plate electrode.

[0003]

However, DRA
As the miniaturization and the degree of integration of M further progress, the occupied area of the memory capacitor decreases, while the storage capacity required for the memory capacitor remains unchanged. Therefore, in order to increase the effective opposing area between the storage node electrode and the cell plate electrode, the thickness of the storage node electrode must be increased. Then, due to a step between the memory cell portion and its peripheral circuit portion, which is caused mainly by the height of the memory capacitor, a resolution failure is likely to occur in photolithography performed in a later process.

A technique capable of solving the above-mentioned problem is disclosed in Japanese Unexamined Patent Publication No.
It is disclosed in JP-A-326267. This technology provides a DRAM in which storage node electrodes are formed in a hierarchical structure and the exposed surfaces of the layers are used for capacitive coupling, and the effective capacitance can be increased without increasing the occupied plane area. .

However, in Japanese Patent Application Laid-Open No. Hei 6-326267, when manufacturing the above-described DRAM, a multi-layered polycrystalline silicon film is laminated via an insulating film and patterned to form an insulating film between the polycrystalline silicon films. In the step of removing, there is a high possibility that the interlayer insulating film is eroded during wet etching and reaches the bit line buried in the interlayer insulating film. In this case, a short circuit occurs between the upper electrode formed in a later step and the bit line, which is inconvenient.

Accordingly, an object of the present invention is to respond to recent demands for further miniaturization and higher integration of semiconductor devices, while suppressing the occurrence of steps by reducing the size and height of capacitors. It is another object of the present invention to provide a semiconductor memory device and a method of manufacturing the same, which can realize a sufficient storage capacitance while ensuring the reliability of suppressing short circuits between wirings.

[0007]

According to a method of manufacturing a semiconductor memory device of the present invention, an access transistor having a gate, a source, and a drain, and a lower electrode and an upper electrode are capacitively coupled to each other via a dielectric film. A method of manufacturing a semiconductor memory device including a memory capacitor, comprising: a first step of forming a first insulating film covering the access transistor; and forming a part of a surface of the source on the first insulating film. A second step of forming an opening exposing the first insulating film, a third step of forming a first conductive film buried in the opening on the first insulating film and connected to the source, A second insulating film and a second conductive film on at least one conductive film;
A fourth step of alternately forming layers, a fifth step of patterning the first conductive film, the second insulating film, and the second conductive film to form an island-like lower electrode pattern;
A sixth step of forming a third conductive film covering side surfaces of the lower electrode pattern, and a surface of the first insulating film exposed between the third conductive films covering adjacent side surfaces of the lower electrode pattern A seventh step of forming a third insulating film so as to cover the entire surface including the first step, and an eighth step of processing the lower electrode pattern to form a groove exposing a part of the surface of the first conductive film. A step of removing the second insulating film through the groove in a state where the third insulating film is present, and then removing the third insulating film to form the lower electrode; The first conductive film, the second conductive film, and the third conductive film.
A tenth step of forming a fourth insulating film to be the dielectric film so as to cover an exposed surface including the inside of the groove of the conductive film, and a step of forming the upper electrode to cover the dielectric film. And an eleventh step of forming the fourth conductive film.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the third insulating film is an acid-resistant film,
In the ninth step, after the second insulating film is removed through the groove by the first wet etching by using the third insulating film as an etching stopper, the etching rate is higher than that of the first wet etching. The third insulating film is removed by the first wet etching having a large thickness.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the third insulating film is a silicon nitride film.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the first insulating film includes an interlayer insulating film;
It is formed in a two-layer structure with a flattening film whose upper surface is flattened.

A method of manufacturing a semiconductor memory device according to the present invention includes an access transistor having a gate, a source, and a drain, and a memory capacitor in which a lower electrode and an upper electrode are capacitively opposed to each other via a dielectric film. A method for manufacturing a semiconductor memory device, comprising: a first step of forming a first insulating film covering the access transistor; and a second step of forming a second insulating film on the first insulating film. Forming a hole in the first insulating film and the second insulating film to expose a part of the surface of the source; and forming the hole on the second insulating film. A fourth step of forming a first conductive film connected to the buried source, and a third insulating film and a second conductive film alternately formed on the first conductive film by at least one layer at a time. A fifth step, the first conductive film, A sixth step of patterning the third insulating film and the second conductive film to form a lower electrode pattern, a seventh step of forming a third conductive film covering side surfaces of the lower electrode pattern, An eighth step of processing an electrode pattern to form a groove exposing a part of the surface of the first conductive film, and a step of forming a groove between the third conductive films adjacent to the third conductive film. A ninth step of removing the third insulating film and forming the lower electrode; and an exposed surface of the first conductive film, the second conductive film, and the third conductive film including the inside of the groove. A fourth layer which becomes the dielectric film so as to cover
A tenth step of forming an insulating film, and an eleventh step of forming a fourth conductive film serving as the upper electrode so as to cover the dielectric film.

In one embodiment of the method of manufacturing a semiconductor memory device according to the present invention, the second insulating film is an acid-resistant film,
In the ninth step, the third insulating film is removed through the groove by first wet etching using the second insulating film as a stopper.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the second insulating film is a silicon nitride film.

In one embodiment of the method for manufacturing a semiconductor memory device according to the present invention, the first insulating film is formed by an interlayer insulating film;
It is formed in a two-layer structure with a flattening film whose upper surface is flattened.

A semiconductor memory device according to the present invention includes: an access transistor having a gate, a source, and a drain; and a memory capacitor, in which a lower electrode and an upper electrode are capacitively coupled to each other via a dielectric film to face each other. The device, wherein the lower electrode extends laterally on the first insulating film covering the access transistor and is connected to the lower layer source, and upward from an edge of the bottom wall. It has an umbrella-shaped fin-shaped side wall having an intricate inner surface, and the upper portion is formed in a grooved shape.The dielectric film is formed from the outer surface of the side wall to the side wall and the side wall. The upper electrode is formed so as to cover the inner surface of the bottom wall portion, and the upper electrode is formed so as to cover the lower electrode via the dielectric film, and is formed at least on the interlayer insulating film. Having acid resistance of the second insulating film between the lower electrode that.

In one embodiment of the semiconductor memory device according to the present invention, the second insulating film is made of a silicon nitride film.

[0017]

In the method of manufacturing a semiconductor memory device according to the present invention, when removing the second insulating film (third insulating film) existing in the island-like lower electrode pattern in the ninth step, the second insulating film is adjacent to the lower electrode pattern. The surface of the first insulating film between the lower electrode patterns is covered with a third insulating film (second insulating film), and the first conductive film also exists on the bottom surface in the lower electrode pattern. That is, at this time, the first insulating film is not exposed, and the second insulating film (the third insulating film) is not exposed.
The third insulating film (second insulating film) and the first conductive film serve as stoppers when wet etching or the like for removing the first insulating film is performed to protect the first insulating film and prevent erosion. You. Therefore, the first to third conductive films are formed by alternately stacking the second insulating film and the second conductive film to form a hierarchical structure, and removing the second insulating film (third insulating film). The fin-shaped lower electrode having a large surface area and having a large surface area can be formed as designed while preventing a short circuit or the like and ensuring sufficient insulation.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some specific embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) First, a first embodiment will be described. In the first embodiment,
A so-called COB (Capacitor Ov) in which an access transistor and a memory capacitor are provided as a semiconductor memory device, and the memory capacitor is formed substantially above a bit line.
The structure of the DRAM will be described together with a manufacturing method. 1 to 5 are schematic sectional views showing a method of manufacturing the DRAM of the first embodiment in the order of steps.

First, as shown in FIG.
A field oxide film 3 is formed as a device isolation structure on a silicon semiconductor substrate 1 of a mold by a so-called LOCOS method to define a device formation region 2. Instead of the field oxide film 3, a conductive film is buried in the oxide film by a field shield element isolation method, and a portion of the silicon semiconductor substrate immediately below is fixed to a predetermined potential by the conductive film to perform element isolation. May be formed.

Subsequently, the surface of the silicon semiconductor substrate 1 in the element formation region 2 which is separated from each other by the field oxide film 3 and relatively defined is thermally oxidized to form a silicon oxide film. A polycrystalline silicon film doped with an n-type impurity such as phosphorus (P) is deposited and formed.

Subsequently, the silicon oxide film and the polycrystalline silicon film are patterned by photolithography and subsequent dry etching to leave the silicon oxide film and the polycrystalline silicon film in the element formation region 2 in the form of an electrode. And a gate electrode 5 are formed.

Subsequently, the photoresist used for patterning is removed by ashing, and a silicon oxide film is deposited and formed on the entire surface including the upper surface of the gate electrode 5 by the CVD method. Etching is performed to form a sidewall 6 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 4 and the gate electrode 5.

Subsequently, using the gate electrode 5 and the side wall 6 as a mask, an n-type impurity such as phosphorus (P) is introduced into the surface region of the silicon semiconductor substrate 1 on both sides of the gate electrode 5 by ion implantation. A source 7 and a drain 8 which are diffusion layers are formed, and an access transistor having the gate electrode 5 and a pair of impurity diffusion layers 7 is completed.

Next, as shown in FIG. 1B, CV is applied to the entire surface of the silicon semiconductor substrate 1 including the field oxide film 3.
A silicon oxide film is deposited and formed by the D method, and an interlayer insulating film 9 is formed.
To form

Subsequently, a bit line (not shown) electrically connected to the drain 8 which is one of the impurity diffusion layers is formed in the interlayer insulating film 8 by patterning, and a borophosphate silicate is formed on the interlayer insulating film 9 (and the bit line). A flattening layer 10 made of glass (BPSG) or the like is deposited and formed by a CVD method.

Next, as shown in FIG. 1C, the flattening layer 10 and the interlayer insulating film 9 are patterned to expose a part of the surface of the source 7 which is the other impurity diffusion layer. To form

Next, as shown in FIG. 2A, after the photoresist used for patterning is removed by ashing, the storage contact holes 11 are buried on the flattening layer 10 by low-pressure CVD. Polycrystalline silicon film 1
Form 2

Then, as shown in FIG. 2B, a silicon oxide film 13, a polycrystalline silicon film 14, a silicon oxide film 15, and a polycrystalline silicon film 16 are sequentially deposited on the polycrystalline silicon film 12. Here, the silicon oxide film 1
In the low-pressure CVD process for forming the polycrystalline silicon films 12, 14, 16 in the low-pressure CVD process for forming the polycrystalline silicon films 12, 14, 16,
SiH ₄ gas is used as a source gas.

Next, as shown in FIG. 2C, the polycrystalline silicon film 16, the silicon oxide film 15, the polycrystalline silicon film 14, the silicon oxide film 13, and the polycrystalline silicon film 12 are formed.
Is patterned to form an island-like lower electrode pattern 17 corresponding to each storage contact hole 11. Specifically, dry etching at the time of patterning is performed at 5 Torr using an etching gas such as CF _4.
The lower electrode pattern 17 having a shape following the pattern of the photoresist is formed by performing the process at a predetermined pressure below a predetermined temperature of 100 ° C. or lower for about 3 minutes.

Next, as shown in FIG. 3A, after the photoresist used for patterning is removed by ashing, the lower electrode pattern is formed by low-pressure CVD using SiH ₄ gas as a source gas. A polycrystalline silicon film 18 is deposited and formed on the entire surface including the space 17.

Next, as shown in FIG. 3B, the entire surface of the polycrystalline silicon film 18 is anisotropically etched at a predetermined pressure of 5 Torr or less at a predetermined temperature of 100 ° C. or less for about 1 minute, thereby forming a lower electrode. The polycrystalline silicon film 18 is left only on the side surface of the pattern 17,
To form Here, in the above-described step of forming the lower electrode pattern 17, if the width between the adjacent lower electrode patterns 17 is formed to the size of the exposure limit of the photolithography, the sidewalls 19 covering the side surfaces of the adjacent lower electrode patterns 17 are formed. The width between them can be made smaller than the exposure limit.

Next, as shown in FIG.
An acid-resistant thin film, here, a silicon nitride film 20 is formed on the entire surface by the VD method. Specifically, using a mixed gas of SiH ₂ Cl ₄ and NH ₃ as a source gas, the side wall 1 formed on the adjacent lower electrode pattern 17 is formed.
A silicon nitride film 20 is formed so as to cover the entire surface including the flattening film 11 exposed between the portions 9.

Next, as shown in FIG. 4A, a substantially central portion of the silicon nitride film 20 and the lower electrode pattern 17 is patterned to form a groove 21 for exposing a part of the surface of the polycrystalline silicon film 12 on the bottom surface. Form. Specifically, dry etching at the time of patterning is performed by using an etching gas such as CF _{4 at} a predetermined pressure of 5 Torr or less.
By performing the process at a predetermined temperature of 00 ° C. or less for about 2 minutes, a groove 21 having a shape following the pattern of the photoresist is formed.

Next, as shown in FIG. 4B, after the photoresist used for patterning is removed by ashing, the silicon oxide films 13 and 15 are removed by wet etching through the groove 21. Specifically, 0.1% of B
The silicon oxide films 13 and 15 in the lower electrode pattern 17 are completely removed by performing wet etching for about 10 minutes using an etchant containing HF.

Here, the surface of the flattening film 11 between the adjacent lower electrode patterns 17 is covered with the silicon nitride film 20, and the polycrystalline silicon film 12 also exists on the bottom surface in the lower electrode pattern 17. That is, the flattening film 11 is not exposed at this time, and the silicon nitride film 20 and the polycrystalline silicon film 12 serve as stoppers when wet etching for removing the silicon oxide films 13 and 15 is performed.
Is protected, and erosion of the flattening film 11 by the etchant is prevented.

Next, as shown in FIG. 4C, the silicon nitride film 20 is removed by wet etching. Specifically, the silicon nitride film 20 is completely removed by performing wet etching for about 5 minutes using hot phosphoric acid at a temperature of 100 ° C. or higher. At this time,
An intricate fin-shaped storage node electrode 22 composed of the polycrystalline silicon films 12, 14, 16 and the sidewall 19 is completed.

Next, as shown in FIG. 5, a predetermined pressure is applied to the surface of the storage node electrode 22 by low pressure CVD in a thermal oxidation furnace using a mixed gas of SiH ₂ Cl ₄ and NH ₃ as a source gas. A silicon oxide film, a silicon nitride film, and a silicon oxide film having a thickness are sequentially formed to form a dielectric film 23 made of an ONO film covering the surface.

Subsequently, a polycrystalline silicon film is deposited so as to bury the storage node electrode 22, and the dielectric film 2 is formed.
3, a cell plate electrode 24 facing the surface of the storage node electrode 22 is formed, and a memory capacitor including the storage node electrode 22, the dielectric film 23 and the cell plate electrode 24 is completed.

Thereafter, although not shown, further formation of an interlayer insulating film, formation of a contact hole and subsequent formation of a wiring layer, and formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion And the like are often formed sequentially.), Etc., to complete the DRAM.

In the DRAM manufactured through the above-described steps, the storage node electrode 22 of the memory capacitor has a polycrystalline silicon film 1 in an intricate fin shape.
4 and 16 are formed, and furthermore, by forming the side wall 19, the interval between the adjacent storage node electrodes 22 is reduced to, for example, a narrow gap smaller than the exposure limit of photolithography. Therefore, the surface area of the storage node electrode 22 can be increased within a narrow plane area.

When the silicon oxide films 13 and 15 in the lower electrode pattern 17 are removed by wet etching, the silicon nitride film 20 and the polycrystalline silicon film 12 serve as etching stoppers. Is prevented, and a short circuit with an upper wiring such as a bit line buried in the flattening film 11 is suppressed.

That is, according to the first embodiment, the polycrystalline silicon films 12, 14, 16 and the silicon oxide films 13, 1
5 are alternately stacked to form a hierarchical structure, and by removing the silicon oxide films 13 and 15, the polycrystalline silicon films 12 and
The intricate fin-shaped storage node electrodes 22 having a large surface area composed of 14 and 16 can be formed as designed while preventing a short circuit or the like and ensuring sufficient insulation.

(Second Embodiment) First, a second embodiment will be described. In this second embodiment,
As in the case of the first embodiment, a DRAM having a COB (Capacitor Over Bitline) structure is exemplified as a semiconductor memory device, but differs in that a step of forming an acid-resistant thin film (silicon nitride film) and a formation site are different. Also in the second embodiment, the configuration of the DRAM will be described together with the manufacturing method. 6 to 9 are schematic cross-sectional views showing a method of manufacturing the DRAM of the second embodiment in the order of steps. Note that the same reference numerals are given to components and the like corresponding to the DRAM described in the first embodiment.

First, as shown in FIG.
A field oxide film 3 is formed as a device isolation structure on a silicon semiconductor substrate 1 of a mold by a so-called LOCOS method to define a device formation region 2. Instead of the field oxide film 3, a conductive film is buried in the oxide film by a field shield element isolation method, and a portion of the silicon semiconductor substrate immediately below is fixed to a predetermined potential by the conductive film to perform element isolation. May be formed.

Next, the surface of the silicon semiconductor substrate 1 in the element formation region 2 which is separated from each other by the field oxide film 3 and is relatively defined is thermally oxidized to form a silicon oxide film. A polycrystalline silicon film doped with an n-type impurity such as (P) is deposited and formed.

Next, the silicon oxide film and the polycrystalline silicon film are patterned by photolithography and subsequent dry etching to leave the silicon oxide film and the polycrystalline silicon film in the element formation region 2 in the form of an electrode. The gate electrode 5 is formed.

Next, after the photoresist used for patterning is removed by ashing, a silicon oxide film is deposited and formed on the entire surface including on the gate electrode 5 by CVD, and the entire surface of the silicon oxide film is made anisotropic. Etching is performed to form a sidewall 6 while leaving the silicon oxide film only on the side surfaces of the gate oxide film 4 and the gate electrode 5.

Next, n-type impurities such as phosphorus (P) are introduced by ion implantation into the surface regions of the silicon semiconductor substrate 1 on both sides of the gate electrode 5 using the gate electrode 5 and the sidewalls 6 as a mask, and a pair of impurity diffusions The source 7 and the drain 8 which are layers are formed, and an access transistor having the gate electrode 5 and the pair of impurity diffusion layers 7 is completed.

Next, as shown in FIG. 6B, CV is applied to the entire surface of the silicon semiconductor substrate 1 including the field oxide film 3.
A silicon oxide film is deposited and formed by the D method, and an interlayer insulating film 9 is formed.
To form

Subsequently, a bit line (not shown) electrically connected to the drain 8 which is one of the impurity diffusion layers is formed in the interlayer insulating film 8 by patterning, and a borophosphate silicate is formed on the interlayer insulating film 9 (and the bit line). A flattening layer 10 made of glass (BPSG) or the like is deposited and formed by a CVD method.

Subsequently, SiH ₂ C is formed by low pressure CVD.
Using a mixed gas of l ₄ and NH ₃ as a source gas,
An acid-resistant thin film, here, a silicon nitride film 31 is formed on the planarization layer 10.

Subsequently, as shown in FIG. 6C, the planarizing layer 10, the interlayer insulating film 9 and the silicon nitride film 31 are patterned to remove a part of the surface of the source 7 which is the other impurity diffusion layer. A storage contact hole 11 to be exposed is formed.

Next, as shown in FIG. 7A, after removing the photoresist used for patterning by ashing, the storage contact holes 11 are buried on the silicon nitride film 31 by low-pressure CVD. A polycrystalline silicon film 12 is formed.

Next, as shown in FIG. 7B, a silicon oxide film 13, a polycrystalline silicon film 14, a silicon oxide film 15, and a polycrystalline silicon film 16 are sequentially deposited on the polycrystalline silicon film 12. Here, the silicon oxide film 1
In the low-pressure CVD process for forming the polycrystalline silicon films 12, 14, 16 in the low-pressure CVD process for forming the polycrystalline silicon films 12, 14, 16,
SiH ₄ gas is used as a source gas.

Next, as shown in FIG. 7C, the polycrystalline silicon film 16, the silicon oxide film 15, the polycrystalline silicon film 14, the silicon oxide film 13, and the polycrystalline silicon film 12 are formed.
Is patterned to form an island-like lower electrode pattern 17 corresponding to each storage contact hole 11. Specifically, dry etching at the time of patterning is performed at 5 Torr using an etching gas such as CF _4.
The lower electrode pattern 17 having a shape following the pattern of the photoresist is formed by performing the process at a predetermined pressure below a predetermined temperature of 100 ° C. or lower for about 3 minutes.

Next, as shown in FIG. 8A, after the photoresist used for patterning is removed by ashing, the adjacent lower electrode pattern is formed by low pressure CVD using SiH ₄ gas as a source gas. A polycrystalline silicon film 18 is deposited and formed on the entire surface including the space 17.

Next, as shown in FIG. 8B, the entire surface of the polycrystalline silicon film 18 is anisotropically etched at a predetermined pressure of 5 Torr or less at a predetermined temperature of 100 ° C. or less for about 1 minute, thereby forming a lower electrode. The polycrystalline silicon film 18 is left only on the side surface of the pattern 17,
To form Here, in the above-described step of forming the lower electrode pattern 17, if the width between the adjacent lower electrode patterns 17 is formed to the size of the exposure limit of the photolithography, the sidewalls 19 covering the side surfaces of the adjacent lower electrode patterns 17 are formed. The width between them can be made smaller than the exposure limit.

Next, as shown in FIG. 8C, the substantially central portion of the lower electrode pattern 17 is patterned to expose a part of the surface of the polycrystalline silicon film 12 on the bottom surface.
Form one. Specifically, by performing dry etching at the time of patterning at a predetermined pressure of 5 Torr or less at a predetermined temperature of 100 ° C. or less for about 2 minutes using an etching gas such as CF ₄ , the shape following the pattern of the photoresist is obtained. A groove 21 is formed.

Next, after removing the photoresist used for patterning by ashing, the silicon oxide films 13 and 15 are removed by wet etching through the groove 21 as shown in FIG. Specifically, 0.1% of B
The silicon oxide films 13 and 15 in the lower electrode pattern 17 are completely removed by performing wet etching for about 10 minutes using an etchant containing HF. At this time, an intricate fin-shaped storage node electrode 22 composed of the polycrystalline silicon films 12, 14, 16 and the sidewall 19 is completed.

Here, the surface of the flattening film 11 between the adjacent lower electrode patterns 17 is covered with the silicon nitride film 31, and the polycrystalline silicon film 12 also exists on the bottom surface in the lower electrode pattern 17. That is, at this time, the flattening film 11 is not exposed, and the silicon nitride film 31 and the polycrystalline silicon film 12 serve as stoppers when wet etching for removing the silicon oxide films 13 and 15 is performed.
Is protected, and erosion of the flattening film 11 by the etchant is prevented.

Next, as shown in FIG.
In a thermal oxidation furnace using a mixed gas of SiH ₂ Cl ₄ and NH ₃ as a source gas, a silicon oxide film having a predetermined thickness is formed on the surface of the storage node electrode 22 by a VD method.
A silicon nitride film and a silicon oxide film are sequentially formed to form a dielectric film 23 made of an ONO film covering the surface.

Subsequently, a polycrystalline silicon film is deposited and buried so as to bury the storage node electrode 22, and the dielectric film 2 is formed.
3, a cell plate electrode 24 facing the surface of the storage node electrode 22 is formed, and a memory capacitor including the storage node electrode 22, the dielectric film 23 and the cell plate electrode 24 is completed.

Thereafter, although not shown, further formation of an interlayer insulating film, formation of a contact hole and subsequent formation of a wiring layer, and formation of a peripheral circuit portion of a memory cell portion (this peripheral circuit portion is a memory cell portion And the like are often formed sequentially.), Etc., to complete the DRAM.

In the DRAM manufactured through the above-described steps, the storage node electrode 22 of the memory capacitor has a polycrystalline silicon film 1 in an intricate fin shape.
4 and 16 are formed, and furthermore, by forming the side wall 19, the interval between the adjacent storage node electrodes 22 is reduced to, for example, a narrow gap smaller than the exposure limit of photolithography. Therefore, the surface area of the storage node electrode 22 can be increased within a narrow plane area.

When the silicon oxide films 13 and 15 in the lower electrode pattern 17 are removed by wet etching, the silicon nitride film 31 and the polycrystalline silicon film 12 serve as an etching stopper. Is prevented, and a short circuit with an upper wiring such as a bit line buried in the flattening film 11 is suppressed.

That is, according to the second embodiment, the polycrystalline silicon films 12, 14, 16 and the silicon oxide films 13, 1
5 are alternately stacked to form a hierarchical structure, and by removing the silicon oxide films 13 and 15, the polycrystalline silicon films 12 and
The intricate fin-shaped storage node electrodes 22 having a large surface area composed of 14 and 16 can be formed as designed while preventing a short circuit or the like and ensuring sufficient insulation.

[0068]

According to the present invention, in response to recent demands for further miniaturization and higher integration of semiconductor devices, the size of the capacitor is reduced and the height is reduced to suppress the occurrence of steps. In addition, it is possible to realize a sufficient storage capacitance while ensuring the reliability of suppressing the short circuit between the wirings.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method for manufacturing a DRAM according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view showing a manufacturing method of the DRAM according to the first embodiment of the present invention in the order of steps, following FIG. 1;

FIG. 3 is a schematic cross-sectional view showing a manufacturing method of the DRAM according to the first embodiment of the present invention in the order of steps, following FIG. 2;

FIG. 4 is a schematic cross-sectional view showing a manufacturing method of the DRAM according to the first embodiment of the present invention in the order of steps, following FIG. 3;

FIG. 5 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the first embodiment of the present invention in the order of steps, following FIG. 4;

FIG. 6 is a schematic cross-sectional view showing a method for manufacturing a DRAM according to a second embodiment of the present invention in the order of steps.

FIG. 7 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the second embodiment of the present invention in the order of steps, following FIG. 6;

FIG. 8 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the second embodiment of the present invention in the order of steps, following FIG. 7;

FIG. 9 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the second embodiment of the present invention in the order of steps, following FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Element formation area 3 Field oxide film 4 Gate oxide film 5 Gate electrode 6 Side wall 7 (made of a silicon oxide film) 7 Source 8 Drain 9 Interlayer insulating film 10 Flattening film 11 Storage contact hole 12, 14, 16 , 18 Polycrystalline silicon film 13, 15 Silicon oxide film 17 Lower electrode pattern 19 Side wall (comprising polycrystalline silicon film) 20, 31 Silicon nitride film 21 Groove 22 Storage node electrode 23 Dielectric film 24 Cell plate electrode

Claims (10)

[Claims] 1. A method for manufacturing a semiconductor memory device, comprising: an access transistor having a gate, a source, and a drain; and a memory capacitor in which a lower electrode and an upper electrode are capacitively opposed to each other via a dielectric film. A first step of forming a first insulating film covering the access transistor; a second step of forming an opening in the first insulating film to expose a part of the surface of the source; Forming a first conductive film connected to the source by burying the opening on the insulating film; and forming a second insulating film and a second conductive film on the first conductive film. A fourth step of alternately forming films at least one layer at a time, and a fifth step of patterning the first conductive film, the second insulating film, and the second conductive film to form an island-like lower electrode pattern. And the lower electrode pattern Forming a third conductive film covering a side surface of the lower electrode pattern, and a surface of the first insulating film exposed between the third conductive films covering a side surface of the adjacent lower electrode pattern. A seventh step of forming a third insulating film so as to cover the entire surface; and an eighth step of processing the lower electrode pattern and forming a groove exposing a part of the surface of the first conductive film. A ninth step of, after removing the second insulating film through the groove in a state where the third insulating film is present, removing the third insulating film and forming the lower electrode; A tenth step of forming a fourth insulating film serving as the dielectric film so as to cover an exposed surface of the first conductive film, the second conductive film, and the third conductive film including the inside of the groove; An eleventh step of forming a fourth conductive film serving as the upper electrode so as to cover the dielectric film. Method of manufacturing a semiconductor memory device which is characterized in that. 2. The method according to claim 1, wherein the third insulating film is an acid-resistant film. In the ninth step, the third insulating film is used as an etching stopper to perform the second insulating film through the groove by first wet etching. 2. The semiconductor memory device according to claim 1, wherein after removing the film, the third insulating film is removed by first wet etching having an etching rate higher than that of the first wet etching. 3. Production method. 3. The method according to claim 2, wherein the third insulating film is a silicon nitride film. 4. The method according to claim 1, wherein the first insulating film has a two-layer structure of an interlayer insulating film and a flattened film having a flattened upper surface. 13. The method for manufacturing a semiconductor memory device according to item 13. 5. A method for manufacturing a semiconductor memory device comprising: an access transistor having a gate, a source, and a drain; and a memory capacitor in which a lower electrode and an upper electrode are capacitively opposed to each other via a dielectric film. A first step of forming a first insulating film covering the access transistor; a second step of forming a second insulating film on the first insulating film; the first insulating film and the second A third step of forming an opening exposing a part of the surface of the source in the insulating film, and a first conductive layer buried in the opening on the second insulating film and connected to the source. A fourth step of forming a film, a fifth step of alternately forming at least one third insulating film and a second conductive film on the first conductive film, and a step of forming the first conductive film. Film, the third insulating film, and the second conductive film Forming a third conductive film covering the side surface of the lower electrode pattern, and processing the lower electrode pattern to form the first conductive film. An eighth step of forming a groove exposing a part of the surface of the film, and removing the third insulating film in a state where the second insulating film exists between the adjacent third conductive films, A ninth step of forming a lower electrode, and a step of forming the dielectric film so as to cover an exposed surface of the first conductive film, the second conductive film, and the third conductive film including the inside of the groove. A semiconductor memory device comprising: a tenth step of forming a fourth insulating film; and an eleventh step of forming a fourth conductive film serving as the upper electrode so as to cover the dielectric film. Manufacturing method. 6. The third insulating film, wherein the second insulating film is an acid-resistant film, and in the ninth step, the second insulating film is stoppered through the groove by first wet etching using the second insulating film as a stopper. 6. The method according to claim 5, wherein
6. The method for manufacturing a semiconductor memory device according to claim 1. 7. The method according to claim 6, wherein the second insulating film is a silicon nitride film. 8. The semiconductor device according to claim 5, wherein the first insulating film has a two-layer structure of an interlayer insulating film and a planarized film having a planarized upper surface. 13. The method for manufacturing a semiconductor memory device according to item 13. 9. A semiconductor memory device comprising: an access transistor having a gate, a source, and a drain; and a memory capacitor in which a lower electrode and an upper electrode are capacitively coupled to each other via a dielectric film. A first covering the access transistor
A bottom wall portion that is laterally spread on the insulating film and is connected to the lower layer source, and a fin-shaped side wall portion that is umbrella-shaped upward from the edge of the bottom wall portion and has an intricate inner surface. The upper electrode is formed so as to cover from the outer surface of the side wall portion to the inner surface of the side wall portion and the bottom wall portion. Is formed so as to cover the lower electrode via the dielectric film, and has an acid-resistant second insulating film between at least the adjacent lower electrodes on the interlayer insulating film. Semiconductor storage device. 10. The semiconductor memory device according to claim 9, wherein said second insulating film is made of a silicon nitride film.