JPH1174498A - Semiconductor integrated device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated device capable of improving the photoelectric conversion efficiency of its light receiving element, by removing one or whole opposed portion of its silicon layer to its electrode wiring through etching, and by projecting a light therethrough on the light receiving element. SOLUTION: In a silicon semiconductor substrate with an SOI structure, a Schottky junction 25 is formed between a first metallic electrode 26 and an N-type or intrinsic silicon layer 23. On the lateral side of the first metallic electrode 26, an N<+> -type region 28 and a second metallic electrode 27 connected with the region 28 are formed. The N-type or intrinsic silicon layer 23 is extenddely from the under portion of the first electrode 26 to the N<+> -type region 28 to bring them into an electrically connected state, one or whole opposed portion of the silicon layer 23 to the wiring of the electrode 26 is removed by an etching so that a light 29 can be projected on the depleted N-type or intrinsic silicon layer 23 from the opposite side to the Schottky junction 25 of a diode via an SiO2 layer 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical / electrical conversion semiconductor integrated device using a diode as a light receiving element.

[0002]

2. Description of the Related Art As a light receiving element incorporated in a semiconductor integrated circuit, a diode, a lateral bipolar transistor, and a MOS transistor structure are used.
Conventionally, since light had to be irradiated from the upper surface of the chip, absorption or reflection occurred in wirings, gate electrodes, and the like, and it was difficult to increase the efficiency of converting light into an electric signal.
In recent integrated circuits, the number of wiring layers on the upper surface of the chip is increasing to four to five and the number of layers is increasing. Therefore, when the light receiving element and the control or signal processing integrated circuit are mixed on the chip, the light receiving element is It is becoming difficult to keep the light-to-electricity conversion efficiency high.

FIG. 10 is a sectional view showing a conventional light receiving element having a MOS structure. In the figure, 11 is a P type silicon substrate, 12 is SiO ₂ , 13 is an N ⁺ type source,
14 is an N ⁺ type drain, 15 is a gate made of polysilicon, 16 is a source electrode, 17 is a drain electrode,
18 is a light reflection film, and 19 is light. That is, light 19 is incident on a MOS FET comprising a source 13, a drain 14 and a gate 15 formed on a silicon substrate 11 and a silicon substrate comprising SiO ₂
The optical-to-electrical conversion signal is detected by changing the value of the current flowing between the drain and the drain 14.

[0004]

However, since the light 19 is incident from the electrode wiring side on the upper surface of the silicon substrate, absorption or reflection occurs at the electrode wiring or gate, and it is difficult to increase the efficiency of converting light into an electric signal. Met.

The present invention has been made in view of the above circumstances, and removes a part or all of silicon on the side opposite to an electrode wiring by etching and makes light incident on the light receiving element to thereby improve the light receiving element. It is an object of the present invention to provide a semiconductor integrated device capable of improving light-to-electricity conversion efficiency.

[0006]

In order to achieve the above object, a semiconductor integrated device according to the present invention comprises a first metal electrode and an N or intrinsic thin film on a thin island of silicon in a silicon semiconductor substrate island having an SOI structure. Forming a Schottky junction with the silicon layer, forming an N ⁺ type region beside the first metal electrode and a second electrode connected to the N ⁺ type region, and forming the N or intrinsic silicon layer on the first metal electrode; A part of the silicon on the side opposite to the electrode wiring is removed by etching, and a part opposite to the Schottky junction of the diode is formed by forming from the lower part of the electrode to the N ⁺ region and electrically connected. The N or intrinsic region evacuated from the substrate can be irradiated with light through an oxide film, and the second electrode is used as an output terminal. It is assumed that.

Further, according to the present invention, in the above-mentioned semiconductor integrated device, an N ⁺ type region is formed at a central portion, and a Schottky electrode is formed around the N ⁺ type region.

The present invention also relates to a semiconductor integrated device as described above,
A one-dimensional or two-dimensional array is arranged on a silicon semiconductor substrate having an I structure, Schottky electrodes are commonly connected, and electrodes provided on an N ⁺ type region are commonly connected and connected in parallel. The silicon on the back surface is removed by etching, and it is possible to irradiate the depleted N or intrinsic region from the opposite side of the Schottky junction of the diode through an oxide film. An electrode commonly connected to the ⁺ type region is used as an output terminal.

Further, the present invention is characterized in that in the above-mentioned semiconductor integrated device, an impurity is introduced into the N or intrinsic region.

According to the present invention, there are provided two semiconductor integrated devices, one of which has a structure capable of irradiating light from the substrate side, and the other has a structure which does not / cannot irradiate light from the substrate side. The difference between the obtained electric signals is output.

Further, the present invention is characterized in that the output terminal of the semiconductor integrated device is further connected to an input terminal of a signal amplification and identification circuit formed on a silicon semiconductor substrate having the same SOI structure. .

Further, according to the present invention, a plurality of circuits each composed of the above-mentioned semiconductor integrated device can be formed on a silicon semiconductor substrate having an SOI structure by a single circuit.
It is characterized by being arranged in a two-dimensional or two-dimensional array.

Further, according to the semiconductor integrated device of the present invention, the P ⁺ region connected to the first metal electrode and the N ⁺ are connected on a thin island of silicon in a silicon semiconductor substrate island having an SOI structure.
Alternatively, a PN junction diode is formed between the N or intrinsic silicon layer and an N ⁺ type region and a second electrode connected thereto are formed beside the first metal electrode. The portion from the lower portion of the first electrode to the N ⁺ region is electrically connected, and part or all of silicon on the side opposite to the electrode wiring is removed by etching, and the PN junction diode is opposed. It is characterized in that it is possible to irradiate an N or intrinsic region depleted from the side with light through an oxide film, and to use the second electrode as an output terminal.

Further, according to the semiconductor integrated device of the present invention, a P ⁺ region connected to a first metal electrode and an N ⁺ region are formed on a thin island of silicon in a silicon semiconductor substrate island having an SOI structure.
Alternatively, a PN junction diode having a lateral structure is formed with the intrinsic silicon layer, and an N ⁺ type region and a second electrode connected thereto are formed beside the first metal electrode. A silicon layer is formed from the lower portion of the first electrode to the N ⁺ region to be in an electrically connected state, and part or all of silicon on the side opposite to the electrode wiring is removed by etching to form a lateral structure. The evacuated N or intrinsic region from the opposite side of the PN junction diode can be irradiated with light via an oxide film, and the second electrode is used as an output terminal. is there.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention. In the figure, 21 is a Si substrate, 22 is a Si substrate.
O ₂ and 23 are N or intrinsic silicon layers,
24 is a Schottky electrode, 25 is a Schottky junction, 2
6 is a first metal electrode, 27 is a second metal electrode, 28
Is an N ⁺ type region, 29 is light, and 30 is a hole. That is, the Schottky electrode 24 connected to the first metal electrode 26 and the N or intrinsic silicon layer 2 on the thin island of silicon in the silicon semiconductor substrate island having the SOI structure composed of the Si substrate 21 and SiO ₂ 22
A N ⁺ -type region 28 and a second metal electrode 27 connected to the N ⁺ -type region 28 beside the first metal electrode 26. 23 is the first metal electrode 2
6 from the lower part of N6 to the N ⁺ region 28 to form an electrically connected state, and part or all of silicon on the opposite side to the electrode wiring is removed by etching to form a hole 30; It is possible to irradiate the depleted N or intrinsic region 23 from the opposite side of the diode Schottky junction 25 with light 29 via the SiO ₂ 22, and use the second metal electrode 27 as an output terminal. .

As described above, the Schottky diode is formed on the silicon single crystal layer having the SOI structure, the silicon single crystal portion of the substrate facing the Schottky junction surface is removed by etching, and light is emitted from the substrate side. This allows direct irradiation to the dead area of the Schottky diode. In actual use, the diode is reverse-biased, and the charge generated in the depletion layer region when light is irradiated is detected as an electric signal to enable light-to-electric conversion.
According to the present embodiment, 1) light can be irradiated without any obstacle, so that conversion efficiency can be increased, and 2) SOI structure can be achieved, as compared with the case where light is irradiated from the upper surface of the conventional substrate. N ⁺ region can be reduced,
The parasitic capacitance of the signal output terminal can be reduced, and the detection sensitivity can be improved.

3) By including the hole on the substrate side up to the N ⁺ region, the substrate can be made not a conductor, and the parasitic capacitance can be further suppressed.

It has the following characteristics. From the viewpoint of light-to-electricity conversion efficiency, the efficiency can be improved by adjusting the thickness of the silicon layer of the SOI structure within a range in which depletion is possible, and further improvement in characteristics can be achieved.

FIG. 2 is a sectional view showing a second embodiment of the present invention. In the figure, portions corresponding to the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, 31
Is an impurity. That is, a structure is shown in which an impurity 31 capable of forming an impurity level is introduced into the region of the N-side or intrinsic silicon layer 23 on the semiconductor side of the Schottky junction 25 by, for example, an ion implantation apparatus. This makes it possible to improve the efficiency of light-to-electric conversion. In addition, it is possible to react to light of a longer wavelength, and it is possible to expand the application of light-electric conversion.

FIG. 3 shows a third embodiment of the present invention.
(A) is a top view and (b) is a cross-sectional view. In the figure, portions corresponding to the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. That is, the Schottky electrode 24 has a concentric donut shape, and a concentric N ⁺ type region 28 is formed in the central space. With this configuration, 1) the parasitic capacitance can be reduced because the N ⁺ electrode can be made smaller,
Optical signal detection sensitivity can be improved.

2) Since the silicon on the substrate facing N ⁺ is removed, the sensitivity of detecting an optical signal can be improved.

3) Since the volume of the void layer can be increased while keeping the distance between the electrodes small, the light-to-electricity conversion efficiency can be improved.

Many characteristics can be provided. However, in this figure, the concentric circles are used, but it is obvious that the same effect can be obtained even if the concentric circles or polygons are used.

FIG. 4 is a top view showing a fourth embodiment of the present invention. In the figure, portions corresponding to the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. That is, the Schottky diode shown in FIG. 3 is arranged in a two-dimensional array on a silicon semiconductor substrate having an SOI structure, and the Schottky electrodes 24 are connected in common, and are provided on an N ⁺ type region. The second metal electrode 27 is connected in common to form a parallel-connected diode, the silicon on the back surface is removed by etching, and the N or intrinsic layer that has been depleted from the opposite side of the Schottky junction of the diode is coated with SiO 2. It allows irradiating light through _2, and a second metal electrode 27 which is commonly connected to the N ⁺ type region and an output terminal.

The Schottky diode shown in FIG. 3 may be arranged one-dimensionally on a silicon semiconductor substrate having an SOI structure.

As described above, the Schottky diode shown in FIG. 3 is developed in parallel (in this case, 2 × 2
However, the effect is generally the same even when M × N is used), but it is possible to increase the amount of detection signals while keeping the operation speed high. It goes without saying that laying out such that the two electrodes of the diode do not cross each other as shown in this figure is also effective in reducing the parasitic capacitance. When a multilayer wiring can be used as an integrated circuit, parasitic capacitance can be suppressed by using a wiring in an upper layer as a wiring from an electrode for taking out a signal.

FIG. 5 shows a fifth embodiment of the present invention.
(A) is a top view, and (b) is a sectional view taken along line aa 'of (a). In the figure, portions corresponding to the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. That is, the second metal electrode 27 provided on the N ⁺ type region 28 is 2 × 2
And the rest is entirely covered with the Schottky electrode 24 with a certain gap from the second metal electrode 27 provided on the N ⁺ type region 28, thereby contributing to light-to-electric conversion. The second metal electrode 27 provided on the N ⁺ type region 28 is commonly connected as a Schottky diode, and equivalently functions as a single diode. The 2 × 2 array is shown as an example and M
XN does not change the function at all. The features of this embodiment are as follows: 1) The area of the Schottky junction can be maximized,
Electricity conversion efficiency can be increased.

2) Since a light receiving element having a large area can be formed,
If the area of the light receiving element is larger than the diameter of the light when receiving light,
It is possible to overcome the problem that required high precision for the optical axis alignment, which was regarded as a conventional problem.

FIG. 6 is a sectional view showing a sixth embodiment of the present invention. In the figure, portions corresponding to the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, 32
Is a P ⁺ type region. That is, a PN junction diode is formed between a P ⁺ type region 32 connected to the first metal electrode 26 and the N or intrinsic silicon layer 23 on a thin island of silicon in a silicon semiconductor substrate island having an SOI structure. The first metal electrode 2
Next to the N ⁺ type region 28 and the second
And the N or intrinsic silicon layer 23 is formed from the lower part of the first metal electrode 26 to the N ⁺ region 28 so as to be electrically connected to each other. A part or all of the silicon on the opposite side is removed by etching to form a hole 30, and light 29 through SiO ₂ 22 is passed from the opposite side of the PN junction diode to the region of the depleted N or intrinsic layer 23. And the second metal electrode 27 is used as an output terminal.

As described above, it is shown that similar light-to-electric conversion can be realized even in the structure using the PN junction diode instead of the Schottky diode shown in FIG.

FIG. 7 is a sectional view showing a seventh embodiment of the present invention. In the figure, portions corresponding to the same portions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the figure, 33
Is a P ⁺ type region. That is, a lateral structure PN is formed between a P ⁺ type region 33 connected to the first metal electrode 26 and the N or intrinsic silicon layer 23 on a thin island of silicon in a silicon semiconductor substrate island having a SOI structure. A junction diode,
N ⁺ type region 28 and a second metal electrode 27 connected to the N ⁺ type region 28 are formed beside the metal electrode 26, and the N or intrinsic silicon layer 23 is formed from the lower portion of the first metal electrode 26 to the N ⁺ region. 28, are electrically connected to each other, a part or all of the silicon on the opposite side to the electrode wiring is removed by etching to form a hole 30, and a void is formed from the opposite side of the PN junction diode. It is possible to irradiate the region of the converted N or intrinsic layer 23 with light 29 via SiO ₂ 22, and the second metal electrode 27 is used as an output terminal.

As described above, it is shown that similar optical-electrical conversion can be realized even in a structure using a lateral PN junction diode instead of the Schottky diode shown in FIG.

FIG. 8 is a circuit diagram showing an eighth embodiment of the present invention. In the figure, 34 is a diode having a structure capable of irradiating light, 35 is a diode having a structure not allowing / irradiating light, 36 is a power supply, and 37 is light. That is, the anode of the diode 34 configured to irradiate light from the substrate side and the anode of the diode 35 configured to not / cannot irradiate light from the substrate side are commonly connected to the power supply 36, and the cathode of the diode 34 The dark current is detected by detecting the signal including the current, detecting the dark current from the cathode of the diode 35, and subtracting the dark current obtained from the diode 35 from the signal including the dark current obtained from the diode 34. By detecting the signal, high-precision optical / electrical signal conversion is enabled.

As described above, two light-to-electricity conversion diodes are arranged close to each other, and one of the diodes is irradiated with light from the substrate side to perform a normal light-to-electricity conversion function as described in the present invention. The other diode is left without etching the substrate, or a function to block light even if the substrate is etched is added, so that dark current when there is no light is equivalently obtained as a signal And The actual optical / electrical conversion uses the difference between these two outputs. By doing so, the following effects can be expected.

1) By subtracting the dark current when there is no light signal from the diode from the light-to-electrically converted signal by a circuit method, accurate light-to-electricity conversion becomes possible, especially for a weak signal. 2) The characteristics of the diode fluctuate with changes in temperature.
This temperature characteristic can be corrected by taking the difference by using diodes of the same shape.

FIG. 9 is a circuit diagram showing a ninth embodiment of the present invention. In the figure, 34 is a diode having a structure capable of irradiating light, 36 is a power supply, 37 is light, 38 is an amplifier circuit, 39 is an identification circuit, and 40 is a semiconductor integrated circuit. That is, the anode of the diode 34 having a structure capable of irradiating the light 37 is connected to the power source 36,
Is connected to the input terminal of the amplifier circuit 38, the output terminal of the amplifier circuit 38 is connected to the input terminal of the identification circuit 39, and an electric signal is extracted from the output terminal of the identification circuit 39. The diode 34, the amplification circuit 38 and the identification circuit 39 are formed on a silicon semiconductor substrate having the same SOI structure.

As described above, the amplifier circuit 38 and the identification circuit 3 are mounted on the same chip as the diode 34 for optical / electrical conversion.
9 is mounted. The diodes of the present invention are all formed on an SOI substrate, and the amplifying circuit 38 and the discriminating circuit 39 described here are both constituted by MOS transistor circuits or bipolar transistor circuits using silicon. It is easy to form. The features of this are as follows.

1) Since the signal terminal converted from light into electricity and the input terminal of the amplifier circuit can be arranged close to each other, it is possible to suppress the parasitic capacitance to a small value and to realize a high-performance and low-power integrated circuit for optical reception. Can be realized.

2) Since the state-of-the-art semiconductor technology can be used and can be realized with one chip, downsizing can be achieved, and along with this, economy and low power consumption can be achieved at the same time.

By arranging a plurality of basic circuits according to the ninth embodiment of the present invention shown in FIG. 9 and developing them in a one-dimensional array or a two-dimensional array on a silicon semiconductor substrate having an SOI structure, Efficient large-capacity optical signal transmission and inter-board optical signal connection can be realized. A means for preventing light interference between the basic circuits is required, which can be realized, for example, by a silicon island or a silicon island covered with metal.

In the above embodiments, the N channel may be configured as a P channel and the P channel may be configured as an N channel.

[0043]

As described above, according to the present invention, a part or all of the silicon on the opposite side to the electrode wiring is removed by etching, and the light is incident on the light receiving element. A semiconductor integrated device capable of improving the electric conversion efficiency can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIGS. 3A and 3B show a third embodiment of the present invention, wherein FIG. 3A is a top view and FIG.

FIG. 4 is a top view showing a fourth embodiment of the present invention.

5A and 5B show a fifth embodiment of the present invention, wherein FIG. 5A is a top view, and FIG. 5B is a sectional view taken along line aa ′ of FIG. 5A.

FIG. 6 is a sectional view showing a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a ninth embodiment of the present invention.

FIG. 10 is a sectional view showing a conventional light receiving element having a MOS structure.

[Explanation of symbols]

Reference Signs List 21 Si substrate 22 SiO ₂ 23 N or intrinsic silicon layer 24 Schottky electrode 25 Schottky junction 26 First metal electrode 27 Second metal electrode 28 N ⁺ type region 29 Light 30 Hole

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tsuneo Mano 20-1 Sakuragaoka-cho, Shibuya-ku, Tokyo Inside NTT Electronics Corporation (72) Inventor Yukio Akazawa 20-1 Sakuragaoka-cho, Shibuya-ku, Tokyo NTT Electronics Inside (72) Inventor Masayuki Ino 20-1 Sakuragaoka-cho, Shibuya-ku, Tokyo Inside NTT Electronics Corporation (72) Inventor Hiroshi Inokawa 20-1 Sakuraoka-cho, Shibuya-ku, Tokyo Inside NTT Electronics Corporation

Claims (9)

[Claims] A first metal electrode formed on a thin island of silicon in an island of a silicon semiconductor substrate having an SOI structure;
Alternatively, a Schottky junction is formed with the intrinsic silicon layer, an N ⁺ type region is formed beside the first metal electrode, and a second electrode connected to the N ⁺ type region is formed. A portion from the lower portion of the first electrode to the N ⁺ region is electrically connected, and part or all of silicon on the side opposite to the electrode wiring is removed by etching, thereby forming a Schottky junction of the diode. A semiconductor integrated device, which is capable of irradiating the depleted N or intrinsic region from the opposite side with light through an oxide film, and using the second electrode as an output terminal. 2. The semiconductor integrated device according to claim 1, wherein an N ⁺ type region is formed at a central portion, and a Schottky electrode is formed around the N ⁺ type region. . 3. The semiconductor integrated device according to claim 1 or 2 is arranged in a one-dimensional or two-dimensional array on a silicon semiconductor substrate having an SOI structure, and Schottky electrodes are commonly connected. ^The electrodes provided on the ⁺ type region are connected in common to form a diode of parallel connection, the silicon on the back surface is removed by etching, and the N or intrinsic is evacuated from the opposite side of the diode Schottky junction. A semiconductor integrated device capable of irradiating light to a region through an oxide film and using an electrode commonly connected to the N ⁺ type region as an output terminal. 4. The semiconductor integrated device according to claim 1, wherein an impurity is introduced into the N or intrinsic region. 5. Two semiconductor integrated devices according to claim 1, 2, 3 or 4, one of which has a structure in which light can be irradiated from the substrate side, and the other has a structure in which light cannot be irradiated from the substrate side. A semiconductor integrated device which outputs a difference between electric signals obtained from the two semiconductor integrated devices. 6. An output terminal of the semiconductor integrated device according to claim 1, 2, 3, or 5, further serving as an input terminal of a signal amplification and identification circuit formed on a silicon semiconductor substrate having the same SOI structure. A semiconductor integrated device characterized by being connected. 7. A plurality of circuits each comprising the semiconductor integrated device according to claim 6 are mounted on a silicon semiconductor substrate having an SOI structure by one.
A semiconductor integrated device arranged in a two-dimensional or two-dimensional array. 8. A PN junction diode is formed between a P ⁺ region connected to a first metal electrode and an N or intrinsic silicon layer in a thin island of silicon in a silicon semiconductor substrate island having an SOI structure. An N ⁺ -type region and a second electrode connected to the N ⁺ -type region are formed beside the first metal electrode, and the N or intrinsic silicon layer is formed from the lower portion of the first electrode to the N ⁺ region. In a state where they are electrically connected to each other, a part or all of silicon on the opposite side to the electrode wiring is removed by etching, and oxidized from the opposite side of the PN junction diode to a depleted N or intrinsic region. A semiconductor integrated device capable of irradiating light through a film and using the second electrode as an output terminal. 9. A lateral PN junction between a P ⁺ region connected to a first metal electrode and an N or intrinsic silicon layer in a thin island of silicon in a silicon semiconductor substrate island having an SOI structure A diode is formed, an N ⁺ -type region and a second electrode connected to the N ⁺ -type region are formed beside the first metal electrode, and the N or intrinsic silicon layer is formed from the lower portion of the first electrode.
Configured up to ⁺ area and electrically connected,
A part or all of silicon on the opposite side to the electrode wiring is removed by etching, and light is irradiated from the opposite side of the lateral PN junction diode to the depleted N or intrinsic region via an oxide film. A semiconductor integrated device, wherein the second electrode is used as an output terminal.