JPH117441A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a general data processor capable of corresponding to various multi-media applications. SOLUTION: The data processor is provided with plural memories 100, 102, 260, plural operation parts 30, 130, 200, 210, 220, 230, a data transfer part 20, and a network 240. The data transfer part 20 transfers various data to the memories (e.g. 100, 260) and switches connecting relation among respective memories 100, 102, 260 and respective operation parts 30, 130, 200, 210, 220, 230 through the network 240. Control parts 50, 250 add executable state judgement signals to data read out from respective memories 100, 260 to form a pair of data. Each operation part receives data and the executable state judgement signal, executes prescribed operation for the received data, delays the received executable state judgement signal by the number of cycles equal to the number of operation cycles, and outputs the operation result and the delayed executable state judgement signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to an improvement of a data processing apparatus in which a plurality of memories and a plurality of arithmetic means exist in a processor, and a large amount of data is controlled and processed in these parts. About.

[0002]

2. Description of the Related Art Conventionally, an addition and subtraction,
Arithmetic devices such as multiplication and division, and a hardware engine as a circuit dedicated to the processor are provided.
The hardware engine is disclosed, for example, in US Pat.
2,458 "ARCHITECTURE FOR POWER OF TWO COEFIC
As disclosed in "IENT FIR FILTER", this is a dedicated arithmetic circuit configured for the use of the processor and the processing speed required for the use. US Patent 4,
881, 192 “ONE-DIMENSIONAL LINEAR PICTURE T
RANSFORMER ", as the hardware engine,
By arranging a network composed of a plurality of buses and a plurality of arithmetic units and combining them, a dedicated circuit that realizes a specific process is proposed.

In recent years, with the advance of LSI technology, a processor incorporating a new instruction in addition to a conventionally known instruction, for example, a processor Pentium manufactured by Intel Corporation incorporating a new instruction called a "multimedia instruction".
In II and the like, an arithmetic unit provided therein has been increasingly sophisticated, and various processings such as image processing and audio processing can be executed without using a hardware engine at a certain processing speed. However, when a high processing speed is required, a hardware engine is also required.

In recent years, a processor having a plurality of memories, a plurality of arithmetic units, and a network therein, that is, for example, a Mpac manufactured by Chromatic Research, USA
In a processor called a “media processor” such as “t” or “Trimedia” by Philips, a plurality of types of processing (multimedia processing) such as image processing and audio processing are to be realized at high speed. In the media processor, for example, image processing and audio processing are performed.
When performing processing, it is necessary to provide a hardware engine corresponding to these processing and a desired processing speed.

[0005]

However, for example, a hardware engine provided differs between a media processor that performs image processing and audio processing and a media processor that performs a plurality of other processes. Therefore, since a plurality of media processors have different hardware engines for different executable processes, there is a problem that a variety of processors must be designed.

SUMMARY OF THE INVENTION The present invention focuses on the above-mentioned problems, and an object of the present invention is to provide a data processor capable of adapting to various multimedia applications by providing versatility as a media processor without designing a variety of processors. Is to provide.

[0007]

In order to achieve the above object, a data processing apparatus according to the present invention comprises a plurality of memories, a plurality of arithmetic units, and a network. The connection between the devices can be switched using the network, and the data flowing through them can be processed efficiently.

That is, the data processing apparatus according to the first aspect of the present invention provides one or more data storage units storing data, a plurality of operation units, the data storage unit and the plurality of operation units. A network for switching connections between the control unit and a control unit for outputting a valid data specifying signal indicating that the data to be read is valid data when reading data stored in the data storage unit; Receiving the valid data identification signal from the data storage unit, and specifying the received valid data identification signal by the number of cycles from when the data is read from the data storage unit to when the result calculated by the one or more arithmetic units is obtained. And a delay circuit for delaying and outputting a signal.

According to a second aspect of the present invention, in the data processing device according to the first aspect, the delay circuit is constituted by delay units provided corresponding to the plurality of arithmetic units, respectively. Are characterized in that the corresponding operation unit delays and outputs the valid data specifying signal by the number of cycles required for the operation.

According to a third aspect of the present invention, in the data processing device according to the first or second aspect, the control unit includes: a write pointer to which the number of data stored in the data storage unit is given; A pointer to which the number of times of reading data from the unit is sequentially given is compared with the value of the write pointer, and when the value of the pointer is equal to or less than the value of the write pointer, a valid data specifying signal is output. A determination unit.

According to a fourth aspect of the present invention, in the data processing apparatus according to the first, second, or third aspect, the valid data specifying signal has data that can be processed inside the data storage unit. Is an executable determination signal that means

According to a fifth aspect of the present invention, in the data processing device according to the first or second aspect, a main data storage unit in which data is stored in advance and a data stored in the main data storage unit are further stored. And a data transfer unit for transferring data to the plurality of data storage units, wherein the data transfer unit outputs to the control unit a synchronization signal instructing to simultaneously read data from the plurality of data storage units. It is characterized by doing.

According to a sixth aspect of the present invention, in the data processing device of the fifth aspect, the number of control units is provided corresponding to each data storage unit, the number being equal to the number of data storage units. .

According to a seventh aspect of the present invention, in the data processing apparatus according to the sixth aspect, each control unit includes a delay cycle number register for storing a set cycle number for delaying data reading after the input of the synchronization signal. And reading of data is started when the number of delay cycles has elapsed after the input of the synchronization signal.

According to an eighth aspect of the present invention, in the data processing apparatus according to the first or second aspect, the number of data processing stages by the plurality of processing units after the connection switching by the network is changed by the switching. Is different from the number of operation stages in front of.

According to a ninth aspect of the present invention, in the data processing apparatus according to the first or second aspect, the network outputs data from two or more data storage units to the same operation unit. The connection is switched.

[0017] The invention according to claim 10 is the invention according to claim 1,
The data processing device according to claim 2 or 7,
The network is connected such that data is output from one data storage unit to one operation unit, and then the operation result of this operation unit and data of another data storage unit are output to another operation unit. Is switched.

According to an eleventh aspect of the present invention, there is provided the data processing device according to the first or second aspect, further comprising a main data storage unit in which data is stored in advance, and the connection switching information by the network is , Stored in the main data storage unit.

According to a twelfth aspect of the present invention, in the data processing apparatus according to the first or second aspect, the network includes an output bus through which data and valid data identification signals are output from a data storage unit and a control unit, respectively. Switches and
An input bus switch for inputting the received data and the valid data specifying signal to an arithmetic unit.

The invention according to claim 13 is the invention according to claim 12.
The data processing device according to claim 1, wherein the network is:
A plurality of buses, and a bus switch arranged for each of the buses, wherein the bus switch is conductive to allow data transmission, and is nonconductive to prohibit data transmission. I do.

According to a fourteenth aspect of the present invention, in the data processing device according to the first or second aspect, the plurality of arithmetic units perform mutually different arithmetic operations.

According to a fifteenth aspect of the present invention, in the data processing device of the first or second aspect, a valid data specifying signal is received via a network from an operation unit that performs the last operation, and a write instruction is output. The other control unit receives the operation result finally obtained from the operation unit performing the last operation, and receives the write instruction from the other control unit and stores the operation result finally obtained. And another data storage unit.

With the above arrangement, according to the first to fifteenth aspects of the present invention, at the time of reading data from the data storage unit, a valid data specifying signal is added to the data, and the data is calculated by the calculation unit. When the operation result data is stored in the storage unit, the valid data specifying signal is input to the storage unit at the same time. Therefore, even if the number of operation stages is different, the operation result data can be recognized as valid data. , Can be stored in the storage unit.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram for explaining a data processing apparatus according to the basic principle of the present invention. 2 and 3 are diagrams for explaining a basic operation flow in the present invention. FIG. 4 is a diagram for explaining data in each unit according to the principle of the present invention.

In the description of the principle diagram of FIG. 1, a case where the following program is executed will be taken as an example of explanation. In this example, the elements of the arrays a and b are multiplied, then the elements of the array c are added, and the result is stored in the elements of the array d.

[0027] In FIG. 1, reference numeral 10 denotes a first memory (main data storage) outside the processor that stores data. 16 is
1 shows a data processing device for processing data, and 14 is a clock generator for supplying a clock to each part. The clock generating unit 14 supplies a clock to each unit in the data processing device 16 through a clock line 15, and each unit supplied with the clock performs a constant process in each cycle in synchronization with the clock.

Reference numeral 20 denotes a first external device outside the data processing device 16.
A first operation unit (data transfer unit), which receives data from the memory 10 and processes the data, and transfers the received data to a second memory 100 (described later), 12
This is a data line for exchanging data between 10 and the first arithmetic unit 20. In this description, it is assumed that three data can be sent to the data line 12.

The second memory 10 stores an execution program 4 for instructing an execution operation of the first arithmetic unit 20 and the data processing device 16 and input data 6 for performing future processing in the first memory 10.
Is a program loader that stores data in

100 is a second memory (data storage unit), 22
Is a data line for sending data from the first arithmetic unit 20 to the second memory 100.

Numeral 50 denotes a pointer 60 indicating a read address of data from the second memory 100, and a first arithmetic unit
The write pointer 62 indicating the number of words sent from 20 to the second memory 100 and stored therein is compared with the pointer 60 and the write pointer 62 to determine whether data can be read from the second memory 100. And a first control unit (control unit) including an executable determination unit (determination unit) 70 that performs the determination.

FIG. 3A shows a judgment flow in the executable judgment section 70. By referring to the pointer 60 and the write pointer 62 and confirming the existence of data in the second memory 100, an executable determination signal 72 (valid data specifying signal) is generated.

Reference numeral 64 denotes the first operation unit 20 to the first control unit 50
The pointer setting line 66 for setting the pointer 60 is a light pointer setting line for setting the write pointer 62 of the first control unit 50 from the first arithmetic unit 20. 68 is a second control unit
This is an address line which reads out the pointer 60 of 50 into the second memory 100 and indicates it as an address. 32 is the second memory 10
A data line 72 for transmitting the data read from 0 to the second arithmetic unit 30 is an executable determination signal for notifying the second memory 100 and the second arithmetic unit 30 whether the data can be executed.

In the present description, the data line 32 transfers three types of elements of the arrays a, b, and c for each cycle.
If there is data to be executed on this data line, the executable judgment signal 72 becomes, for example, "1", indicating whether there is data meaningful to be executed. Therefore, the data line 32 and the executable determination signal 72 are paired for each cycle and transferred between the units.

Reference numeral 30 denotes a second operation unit (operation unit). The second operation unit 30 receives data on the data line 32,
Data latch 40 for storing data in synchronization with clock
And an executable determination signal latch (delay unit) 140 for storing the executable determination signal 72 and a plurality of data of the data latch 40, selecting one of them and multiplying them by a multiplication unit (processing ) 38, and an output selector 42 which receives the result of the multiplication unit 38 and the data from the data latch 40, and sends one of them to the third operation unit 130.

Numeral 34 denotes a data line for outputting data from the second arithmetic unit 30, and reference numeral 144 denotes an executable determination signal for determining whether the second arithmetic unit 30 can execute the data.

Reference numeral 130 denotes a third arithmetic unit (arithmetic unit),
The third arithmetic unit 130 receives the data on the data line 34 from the second arithmetic unit 30 and stores the data in synchronization with the clock. The data latch 146 and the executable determination signal 144 stores the executable determination signal 144. An adder (processing unit) 136 for inputting and selecting a plurality of data of the signal latch (delay unit) 142 and the data latch 146 and adding the selected data, and a result of the adder 136 and the data latch 146 And an output selector 148 for receiving any of these data and sending out any of them to the third memory 102.

A delay circuit 141 is constituted by the two executable determination signal latches (delay units) 140 and 142.

Reference numeral 36 denotes an output selector 14 of the third arithmetic unit 130.
The data line 150 for outputting the data from 8 is an executable determination signal for which the third arithmetic unit 130 has determined whether or not it is executable.

Reference numeral 102 denotes a third memory (another data storage unit), and reference numeral 24 denotes a data line for transmitting data from the third memory 102 to the first arithmetic unit 20.

Reference numeral 120 denotes a second control unit (other control unit), which includes a pointer 160, a write pointer 162 indicating an address to write the data in the third memory 102, and a third control unit. An executable determination unit 170 receives the executable determination signal 150, determines whether data can be written to the third memory 102, and outputs a write command to the third memory 102 when it determines that data can be written. You.

Reference numeral 166 denotes an executable judgment signal of the executable judgment unit 170 for notifying whether or not writing to the third memory 102 is possible. 65 is a signal from the first arithmetic unit 20 to the second control unit 120
Pointer setting line for setting and referring to the pointer 160 of
Is a write pointer setting line for setting and referring to the write pointer 162 of the first arithmetic unit 20 to the second control unit 120. An address line 168 indicates the output of the write pointer 162 of the second control unit 120 as a write address to the third memory 102.

The operation will be described below with reference to FIGS. 1, 2, 3 and 4.

(Before cycle # 0) Execution program 4 and input data 6 for the data processing device in the present invention
Is generated by a compiler or assembler and stored in the first memory 10 in advance by the program loader 2.
[S000].

That is, the data of the input data arrays a, b, and c are stored in the first memory 10 as the input data 6, and the execution program 4 includes the flow of the principle operation according to the present invention. Is stored.

Here, the program loader 2 may be an external processor or the like. However, since it is not a main point in the present invention, the description is omitted.

The first operation unit 20 receives the execution program 4 in the first memory 10 and receives the pointer 60 of the first control unit 50.
And the write pointer 62 are initialized to “0”.

The first arithmetic unit 20 receives the execution program 4 in the first memory 10 and stores the pointer in the second control unit 120
160 and the write pointer 162 are each initialized to "0".
[S001].

Further, the executable determination section 70 of the first control section 50
Then, the pointer 60 and the write pointer 62 are referenced and compared in each cycle, and it is determined that there is no executable data in the second memory 100. This operation is performed independently of the first arithmetic unit 20 for each cycle [T00
0].

Further, the executable determination unit of the second control unit 120
In step 170, the executable determination signal 150 from the third arithmetic unit 130 is received in each cycle, and it is determined that there is no write data. This operation is also performed independently of the first arithmetic unit 20 for each cycle [U000].

The first arithmetic unit 20 receives the execution program 4 in the first memory 10 and reads the array a,
Receives 100 words of data (b, c)
To the memory 100 of.

(Cycle # 0) The first arithmetic unit 20 receives the execution program 4 in the first memory 10, and stores the number “100” in the write pointer 62 of the first control unit 50 and further in the pointer 60. Write “0”. [S002] (Cycle # 1) The executable determination unit 70 of the first control unit 50 compares the write pointer 62 with the pointer 60, the pointer is “0”, and the write pointer 62 is set to “100”. Has been read, it is determined that it is readable [T00
0].

Accordingly, the executable determination section 70 sends an executable determination signal 72 to the second memory 100 and the second arithmetic section 30, and the second memory 100 outputs the data arrays a and b based on this signal. , C, the first data a [0], b [0], c [0] are sent out. The pointer 60 is incremented by one for the array [T001].

The operations of the first control unit 50 and the second memory 100 in this cycle # 1 will be described below.
Until 60 becomes the same "100" as the value of the write pointer 62, it is continuously executed.

(Cycle # 2) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 1 is performed.
The next data in the array of a, b, and c is read, and the pointer
60 is further incremented by one address [T00
0] [T001].

The data latch 40 of the second operation unit 30
The three data a [0], b [0], and c [0] are received from the memory 100 of FIG. The multiplying unit 38 calculates a [0]
And b [0], and performs a multiplication operation (a [0] xb [0]). Further, the executable determination signal latch 140 receives the executable determination signal 72 from the first control unit 50 and sends it to the third arithmetic unit 130. Also, the output selector 42
Processing result data (a [0] xb [0]) from 38 and data latch 40
Is sent to the third calculation unit 130. The operation of the second arithmetic unit 30 in this cycle is similarly executed thereafter in each cycle.

(Cycle # 3) In the first controller 50 and the second memory 100, the same operation as in the cycle # 2 is performed.
The next data in the array of a, b, and c is read, and the pointer
60 is further incremented by one address [T00
0] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 2 is performed, and the next element a [1] xb [1] of the array is calculated.

The data latch 146 of the third arithmetic unit 130
It receives two data of processing result data (a [0] xb [0]) and data c [0] from the second arithmetic unit 30 and sends them to the adding unit 136. The adder 136 calculates these data (a [0] xb [0]) and
Receiving c [0], an addition operation (a [0] xb [0]) + c [0] is performed. Further, the executable determination signal latch 142 receives the executable determination signal 144 from the second arithmetic unit 30 and sends it to the second control unit 120. The output selector 148 sends the processing result data (a [0] xb [0]) + c [0] from the adder 136 to the third memory 102. Third arithmetic unit in this cycle
The operation of 130 is similarly executed in each cycle thereafter.

(Cycle # 4) In the first control unit 50 and the second memory 100, the same operation as in cycle # 3 is performed.
The next data in the array of a, b, and c is read, and the pointer
60 is further incremented by one address [T00
0] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 3 is performed, and the next element a [2] xb [2] of the array is calculated.

The third operation unit 130 performs the same processing as in cycle # 3, and calculates the next element a [1] xb [1] + c [1] of the array.

Executable determination section 170 of second control section 120
Receives the executable determination signal 150 of the third arithmetic unit 130,
Judge that writing is possible [U000].

Further, the third memory 102 has a second controller
Executable judgment signal 166 from 120 executable judgment section 170
In response, the result data from the third arithmetic unit 130 is written as the result data d [0] at the address indicated by the write pointer 162. At the same time, the write pointer 162 of the second control unit 120
Then increase by +1 [U001].

That is, the data received by the second arithmetic unit 30 includes the data 32 sent out by the second memory 100 in the previous cycle and the data sent out by the first control unit 50 in the previous cycle. This is the executable determination signal 72. The data and the data executable determination signal received by the third arithmetic unit 130 are the data 34 sent out by the second arithmetic unit 30 in the immediately preceding cycle and the data executable determination signal 144 (that is, 2). The data sent by the second memory 100 in the previous cycle and the data executable signal sent by the first control unit 50). Further, a third memory 102 and a second control unit
The data and the executable determination signal received by 120 are the data and the executable determination signal sent by the third arithmetic unit 130.

(Cycle # 5) In the first control unit 50 and the second memory 100, the same operation as in cycle # 3 is performed.
The next data in the array of a, b, and c is read, and the pointer
60 is further incremented by one address [T00
0] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 4 is performed, and the next element a [3] xb [3] in the array is calculated. In the third operation unit 130, the same processing as in the cycle # 4 is performed, and the next element a [2] xb [2] + c [2] of the array is calculated.

In the second control unit 120 and the third memory 102, the same processing as in cycle # 4 is performed, and the next element in the array is
d [1] is stored, and the write pointer 162 is incremented by one.

In each of the subsequent cycles, the same processing is performed, and the first controller 50 and the second memory 100 repeat the processing until the pointer 60 and the write pointer 62 have the same number, "100". In the second control unit 120,
The executable determination signal 72 generated by the first control unit 50 is counted from cycle # 4 to cycle 103, and the result data d [0] to d [99] are stored for "100" cycles, and the program The process will end.

The first arithmetic unit 20 periodically executes the second control unit 120 at the timing determined by the execution program.
The light pointer 162 in FIG.
It is determined whether or not this program has been terminated by determining whether or not it is "0" [S003], [S00
Four] .

In other words, each time such data is sent out in each cycle with respect to the data stored in the second memory 100, an executable determination signal indicating whether or not the processing can be executed corresponding to each data. Is output from the executable determination unit 70 of the first control unit 50 and added, and the data and the executable determination signal are sent as a pair to the second and third arithmetic units 30 and 130. In each operation unit, the processed data and
Further, it outputs the input feasibility determination signal as a pair. Also, when writing the data after the arithmetic processing to the memory after passing through a plurality of stages of arithmetic units, refer to the executable determination signal transmitted in pairs with the data and check whether valid data exists. By determining whether or not the processing is performed on the memory side, it is possible to write the data of the processing result without fail irrespective of the number of stages of the operation unit.

Using the above principle, this principle can be applied to a network having a plurality of memories, a plurality of control units corresponding thereto, and a plurality of arithmetic units having a plurality of stages, and having a plurality of paths. And the connection status of this network,
This is extended to the case where the reconfiguration is performed using the network configuration line from the first arithmetic unit.

FIG. 5 is a diagram for explaining a data processing device according to the first embodiment of the present invention. In the first embodiment of the present invention, differences from the principle will be described below.

Reference numeral 270 denotes an executable judgment signal from the first control unit 50, and 324 denotes a data line from the second memory 100.
Reference numeral 260 denotes a fourth memory (data storage unit), and reference numeral 250 denotes a third control unit (control unit) that controls the fourth memory 260.
These are functionally the same as the second memory 100 and the first control unit 100, respectively.

Reference numeral 240 denotes an executable determination signal (bus) 172, 17
This network has four pairs of 4,176,178 and data lines (buses) 171,173,175,177.

182, 184, 190, 194, 196 are the network 24
An output bus switch for outputting an executable determination signal and data to 0. The output bus switch is capable of outputting an executable determination signal and data to any of the networks 240 in a programmable manner, and the selection method is programmed in the execution program 4.

Reference numerals 180, 186, 188, and 192 designate input bus switches for programmably inputting an executable determination signal and data from any of the networks 240 to each operation unit. This selection method is the same as that of the output bus switch. It is programmed during program 4.

Reference numeral 400 denotes a data processing device configuration line for controlling the input bus switch and the output bus switch.

The above is the point different from the principle in the first embodiment of the present invention.

FIGS. 6 and 7 show the present embodiment.
FIG. 3 is a diagram illustrating a flow of data in a network configured by network configuration lines.

In the data processing device shown in FIG.
To execute Program 1], as shown in FIG.
Executability determination signal 270 of first control unit 50 and second memory
The output bus switch 182 is switched so as to output the pair with 100 data lines 324 to the executable signal 172 and the data line 171 of the network 240. In addition, the input bus switch 180 to the second arithmetic unit 30 can be executed by the execution determination signal 17.
2 and data line 171. Further, the executable determination signal 276 from the third arithmetic unit 130 and the data line
The output bus switch 184 is switched so as to output 322 to the executable signal 174 and the data line 173 of the network 240. In addition, the second control unit 120 and the third memory 10
The same operation can be performed by switching the input bus switch 188 so that the executable signal 276 and the data line 330 are input from the executable determination signal 174 and the data line 173 of the network 240. Note that the timing is the same as the description of the above-described principle, and the description thereof will be omitted.

Here, the fourth operation unit 200 is further considered as an operation unit having a multiplication function similar to that of the second operation unit 30, and the fifth operation unit 210 is assumed to have the same addition function as the third operation unit 130. Think of it as an arithmetic unit with functions.

In this case, consider the following program.

[0084] The difference between [Program 2] and [Program 1] is that the number of multiplications and additions is two each. That is, in the data processing device 16, the data input from the network 240 is transferred to the second arithmetic unit 30 and the third arithmetic unit 13.
0, and then multiplied by another arithmetic unit (the fourth arithmetic unit 200 and the fifth arithmetic unit 21) via the network 240.
0) is input again and further multiplied / added.

The above program can be realized by setting the switching method of the network 240 as follows. The following contents are contents generated by a compiler or the like at the time of compiling the program, and are stored as setting data on the execution program 4, for example.

As shown in FIG. 7, a pair of the executable determination signal 270 of the first control unit 50 and the data line 324 of the second memory 100 is connected to the executable determination signal 172 and the data line 171 of the network 240. Output bus switch 182 to output to
And an input bus switch to the second arithmetic unit 30
180 is performed from the executable determination signal 172 and the data line 171. Further, the executable determination signal 276 from the third arithmetic unit 130 and the data line 322 are connected to the network 240
The output bus switch 184 is switched so as to output the execution determination signal 174 to the data line 173 and the input bus switch 186 to the fourth arithmetic unit 200 is determined to be executable.
Switch to input 174 and data line 173. Further, the executable determination signal 280 from the fifth arithmetic unit 210 and the data line 328 are connected to the executable determination signal 17 of the network 240.
Output bus switch to output to 6 and data line 175
Switch 190. Further, the input bus switch 188 is switched so that the executable signal 276 and the data line 330 to the second control unit 120 are inputted from the executable determination signal 176 and the data line 175 of the network 240. Thereby, a similar operation can be performed.

FIGS. 8 and 9 are diagrams for explaining data in each section in [Program 2] according to the first embodiment of the present invention.

Next, a first embodiment of the present invention will be described with reference to FIGS. 2, 3, 5, 6, 7, 8, and 9. FIG.

(Before cycle # 0) The execution program 4 and the input data 6 for the data processing device of the present invention are generated by a compiler or assembler, and stored in the first memory 10 in advance by the program loader 2 [ S00
0].

That is, the data of the input data arrays a, b, and c are stored as the input data 6 in the first memory 10. Further, the execution program 4 stores a flow of the operation of the embodiment according to the present invention.

Here, the program loader may be an external processor or the like, but is not a main point in the present invention, and therefore, the description is omitted.

The first arithmetic unit 20 receives the execution program 4 in the first memory 10, and initializes the pointer 60 and the write pointer 62 of the first control unit 50 to "0".

The first operation unit 20 receives the execution program 4 in the first memory 10 and stores the pointer 16 in the second control unit 120
0 and the write pointer 162 are each initialized to "0".

The first arithmetic unit 20 receives the execution program 4 in the first memory 10, and sets the connection configuration of each input bus switch and each output bus switch by the network configuration line 400 [S001].

Further, the executable determination section 70 of the first control section 50
Then, in each cycle, the pointer 60 and the write pointer 62 are referenced and compared to determine that there is no executable data in the second memory 100 [T000].

Further, the executable determination unit of the second control unit 120
In step 170, the executable determination signal 150 from the third arithmetic unit 130 is received in each cycle, and it is determined that there is no write data [U000].

The first arithmetic unit 20 receives the execution program 4 of the first memory 10 and the data of "100" words of the arrays a, b and c from the first memory 10 and sequentially processes them. Write to the second memory 100.

(Cycle # 0) The first arithmetic unit 20 receives the execution program 4 in the first memory 10, writes the number “100” into the write pointer 62 of the first control unit 50, Writes “0” [S002].

(Cycle # 1) The executable determination unit 70 of the first control unit 50 compares the write pointer 62 with the pointer 60, and finds that the pointer is “0” and the write pointer 62 is “10”.
Since it is set to "0", it is determined that reading is possible [T000].

Therefore, the executable determination unit 70 determines that
And to the second arithmetic unit 30 via the executable determination signal 172 of the network 240.

In the second memory 100, the first data of the data arrays a, b and c are
a [0], b [0], and c [0] are sent to the data line 171 of the network 240. The value of the pointer 60 is incremented by one for the array [T001].

The operations of the first control unit 50 and the second memory 100 in this cycle # 1 will be described later.
Until the value of 60 becomes the same value of "100" as the value of the write pointer 62, it is continuously executed.

(Cycle # 2) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 1 is performed.
The next data in the array of a, b, and c is read, and the pointer
60 is further incremented by one address [T00
0] [T001].

The data latch 40 of the second operation unit 30 receives three data a [0], b [0], c [0] from the second memory 100 and sends them to the multiplication unit 38. The multiplying unit 38 calculates a [0]
And performs a multiplication operation a [0] xa [0]. Further, the executable determination signal latch 140 receives the executable determination signal 172 from the first control unit 50, and
Send to 0. The output selector 42 sends the processing result data (a [0] xa [0]) from the multiplication unit 38 and the data b [0] and c [0] from the data latch 40 to the third arithmetic unit 130. . The operation of the second arithmetic unit 30 in this cycle is similarly executed in each cycle thereafter.

(Cycle # 3) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 2 is performed.
The next data in the array of a, b, and c is read, and the pointer
The value of 60 is further incremented by one address
[T000] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 2 is performed, and the next element a [1] xa [1] in the array is calculated.

The data latch 146 of the third operation unit 130
Data (a [0] xa [0]), data b [0],
The three c [0] are received and sent to the adder 136. The adder 136 receives (a [0] xa [0]) and c [0] and performs an addition operation (a [0] xa [0]) + c [0]. Further, the executable determination signal latch 142 receives the executable determination signal 144 from the second arithmetic unit 30 and sends it to the executable determination signal 174 of the network 240. Also, the output selector 148 outputs the processing result data (a [0] xa [0]) + c [0] from the adder 136 and the data
b [0] is sent to the data line 173 of the network 240.
The operation of the third arithmetic unit 130 in this cycle is similarly executed every cycle thereafter.

(Cycle # 4) In the first control unit 50 and the second memory 100, the same operation as in cycle # 3 is performed.
The next data in the array of a, b, and c is read, and the pointer
The value of 60 is further incremented by one address
[T000] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 3 is performed, and the next element a [2] xa [2] in the array is calculated.

The third operation unit 130 performs the same processing as in cycle # 3, and calculates the next element a [1] xa [1] + c [1] in the array.

In the data latch of the fourth arithmetic unit 200, a [0] xa [0] + c [0], b
[0] is received and sent to the multiplication unit. The multiplication unit receives b [0] therein, and performs a multiplication operation b [0] xb
Perform [0]. Further, the executable determination signal latch of the fourth arithmetic unit 200 is connected to the executable determination signal 17 of the network 240.
4 is sent to the fifth arithmetic unit 210. The output selector of the fourth arithmetic unit 200 outputs the processing result data (b [0] xb [0]) from the multiplication unit and the data a from the data latch.
[0] xa [0] + c [0] is sent to the fifth arithmetic unit 210. The operation of the fourth arithmetic unit 200 in this cycle is similarly executed in each cycle thereafter.

(Cycle # 5) In the first control unit 50 and the second memory 100, the same operation as in cycle # 4 is performed.
The next data in the array of a, b, and c is read, and the pointer
The value of 60 is further incremented by one address
[T000] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 4 is performed, and the next element a [3] xa [3] of the array is calculated.

In the third arithmetic section 130, the same processing as in cycle # 4 is performed, and the next element a [2] xa [2] + c [2] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in cycle # 4 is performed, and the next element b [1] xb [1] of the array is calculated.

The data latch of the fifth arithmetic unit 210
From the arithmetic unit 200, and two data of (a [0] xa [0] + c [0]) and b [0] xb [0] are sent to the adding unit. The adder is
The data (a [0] xa [0] + c [0]) and b [0] xb [0] are received, and an addition operation is performed (a [0] xa [0] + c [0]) + (b [0] xb [0]).
Further, the executable determination signal latch receives the executable determination signal 214 from the fourth arithmetic unit 200, and
It is sent to the executable judgment signal 280/176 of 0. Further, the output selector outputs the processing result data a [0] xa [0] + b
Send [0] xb [0] + c [0] to data line 175 of network 240. The operation of the fifth arithmetic unit 210 in this cycle is also
Thereafter, the same process is performed for each cycle.

(Cycle # 6) In the first control unit 50 and the second memory 100, the same operation as in cycle # 5 is performed.
The next data in the array of a, b, and c is read, and the pointer
The value of 60 is further incremented by one address
[T000] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 5 is performed, and the next element a [4] xa [4] in the array is calculated.

In the third arithmetic unit 130, the same processing as in cycle # 5 is performed, and the next element a [3] xa [3] + c [3] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in cycle # 5 is performed, and the next element b [2] xb [2] in the array is calculated.

In the fifth arithmetic section 210, the same processing as in cycle # 5 is performed, and the next element a [1] xa [1] + b [1] xb [1] +
c [1] is calculated.

Executable determination section 170 of second control section 120
Receives the executable determination signal of the fifth arithmetic unit 210 via the executable determination signal 176 of the network 240 and determines that writing is possible [U000].

Further, the third memory 102 receives the execution determination signal 166 from the execution determination unit 170 and transmits the result data from the fifth calculation unit 210 to the data line of the network 240.
175, and writes the result data d [0] to the address indicated by the write pointer 162. At the same time, the value of the write pointer 162 of the second control unit 120 subsequently increases by +1 [U001].

(Cycle # 7) In the first control unit 50 and the second memory 100, the same operation as in cycle # 5 is performed.
The next data in the array of a, b, and c is read, and the pointer
The value of 60 is further incremented by one address
[T000] [T001].

In the second arithmetic unit 30, the same processing as in cycle # 6 is performed, and the next element a [5] xa [5] in the array is calculated.

In the third arithmetic section 130, the same processing as in cycle # 6 is performed, and the next element a [4] xa [4] + c [4] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in the cycle # 6 is performed, and the next element b [3] xb [3] of the array is calculated.

In the fifth arithmetic unit 210, the same processing as in cycle # 6 is performed, and the next element a [2] xa [2] + b [2] xb [2] +
c [2] is calculated.

In the third memory 102, the same processing as in cycle # 6 is performed, and the next element d [1] in the array is stored. The value of the write pointer 162 is incremented by one.

In each of the subsequent cycles, the same processing is performed. In the first control unit 50 and the second memory 100, the processing is repeated until the pointer 60 and the write pointer 62 have the same number "100". In the second control unit 120, the executable determination signal generated by the first control unit 50 is cycled.
It counts from # 6 to cycle 105, stores the result data d [0] -d [99] for 100 cycles, and ends the program processing. Further, the first arithmetic unit 20 periodically executes the second control unit 12 at a timing determined by the execution program.
By referring to the write pointer 162 at 0 and determining whether or not the numerical value is "100", it is determined whether or not this program is terminated [S003], [S0
04].

Here, if the processing is performed only by the second calculation unit 30 / third calculation unit 130 as in [Program 1], the cycle required for the calculation processing is “2”. ,
As shown in [Program 2], when the network 240 is rearranged so that the processing is performed by the fourth arithmetic unit 200 / fifth arithmetic unit 210 via the second arithmetic unit 30 / third arithmetic unit 130. Indicates that the cycle required for the arithmetic processing is "4".

That is, on the sending side of such data, an executable determination signal indicating whether the data is executable (ie, whether or not the data exists) is added to the data, so that the data is transmitted. Even if the number of operation stages becomes variable, it is possible to similarly write the transmitted data by judging this on the data writing side. Further, by arranging a network having a plurality of paths between the memory and each operation unit and switching between the networks, more flexible programmability can be realized.

(Second Embodiment) FIG. 10 shows a data processing apparatus according to a second embodiment of the present invention.

The difference from the first embodiment is that the first embodiment
From the arithmetic unit 20 to the control units 50, 120, and 250, the array data a, b, c, d, and
The point is that a synchronizing signal 600 indicating a cycle to start sending e and f is input.

Further, what is different from the first embodiment is that the first control unit, the second memory, the second operation unit and the third operation unit, the second control unit and the third , A fourth arithmetic unit and a fifth arithmetic unit, and a network 240 between the third control unit, the fourth memory, the sixth arithmetic unit and the seventh arithmetic unit. The point is that bus switches 350 and 360 (352, 354, 356, 358, 362, 364, 366, 368) for separating the bus are provided.

The bus switch can conduct bidirectionally by turning on the switch.
By turning it off, data can be exchanged between switches individually. Therefore, by switching these bus switches, higher programmability can be obtained.

In the second embodiment, the following program is considered.

[0138] The difference between [Program 3] and [Program 2] is that the number of input data arrays to be operated is large. That is, in the description of the principle described above, three data are transmitted per one data line. Therefore, in the above-described program, it is necessary to store the data in a plurality of memories and transmit the data to the operation part.

Accordingly, the final stage of the operation (g [iii] = t1 * t2;)
, It is necessary to synchronize the input data (t1, t2) with each other. In addition, since the number of data arrays to be handled is large (6 types), the usage of the network increases accordingly.

By switching the network as follows, it is possible to realize the program. The following contents are contents generated by a compiler or the like at the time of compiling a program, and are stored, for example, as setting data in an execution program.

FIG. 11 is a diagram for explaining the flow of data in a network constituted by network configuration lines in the present embodiment.

In the data processing device shown in FIG.
In order to execute [Program 3], as shown in FIG. 11, a pair of the executable determination signal 270 of the first control unit 50 and the data line 324 of the second memory 100 is connected to the network 24.
The output bus switch 182 is switched so as to output an executable determination signal 172 and a data line 171 of 0, and a signal is output from the executable determination signal 172 and the data line 171 to the second arithmetic unit 30. Flip input bus switch 180. Also, the executable determination signal 27 from the third arithmetic unit 130
The output bus switch 184 is switched so as to output 6 and the data line 322 to the executable signal 174 and the data line 173 of the network 240.

In the bus switch 350, the bus switch 352
Is a first control unit 50, a second memory 100, a second arithmetic unit
30 and the third arithmetic unit 130 require data individually, so that it is set to OFF, and the bus switch 354 is set to the third
Since it is necessary to send the result of the calculation unit 130 to the fourth calculation unit 200, it is set to ON.

Executable determination signal 286 of third control unit 250
The output bus switch 194 is switched so as to output a pair of the data line 336 of the fourth memory 260 to the executable signal 172 and the data line 171 of the network 240,
The input bus switch 192 is configured to input a signal from the executable determination signal 172 and the data line 171 to the sixth arithmetic unit 220.
Further, the output bus switch 196 is switched so that the executable determination signal 284 and the data line 334 from the seventh arithmetic unit 230 are output to the executable determination signal 174 and the data line 173 of the network 240.

In the bus switch 360, the bus switch 262
Is a third control unit 250, a fourth memory 260, a sixth arithmetic unit
Since data is separately required by the 220 and the seventh arithmetic unit 230, it is set to OFF, and the bus switch 364 needs to send the result of the seventh arithmetic unit 230 to the fourth arithmetic unit 200. , Set to ON.

The input bus switch is set so that the executable determination signal 174 and the data line 173 are input to the fourth arithmetic unit 200.
186, and the output bus switch 190 is switched so as to output the executable determination signal 280 and the data line 328 from the fifth arithmetic unit 210 to the executable determination signal 176 and the data line 175 of the network 240. Further, the executable signal 276 and the data line 330 to the second control unit 120 are output from the executable determination signal 176 and the data line 175 of the network 240.
The input bus switch 188 is switched so that a signal is input to the input bus switch 188. As described above, the same operation as described above can be performed.

FIGS. 12 and 13 are diagrams for explaining the basic operation flow of the second embodiment of the present invention. FIG.
And FIG. 15 shows a program according to the second embodiment of the present invention.
FIG. 4 is a diagram illustrating data in each unit in [3].

Hereinafter, a second embodiment of the present invention will be described with reference to FIG.
0, FIG. 11, FIG. 12, FIG. 13, FIG. 14, and FIG.

(Before cycle # 0) The execution program and input data for the data processing device in the present invention are as follows:
Generated by a compiler or assembler and stored in advance in the first memory 10 by a program loader [S10
0].

That is, the input data arrays a, b, c, d,
e and f are stored in the first memory 10 as input data 6. Further, the execution program 4 stores a flow of the following operation according to the present invention.
Here, an external processor or the like can be considered as the program loader, but it is not a main point in the present invention.
Description is omitted.

The first arithmetic unit 20 receives the execution program of the first memory 10, and initializes the pointer 60 and the write pointer 62 of the first control unit 50 to “0”. The first arithmetic unit 20 receives the execution program in the first memory 10, and initializes the pointer 160 and the write pointer 162 of the second control unit 120 to "0". Further, a first arithmetic unit
20 receives the execution program of the first memory 10 and initializes the pointer and the write pointer of the third control unit 250 to "0". The first arithmetic unit 20 includes a first memory
Receive 10 execution programs, each input bus switch,
The connection configuration of each output bus switch and each bus switch
The setting is made by the network configuration line 400 as described above [S101].

The first control unit 50 and the third control unit 25
The executable determination unit of 0 refers to the pointer, the value of the write pointer, and the synchronization signal 600 for each cycle, and there is no executable data in the second memory 100 and the fourth memory 260, and the execution starts. Judge that it is not possible [T10
0].

Further, the executable judgment section of the second control section 120
In step 170, the executable determination signal 150 from the third arithmetic unit 130 is received every cycle, and it is determined that there is no write data [U100].

The first arithmetic unit 20 receives the execution program of the first memory 10, and the first arithmetic unit 20 receives 100-word data of the arrays a, b, and c from the first memory 10, These are sequentially written in the second memory 100. Furthermore,
The number "100" is written in the write pointer 62 of the first control unit 50.
Then, "0" is written to the pointer 60. [S102] Similarly, in the fourth memory 260, the arrays d, e, and f
100 words are written, and the third control unit 25
The 0 write pointer and the pointer are set to "100" and "0", respectively.

(Cycle # 0) The first arithmetic unit 20 receives the execution program of the first memory 10 and
Then, a synchronization signal is output as a calculation start signal [S103].

(Cycle # 1) The first control unit 50 compares the write pointer 62 with the pointer 60, and furthermore,
0, the pointer is “0” and the write pointer
Since 62 is set to "100" and the synchronizing signal is indicated, it is determined that the data can be read out, and this is output to the second memory 100, and is also transmitted to the second memory 100 via the executable signal 172 of the network 240. The data is sent to the second calculation unit 30. In the second memory 100, the data arrays a, b, c
The first data a [0], b [0], and c [0] are sent to the data line 171 of the network 240. The value of the pointer 60 is incremented by one for the array [T100], [T101].

The same operation is performed in the third control unit 250 and the fourth memory 260. Such an operation is continuously executed in each control unit and memory until the pointer becomes "100" which is the same as the value of the write pointer in each cycle.

(Cycle # 2) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 1 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 1 is performed, and the value of the pointer is further incremented by one address.

The second arithmetic unit 30 receives three types of data in the second memory 100 from the data line 171 of the network 240, performs a multiplication operation a [0] xb [0], and further performs a multiplication operation.
The executable determination signal 72 from the first control unit 50 is temporarily set to 1
Delayed by cycle, processing result data (a [0] xb [0]), c
[0] and the delayed executable determination signal
Send to The operation of the second arithmetic unit 30 is also executed for each cycle.

In the sixth arithmetic unit 220, the network 240
Of the fourth memory 260 from the data line 171 and performs a multiplication operation d [0] xe [0], and furthermore, an executable determination signal from the third control unit 250.
286 is temporarily delayed by one cycle, and the processing result data
(d [0] xe [0]), f [0] and the delayed executable determination signal are sent to the seventh arithmetic unit 230. The operation of the sixth arithmetic unit 220 is also executed for each cycle.

(Cycle # 3) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 2 is performed, and the pointer value 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 2 is performed, and the value of the pointer is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 2 is performed, and the next element a [1] xb [1] of the array is calculated.

In the sixth arithmetic section 220, the same processing as in cycle # 2 is performed, and the next element d [1] xe [1] in the array is calculated.

The third operation unit 130 receives the processing result data from the second operation unit 30, performs addition a [0] xb [0] + c [0], and further temporarily stores the second data. The execution determination signal from the arithmetic unit 30 is delayed by one cycle, and the processing result data a [0]
xb [0] + c [0] and the delayed executable determination signal are sent to the executable determination signal 174 and data line 173 of the network 240.

In the seventh arithmetic section 230, the sixth arithmetic section 220
Receive the processing result data from and add d [0] xe [0] + f [0]
, And temporarily delays the executable determination signal from the sixth arithmetic unit 220 by one cycle.
It sends d [0] xe [0] + f [0] and the delayed executable determination signal to the executable determination signal 174 and data line 173 of the network 240.

(Cycle # 4) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 3 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 3 is performed, and the value of the pointer is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 3 is performed, and the next element a [2] xa [2] in the array is calculated.

In the sixth arithmetic unit 220, the same processing as in cycle # 3 is performed, and the next element d [2] xe [2] in the array is calculated.

In the third arithmetic unit 130, the same processing as in cycle # 3 is performed, and the next element a [1] xb [1] + c [1] in the array is calculated.

In the seventh arithmetic unit 230, the same processing as in cycle # 3 is performed, and the next element d [1] xe [1] + f [1] in the array is calculated.

In the fourth arithmetic unit 200, the network 240
From the data line 173 to the processing result t1 from the third arithmetic unit 130
(= a [0] xb [0] + c [0]) and the processing result t2 (= d [0] xe [0] + f [0]) from the seventh arithmetic unit 230, And an executable judgment signal from the section at the same time, and multiply the two by t1xt2
And temporarily delays the executable determination signal by one cycle, and sends out the processing result data and the delayed executable determination signal to the fifth arithmetic unit 210.

Here, by generating a synchronization signal line in the # 0 cycle, data transmission in the same cycle from the second memory 100 and the fourth memory 260 is performed, and the fourth memory in this cycle is performed. Processing result t to the arithmetic unit 200
1. Simultaneous input of t2 is possible.

(Cycle # 5) In the first control unit 50 and the second memory 100, the same operation as in cycle # 4 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 4 is performed, and the value of the pointer is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 4 is performed, and the next element a [3] xa [3] in the array is calculated.

In the sixth arithmetic unit 220, the same processing as in cycle # 4 is performed, and the next element d [3] xe [3] in the array is calculated.

In the third arithmetic unit 130, the same processing as in the cycle # 4 is performed, and the next element a [2] xb [2] + c [2] in the array is calculated.

In the seventh arithmetic unit 230, the same processing as in cycle # 4 is performed, and the next element d [2] xe [2] + f [2] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in cycle # 4 is performed, and the next element t1xt2 in the array is calculated.

In the fifth arithmetic section 210, the fourth arithmetic section 200
, And there is no processing for addition, so that the data itself received from the fourth arithmetic unit 200 and
Further, an executable determination signal obtained by temporarily delaying the executable determination signal from the fourth arithmetic unit 200 by one cycle is combined with the executable determination signal 176 of the network 240 and the data line 175.
And send it out.

(Cycle # 6) In the first control unit 50 and the second memory 100, the same operation as in cycle # 5 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in cycle # 5 is performed, and the value of the pointer is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 5 is performed, and the next element a [4] xb [4] in the array is calculated.

In the sixth arithmetic unit 220, the same processing as in cycle # 5 is performed, and the next element d [4] xe [4] in the array is calculated.

In the third arithmetic unit 130, the same processing as in cycle # 5 is performed, and the next element a [3] xb [3] + c [3] in the array is calculated.

In the seventh arithmetic unit 230, the same processing as in cycle # 5 is performed, and the next element d [3] xe [3] + f [3] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in cycle # 5 is performed, and the next element t1xt2 in the array is calculated.

In the fifth arithmetic section 210, the same processing as in the cycle # 5 is performed, and the data from the fourth arithmetic section 200 is output as it is.

The third memory 102 receives the executable determination signal 176 of the network 240, determines that writing is possible, and transfers the result data from the data line 175 to the address of the write pointer 162 and the result data g [0 ].
At the same time, the value of the write pointer 162 of the second control unit 120 subsequently increases by +1.

(Cycle # 7) In the first control unit 50 and the second memory 100, the same operation as in cycle # 6 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 6 is performed, and the value of the pointer is further incremented by one address.

In the second operation unit 30, the same processing as in the cycle # 6 is performed, and the next element a [5] xb [5] of the array is calculated.

In the sixth arithmetic unit 220, the same processing as in cycle # 6 is performed, and the next element d [5] xe [5] in the array is calculated.

In the third arithmetic unit 130, the same processing as in cycle # 6 is performed, and the next element a [4] xb [4] + c [4] in the array is calculated.

In the seventh arithmetic unit 230, the same processing as in cycle # 6 is performed, and the next element d [4] xe [4] + f [4] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in cycle # 6 is performed, and the next element t1xt2 in the array is calculated.

The fifth processing section 210 performs the same processing as in the cycle # 6, and outputs the data from the fourth processing section 200 as it is.

In the third memory 102, cycle # 6
Is performed, the next element d [1] of the array is stored, and the value of the write pointer 162 is incremented by one.

In each of the subsequent cycles, similar processing is performed, and the first control unit 50 and the second memory 100 and the third control unit 250 and the fourth memory 260 use the pointer and the write pointer for the same. This is repeated until each value has the same number "100".

The second control unit 120 counts the executable determination signal generated by the first control unit 50 from cycle # 6 to cycle 105, and outputs the result data d [0] -d for 100 cycles. When [99] is stored, the processing of the program ends.

Further, the first arithmetic unit 20 periodically executes the second control unit 12 at the timing determined by the execution program.
By referring to the value of the write pointer 162 at 0, it is determined whether or not the numerical value is "100", and it is determined whether or not the program is terminated [S104], [S105].

That is, in [Program 3], the first arithmetic unit 20 sends a synchronization signal 600 indicating the start of reading to each of the executable determination units of the first control unit 50 and the third control unit 250.
Is output and the second memory 100
By synchronizing the array data from the fourth memory 260 and the executable determination signal, the data input in the fourth arithmetic unit 200 can be synchronized, so that when the number of array data to be executed increases, In addition, the program can be executed without error.

Further, in the network 240 between each control unit, the memory and the arithmetic unit, a bus switch 250 which isolates or connects each executable determination signal and data line,
By providing 260, a larger number of data can be connected.

(Third Embodiment) FIG. 16 shows a data processing device according to a third embodiment of the present invention.

The difference from the second embodiment is that the first embodiment
That is, delay cycle number registers 700, 710, and 720 for storing delay cycles to be inserted after the synchronization signal 600 is transmitted from the arithmetic unit 20 to each control unit. By providing the delay cycle number register, it is possible to individually set the data transmission start cycle in each control unit.

In the third embodiment, the following program is considered.

[0210] The difference between this [Program 4] and [Program 3] is that
Since the number of operation stages (0 stages) for obtaining the result data t2 is different from the number of operation stages (2 stages) of t1, in order to synchronize the operation for obtaining this result data, the difference (2 Step)
The only point is that a means of delay is required.

FIG. 17 is a diagram illustrating the flow of data in a network constituted by network configuration lines in the present embodiment.

In the data processing device shown in FIG.
To execute [Program 3], as shown in FIG. 17, a pair of the executable determination signal 270 of the first control unit 50 and the data line 324 of the second memory 100 is connected to the network 240.
The output bus switch 182 is switched so as to output the feasibility determination signal 172 and the data line 171, and the input bus is configured to input a signal to the second arithmetic unit 30 from the feasibility determination signal 172 and the data line 171. Flip switch 180.
Also, the executable determination signal 276 from the third arithmetic unit 130 and the data line 322 are connected to the executable determination signal of the network 240.
The output bus switch 184 is switched so as to output to the 174 and the data line 173.

Further, in the bus switch 350, the bus switch 352 includes the first control unit 50, the second memory 100,
Since the calculation unit 30 and the third calculation unit 130 need data individually, they are set to OFF. Also, the bus switch 354
Is set to ON because it is necessary to send the result of the third arithmetic unit 130 to the fourth arithmetic unit 200.

The pair of the executable determination signal 286 of the third control unit 250 and the data line 336 of the fourth memory 260 is
Executable judgment signal 174 and data line 17 of network 240
The output bus switch 194 is switched so that the signal is output to 3.

Further, in the bus switch 360, the bus switch 362 is set to OFF, and the bus switch 364 connects the executable determination signal 286 of the third control unit 250 and the fourth memory 260 data line 336 to the fourth memory 260. Since it needs to be sent to the arithmetic unit 200, it is set to ON.

In addition, the input bus switch 186 to the fourth arithmetic unit 200 is connected to the executable
4 and the data line 173 are switched to be input, and the executable determination signal 280 and the signal on the data line 328 from the fifth arithmetic unit 210 are output to the executable determination signal 176 and the data line 175 of the network 240. The output bus switch 190 is changed over. Furthermore, the executable signal 276 to the second control unit 120
The input bus switch 188 is switched so as to input an executable judgment signal 176 of the network 240 and the data line 175 to the data line 330. Thereby, a similar operation can be performed.

FIGS. 18 and 19 are diagrams for explaining the basic operation flow of the third embodiment of the present invention. FIG.
And FIG. 21 shows a program according to the third embodiment of the present invention.
FIG. 4 is a diagram illustrating data in each unit in [4].

A third embodiment of the present invention will be described with reference to FIGS. 16, 17, 18, 19, 20, and 21.

(Before cycle # 0) The execution program and input data for the data processing device in the present invention are as follows:
Generated by a compiler or assembler and stored in advance in the first memory 10 by the program loader [S20
0].

That is, the input data arrays a, b, c, d
Are stored in the first memory 10 as input data 6. Further, the execution program 4 stores a flow of the following operation according to the present invention.

Here, an external processor or the like can be considered as the program loader. However, since it is not a main point in the present invention, the description is omitted.

The first arithmetic unit 20 receives the execution program in the first memory 10, and initializes the pointer 60 and the write pointer 62 of the first control unit 50 to “0”. The first arithmetic unit 20 receives the execution program in the first memory 10, and initializes the pointer 160 and the write pointer 162 of the second control unit 120 to "0". Furthermore, one operation unit 20
Receives the execution program in the first memory 10 and
The pointer and the write pointer of the control unit 250 are initialized to "0". The first arithmetic unit 20 includes a first memory
10 execution programs are received, and the connection configuration of each input bus switch, each output bus switch, and the bus switch of the network 240 is set by the network configuration line 400.
[S201].

The first control unit 50 and the third control unit 25
In each of the executable determination units of 0, the value of the pointer, the value of the write pointer, and the synchronization signal 600 are referred to in each cycle, and the executable data is stored in the second memory 100 and the fourth memory 26.
It does not exist in 0 and it is determined that execution cannot be started
[T200].

Further, the executable determination section of the second control section 120
At 170, an executable determination signal is received from the third arithmetic unit 130 for each cycle, and it is determined that there is no write data [U200].

The first arithmetic unit 20 receives the execution program of the first memory 10, receives the data of 100 words of the arrays a, b, and c from the first memory 10, and sequentially receives these data in the second memory 10. Write to memory 100. Further, a first control unit
The number "100" is assigned to the 50
"0" is written into 60 respectively. The first arithmetic unit 20 further includes:
The execution program of the first memory 10 is received, and similarly, 100 words of the arrays d, e, and f are written in the fourth memory 260, and the write pointer and the pointer of the third control unit 250 are respectively set to "100". And "0".

In addition, the first arithmetic unit 20 includes a first memory
Upon receiving the ten execution programs, "0" is stored in the delay cycle register 700 of the first control unit 50 and "2" is stored in the third delay cycle register 720 [S202].

(Cycle # 0) The first arithmetic unit 20 receives the execution program of the first memory 10, and outputs a calculation start signal to the synchronization signal line [S203].

(Cycle # 1) The first control unit 50 compares the value of the write pointer 62 with the value of the pointer 60, further refers to the synchronization signal line, and determines that the value of the pointer 60 is “0”. Since the value of the write pointer 62 is "100", the synchronizing signal is indicated, and the value of the delay cycle register 700 is "0", it is determined that the data can be read. And to the second arithmetic unit 30 via the executable determination signal 172 of the network 240.

The second memory 100 sends the first data a [0], b [0], c [0] of the data arrays a, b, c to the data line 171 of the network 240 based on this signal. The value of the pointer 60 is incremented by one for the array.
[T200], [T201], [T202]. The operations of the first control unit 50 and the second memory 100 are thereafter executed for each cycle.

The third control unit 250 compares the value of the write pointer with the value of the pointer, and further refers to the synchronization signal line to determine that the start cycle has started [T200].

However, the pointer is “0”, the write pointer is set to “100”, and the synchronization signal 600 is indicated, but the value of the delay cycle register 720 of the third control unit 250 is “2”. So, in order to be able to read,
It is determined that two more cycles are required. Here, it starts counting that there are two more cycles until the start cycle [T201].

(Cycle # 2) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 1 is performed, and the value of the pointer 60 is further incremented by one address.

The third control unit 250 compares the value of the write pointer with the value of the pointer, and further refers to the synchronization signal line to determine that the start cycle has started [T200].

However, the pointer is "0", the write pointer is set to "100", and the synchronizing signal 600 is indicated, but the value of the delay cycle register 720 of the third control unit 250 is "2". Therefore, in order to be able to read,
It is determined that one more cycle is needed [T201].

The second arithmetic unit 30 receives three types of data in the second memory 100 from the data line 171 of the network 240, performs a multiplication operation a [0] xb [0], and further performs a multiplication operation.
The executable determination signal 72 from the first control unit 50 is temporarily set to 1
Delayed by the cycle, processing result data (a [0] xb [0]), c
[0] and the delayed executable determination signal
Send to The operation of the second arithmetic unit 30 is also executed for each cycle.

(Cycle # 3) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 2 is performed, and the value of the pointer 60 is further incremented by one address.

The third control unit 250 compares the value of the write pointer with the value of the pointer, and further refers to the synchronization signal line 600 to determine that the start cycle has started [T20].
0].

Since the pointer is "0", the write pointer is set to 100, the synchronization signal 600 is indicated, and it is determined that the start cycle has been reached, this determination is made by the possibility determination signal 174 of the network 240. Sent [T201].

The fourth memory 260 sends the first data d [0] of the data array d to the data line 173 of the network 240 based on this signal. The value of the pointer of the third control unit 250 is incremented by one for the array [T
202].

In the second arithmetic unit 30, the same processing as in the cycle # 2 is performed, and the next element a [1] xb [1] of the array is calculated.

The third operation unit 130 receives the processing result data from the second operation unit 30 and performs addition a [0] xb [0] + c [0]. From the execution result determination signal a [0]
xb [0] + c [0] and the delayed executable decision signal are sent to the executable decision signal 174 and the data line 173 of the network 240.

(Cycle # 4) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 3 is performed, and the value of the pointer 60 is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 3 is performed, and the next element a [2] xa [2] in the array is calculated.

In the third arithmetic unit 130, the same processing as in the cycle # 3 is performed, and the next element a [1] xb [1] + c [1] in the array is calculated.

In the fourth arithmetic unit 200, the network 240
The processing result data t1 (= a [0] xb [0] + c [0]) from the second arithmetic unit 30 and the data t2 (= d [0]) from the fourth memory 260 from the data line 173 of FIG. ) And an executable determination signal from each control unit at the same time, and multiply the two by t1xt2,
Further, the executable determination signal is temporarily delayed by one cycle, and the processing result data and the delayed executable determination signal are sent to the fifth arithmetic unit 210.

Here, the synchronization signal 600 is generated in the # 0 cycle, and the second memory 100 immediately starts sending data in the next cycle because the delay cycle is "0".
Further, since the third control unit 250 that controls the fourth memory 260 delays by two cycles, it is possible to simultaneously input the data t1 and t2 to the fourth arithmetic unit 200 in this cycle. ing.

(Cycle # 5) In the first control unit 50 and the second memory 100, the same operation as in cycle # 4 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 4 is performed, and the value of the pointer is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 4 is performed, and the next element a [3] xa [3] in the array is calculated.

In the third arithmetic unit 130, the same processing as in cycle # 4 is performed, and the next element a [2] xb [2] + c [2] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in cycle # 4 is performed, and the next element t1xt2 in the array is calculated.

In the fifth arithmetic section 210, the fourth arithmetic section 200
Since the processing result data from the fourth arithmetic unit 200 is not received and there is no processing for the addition, the data itself coming from the fourth arithmetic unit 200 and the executable judgment signal from the fourth arithmetic unit 200 are temporarily delayed by one cycle. The feasibility determination signal is sent to the feasibility determination signal 176 and the data line 175 of the network 240.

(Cycle # 6) In the first control unit 50 and the second memory 100, the same operation as in cycle # 5 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 5 is performed, and the value of the pointer is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 5 is performed, and the next element a [4] xb [4] in the array is calculated.

The third arithmetic unit 130 performs the same processing as in cycle # 5, and calculates the next element a [3] xb [3] + c [3] in the array.

In the fourth arithmetic unit 200, the same processing as in cycle # 5 is performed, and the next element t1xt2 in the array is calculated.

In the fifth arithmetic section 210, the same processing as in the cycle # 5 is performed, and the data from the fourth arithmetic section 200 is output as it is.

The third memory 102 receives the execution determination signal 176 of the network 240, determines that writing is possible, and transfers the result data from the data line 175 to the address of the write pointer 162 to the result data g [0]. Write as At the same time, the value of the write pointer 162 of the second control unit 50 is thereafter increased by +1.

(Cycle # 7) In the first control unit 50 and the second memory 100, the same operation as in the cycle # 6 is performed, and the value of the pointer 60 is further incremented by one address.

In the third control unit 250 and the fourth memory 260, the same operation as in the cycle # 6 is performed, and the value of the pointer is further incremented by one address.

In the second arithmetic unit 30, the same processing as in cycle # 6 is performed, and the next element a [5] xb [5] in the array is calculated.

In the third arithmetic unit 130, the same processing as in the cycle # 6 is performed, and the next element a [4] xb [4] + c [4] in the array is calculated.

In the fourth arithmetic unit 200, the same processing as in cycle # 6 is performed, and the next element t1xt2 in the array is calculated.

In the fifth arithmetic section 210, the same processing as in the cycle # 6 is performed, and the data from the fourth arithmetic section 200 is output as it is.

In the third memory 102, the same processing as in cycle # 6 is performed, and the next element d [1] in the array is stored.
The value of the write pointer 162 is incremented by one.

In each of the subsequent cycles, the same processing is performed. The first control unit 50 and the second memory 100 and the third control unit 250 and the fourth memory 260 store the pointer value and the write pointer value. This is repeated until the value reaches the same number "100". Also, the second control unit 120 outputs the executable determination signal generated by the first control unit 50 from cycle # 6 to cycle
Count up to 105, and result data d for 100 cycles
When [0] -d [99] is stored, the processing of the program ends. Further, the first arithmetic unit 20 periodically refers to the write pointer 162 in the second control unit 50 at a timing determined by the execution program, and sets the numerical value to “100”.
Then, it is determined whether or not the program has ended, and the end of the program is determined [S204] and [S205].

That is, when a combination of networks to be processed is determined in advance, a delay cycle is set in the delay cycle number register in each control unit, so that data can be input from each memory at a different timing. become.

As described above, the third embodiment is different from the above-described principle, [Program 1] in the first and second embodiments.
~ [Program 3] can be executed, so it can be said that it is the most flexible in programmability.

In the above description, the executable determination signal 7
Although 2,144,150,172 were used as valid data identification signals,
This executable determination signal is calculated by the arithmetic unit 30.130.200.210.220.230.
May be interpreted as an enable signal for the calculation (processing) in.

In the above description, each of the arithmetic units 30, 130, 2
Each of the operation units 00, 210, 220, and 230 has one operation cycle, but the present invention is not limited to this, and each operation unit may be an operation unit having two or more operation cycles. In this case, each of the delay units built in each operation unit delays the executable determination signal (valid data specifying signal) by the number of cycles equal to the number of operation cycles of its own operation unit. Furthermore, the present invention is not limited to the case where the execution determination signal is delayed for each operation unit. It only has to be entered.

[0272]

As described above, according to the data processing apparatus of the present invention, the connection between the memory and the computing unit can be switched over a network to read data. At the same time, a valid data specifying signal is added to this data, and when this data is stored in the storage unit with the calculation result data calculated by the calculating unit, the valid data specifying signal is simultaneously input to this storage unit. Even if the number of operation stages is different, this operation result data can be recognized as valid data and can be stored in the storage unit. Therefore, it is possible to provide a data processing device which is versatile and adaptable to various multimedia applications.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a data processing device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation flow of a first calculation unit based on the same principle.

FIG. 3 is a diagram illustrating an operation flow of first and second control units according to the same principle.

FIG. 4 is an explanatory diagram of a data value of each unit according to the same principle.

FIG. 5 is a diagram showing a configuration of a data processing device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing an example of a data flow in the data processing device.

FIG. 7 is a diagram showing another example of a data flow in the data processing device.

FIG. 8 is an explanatory diagram of a data value of each unit in another example of a data flow in the data processing device.

FIG. 9 is an explanatory diagram of data values in other units in the same example.

FIG. 10 is a diagram illustrating a configuration of a data processing device according to a second embodiment of the present invention.

FIG. 11 is a diagram showing an example of a data flow in the data processing device.

FIG. 12 is a diagram showing an operation flow of a first arithmetic unit in the data processing device.

FIG. 13 is a diagram showing an operation flow of first and second control units of the data processing device.

FIG. 14 is an explanatory diagram of a data value of each unit in an example of a data flow in the data processing device.

FIG. 15 is an explanatory diagram of data values in other units in the same example.

FIG. 16 is a diagram illustrating a configuration of a data processing device according to a third embodiment of the present invention.

FIG. 17 is a diagram showing an example of a data flow in the data processing device.

FIG. 18 is a diagram showing an operation flow of a first calculation unit in the data processing device.

FIG. 19 is a diagram showing an operation flow of first and second control units of the data processing device.

FIG. 20 is an explanatory diagram of a data value of each unit in an example of a data flow in the data processing device.

FIG. 21 is an explanatory diagram of data values in other units in the same example.

[Explanation of symbols]

2 Program loader 4 Execution program 6 Input data 10 First memory (main data storage unit) 12, 22, 24, 32, 34, 36 Data line 20 First operation unit (Data transfer unit) 30 Second operation unit (Calculation unit) 38 Multiplication unit (Processing unit) 40,146 Data latch 42,148 Output selector 50 First control unit (Control unit) 60,160 Pointer 62,162 Write pointer 64,65 Pointer setting line 66,67 Write Pointer setting line 68 Address line 70,170 Executable judging unit (judging unit) 72,144,150,172 Executable judging signal (valid data specifying signal) 100 Second memory (data storing unit) 102 Third memory (other data storing unit) 120 No. 2 control unit (other control unit) 130 3rd operation unit (operation unit) 136 addition unit (processing unit) 140,142 executable judgment signal latch (delay unit) 141 delay circuit 171 to 178 bus 182,184,190,194,196 output bus switch 180,186,188,192 input Ba Switch 200 fourth operation unit 210 fifth operation unit 212,232 data line 220 sixth operation unit 230 seventh operation unit 240 network 250 third control unit (control unit) 260 fourth memory (data Storage unit) 350,352,354,356,358 360,362,364,366,368 Bus switch 400 Data processing device configuration line 600 Synchronous signal line 700,710,720 Delay cycle number register

Claims (15)

[Claims] A data storage unit for storing one or more data storage units; a plurality of operation units; a network for switching a connection between the data storage unit and the plurality of operation units; When reading data stored in the data storage unit,
A control unit that outputs a valid data specifying signal indicating that the data to be read is valid data; a control unit that receives a valid data specifying signal from the control unit; Or a delay circuit for delaying and outputting the received valid data specifying signal by the number of cycles until a result calculated by the plurality of calculation units is obtained. 2. The delay circuit according to claim 1, wherein the delay circuit includes a plurality of delay units provided corresponding to the plurality of operation units, and each of the delay units includes the effective number of cycles required by the corresponding operation unit for the operation. 2. The data processing device according to claim 1, wherein the data specifying signal is output with a delay. 3. The control unit further comprises: a write pointer to which the number of data stored in the data storage unit is given; a pointer to which the number of times of reading data from the data storage unit is sequentially given; 3. The data processing according to claim 1, further comprising: a determination unit that compares a value of the pointer with a value of the pointer and outputs a valid data specifying signal when the value of the pointer is equal to or less than the value of the write pointer. apparatus. 4. The effective data specifying signal is an executable determination signal indicating that there is data that can be processed in the data storage unit. The data processing device according to claim 1. 5. A main data storage unit in which data is stored in advance, and a data transfer unit that transfers data stored in the main data storage unit to the plurality of data storage units, 3. The data processing apparatus according to claim 1, wherein the transfer unit outputs a synchronization signal for instructing to simultaneously read data from the plurality of data storage units to the control unit. 6. A control unit, corresponding to each data storage unit,
6. The data processing apparatus according to claim 5, wherein a number equal to the number of data storage units is provided. 7. Each of the control units has a delay cycle number register for storing a set cycle number for delaying data reading after the input of the synchronization signal, and when the delay cycle number has elapsed after the input of the synchronization signal, 7. The data processing apparatus according to claim 6, wherein data reading is started. 8. The method according to claim 1, wherein the number of operation stages of data by the plurality of operation units after the switching of the connection by the network is different from the number of operation stages before the switching. Data processing equipment. 9. The data processing apparatus according to claim 1, wherein the network switches connections so that data is output from two or more data storage units to the same operation unit. 10. The network outputs data from one data storage unit to one operation unit, and then transmits the operation result of this operation unit and data of another data storage unit to another operation unit. 8. The data processing device according to claim 1, wherein the connection is switched so as to output the data. 11. The information processing apparatus according to claim 1, further comprising: a main data storage unit in which data is stored in advance, wherein the connection switching information by the network is stored in the main data storage unit. 2. The data processing device according to 2. 12. An output bus switch for outputting data and valid data specifying signals from a data storage unit and a control unit, respectively, and an input bus switch for inputting the received data and valid data specifying signal to an arithmetic unit. The data processing device according to claim 1, wherein the data processing device comprises: 13. The network includes: a plurality of buses; and a bus switch arranged for each of the buses, wherein the bus switch is conductive to allow data transmission;
13. The data processing device according to claim 12, wherein the data transmission is prohibited by being turned off. 14. The data processing device according to claim 1, wherein the plurality of arithmetic units perform mutually different arithmetic operations. 15. A control unit for receiving a valid data specifying signal from a calculation unit for performing a last operation via a network and outputting a write command, and a control unit for finally obtaining from the calculation unit for performing the last calculation. 2. A data storage unit for receiving an operation result, receiving a write command from the another control unit, and storing the finally obtained operation result. 2. The data processing device according to 2.