JPH117414A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit which performs error measures with an MPU even when noise overlays a clock signal at the time of data transfer by providing an error detection function and adding an error detection terminal. SOLUTION: When noise is introduced from an SCL terminal 12, an internal EN signal deviates from a normal signal, sends an error signal, and with the error signal, the error signal is sent from an ER terminal 15 that is an error detection circuit terminal through a DFF circuit 6 for error detection and a gate 7. When the error signal is transferred to an MPU, an input signal including the error signal is inputted to a Data set in the MPU, a signal is successively sent from an LSB out to an MSB out, a signal is sent to ER Flag Check and the ER Flag Check decides whether it is a normal signal or an error signal. When it is decided as an error signal, it is returned to the Data set again, a signal is successively sent from the LSB out to the MSB out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit of a controller driver for driving a display device such as a liquid crystal panel, a plasma display and a printer, and to a semiconductor integrated circuit having a data transfer function.

[0002]

2. Description of the Related Art FIG. 4 shows a main block diagram of a semiconductor integrated circuit of a controller driver for driving a liquid crystal display device having a serial data transfer function. Here, a conventional main block diagram of a semiconductor integrated circuit related to the present invention is shown. The signal from the MPU 50 is the CS terminal 11, the SCL
The data is transmitted to the input / output buffer 40 via the terminal 12, the SDA terminal 13, and the RS terminal 14. The signal from the input / output buffer 40 is transmitted to the instruction register circuit 4a and the data register circuit 4b.
Signals from a and 4b are transmitted to an internal processing circuit 5 including a decoder. FIG. 5 is a detailed block diagram of the main part of FIG.
Signals such as a CS signal, an RS signal, an SDA signal, and an SCL signal are input to the input / output buffer 40 through the terminals 11 to 14 from the MPU 50 in FIG. The CS signal and the SCL signal are input to the binary counter circuit 2 and the gate 1 via the inverter 30. The SDA signal is input to the shift register via the inverter 30. The signal of the input / output buffer 40 is input to a register 4 such as an instruction register or a data register.
Is input to an internal processing circuit 5 including a decoder. Here, MPU is a microprocessor unit, C
S is chip select, RS is data register switch,
SDA indicates a data input, and SCL indicates a clock. Generally, such an apparatus has a serial (sequential), parallel (parallel) 4-bit, and parallel 8-bit interface, and thereby exchanges image data and instruction data with an MPU (microprocessor unit). I do. By the way, in the actual field, this MPU5
When data is exchanged between 0 and the input / output buffer 40, for example, noise may be present on the transmission path 52 of the clock signal connecting the MPU 50 and the input / output buffer 40,
Data may not be transferred properly. In addition, as the transfer speed increases with an increase in the display capacity of the display device, and the frequency characteristics of the IC itself improve due to the adoption of fine processing rules, the noise margin of the system tends to decrease. As a countermeasure, there is an example in which an analog filter is added to the input / output transmission line.

Here, the relationship between the MPU and the semiconductor integrated circuit of the controller drive for liquid crystal drive is that
In U, the slave is associated with the semiconductor integrated circuit of the controller drive for driving the liquid crystal. FIG. 6 is a timing chart of each signal. (A) CS signal, (b) S signal
(C) shows the RS signal, (d) shows the SDA signal, and (e) shows the waveform (1 state or 0 state) of the internal EN signal. FIG. 8 is a conventional flowchart in the MPU. In the case of serial, an 8-bit instruction or data is sequentially input to the Data set in the MPU, and the data is transmitted from the least significant bit (LSB) and sent to the most significant bit (MSB).
At the timing of the most significant bit, the internal EN (internal enab
The 8-bit parallel data aligned with le) is transmitted.

[0004]

However, FIG. 7 (b)
As shown in FIG. 7, when the noise 60 which is an error source is loaded on the SCL signal transmission line (52 in FIG. 4) on the one-shot SCL signal, the timing of the internal EN is shifted and erroneous data (error Signal) enters the internal EN and the system malfunctions. In the normal case, as shown in the flowchart of FIG. 8, when data is input to the Data set in the MPU, the data is sequentially sent to the next step, so that even if there is a transfer error, it cannot be detected. Therefore, when applied to a mobile phone or the like, every time a malfunction occurs due to noise, it is necessary for the user to reset it, which places a burden on the user.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a semiconductor integrated circuit of a controller driver for a display device, which can take an error countermeasure without a user's awareness.

[0006]

In order to achieve the above object, in a semiconductor integrated circuit (IC), a delay type flip-flop (DF) for error detection is provided in a serial interface having a counter circuit and a register circuit.
F) At least a circuit, a gate connected to the delay type flip-flop circuit, and an error detection terminal (ER terminal) connected to the gate are added.

By providing the error detection terminal for outputting the error signal, the MPU is connected to the error detection terminal.
, So that the MPU can take countermeasures against errors without the user being conscious of it. The semiconductor integrated circuit is a semiconductor integrated circuit having a function of a controller driver for driving a display device.

It is preferable that the display device driving controller driver is any one of a liquid crystal display device driving controller driver, a plasma display device driving controller driver and a printer driving control driver.

[0009]

FIG. 1 is a main block diagram of an embodiment of the present invention. In this main block diagram, a DFF circuit 6 for error detection, a gate 7, and an ER terminal 15 are added to an input / output buffer (40 in FIG. 5) which is a component of a conventional serial interface unit. In FIG. 1, a binary counter circuit 2, a shift register circuit 3, a register circuit 4 including an instruction register circuit 4a and a data register circuit 4b in FIG. 4, an internal processing circuit 5 including a decoder, and an added error detecting circuit The DFF circuit 6, the gate 7, and the ER terminal 15 are connected as shown in FIG.
The SCL terminal 12, SDA terminal 13, and RS terminal 14 are connected to an MPU (not shown). When noise is introduced from the SCL terminal 12 as shown in FIG. 7 described above, the internal EN signal is shifted from the normal signal 70 shown by the dotted line in FIG. According to the error signal 80, an error signal 81 as shown by a solid line in FIG. 7 (f) is transmitted from the ER terminal 15 as an error detection terminal through the DFF circuit 6 and the gate 7.
7A shows a CS signal, and FIG. 7B shows an SCL signal.
(E) shows the internal EN signal, and (f) shows each waveform (1 state or 0 state) of the ER signal (error signal).

This error signal 81 is not shown in M
When transferred to the PU, the signal is processed according to the flowchart shown in FIG. An input signal including the error signal is input to the Data set in the MPU, and the LSB out
From MSB out to ER Fl
The signal is sent to the ag check. This ER Fla
g Check determines whether the signal is a normal signal or an error signal.
If it is determined that the signal is an error signal, the signal is returned to Data set again, and signals are sequentially transmitted from LSB out to MSB out. Then, the process proceeds to the next step only when a normal signal is input. In this way, it is possible to take measures to prevent the error signal from being transferred to the next step in the MPU. That is, by providing the ER terminal 15, it is possible to take measures against an error signal in the MPU without bothering the user. Further, as another method of this measure, there is a method as shown in FIG. ER
When the flag check determines that the signal is an error signal, the MPU performs a process of changing the clock rate of the signal entering the data set to half, that is, giving an instruction to the MPU to change the frequency of the clock signal to a half clock signal.
Even if an error signal comes in from the SCL terminal 12 (that is, even if it gets on the transmission line of the clock signal), it is possible to take measures against the error signal by hiding the error signal in a normal signal. That is, by providing the ER terminal 15 which is an error detection terminal, the MPU can take various measures against transfer noise.

[0011]

According to the present invention, an error detection function is provided in a semiconductor integrated circuit of a controller driver for a display device and an error detection terminal is added, so that a noise is generated on a clock signal at the time of data transfer. Also,
A semiconductor integrated circuit that can take measures against errors with the MPU can be provided. This eliminates the need for the user of, for example, a mobile phone to reset itself upon malfunction, thereby greatly reducing the burden on the user.

[Brief description of the drawings]

FIG. 1 is a main block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart inside an MPU to which the present invention is applied;

FIG. 3 is another flowchart inside the MPU to which the present invention is applied;

FIG. 4 is a main block diagram of a semiconductor integrated circuit of a conventional controller driver for driving a liquid crystal display device having a data transfer function.

FIG. 5 is a detailed block diagram of a main part of FIG. 4;

FIG. 6 is a timing chart of each signal.

FIG. 7 is a timing chart when noise is superimposed on the SCL signal.

FIG. 8 is a flowchart inside a conventional MPU.

[Explanation of symbols]

 Reference Signs List 1 gate 2 binary counter circuit 3 shift register circuit 4 register circuit 4a instruction register circuit 4b data register circuit 5 internal processing circuit 6 DFF circuit 7 gate 11 CS terminal 12 SCL terminal 13 SDA terminal 14 RS terminal 15 ER terminal 30 inverter 31 inverter 40 I / O buffer 50 MPU 52 SCL transmission line

Claims (3)

[Claims] In a semiconductor integrated circuit (IC), a serial interface unit having a counter circuit and a register circuit has a delay type flip-flop (DFF) circuit for error detection and a gate connected to the delay type flip-flop circuit. And at least an error detection terminal (ER terminal) connected to the gate. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a controller driver for driving a display device. 3. The semiconductor integrated circuit according to claim 2, wherein the controller driver for driving the display device is one of a controller driver for driving a liquid crystal display device, a controller driver for driving a plasma display device, and a controller driver for driving a printer. circuit.