JPH1169777A - Power-supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a power-supply device in which a switching loss is reduced and whose efficiency is enhanced, by installing a means which increases the impedance of a control means as viewed from a capacitor during a period in which a turning-off operation is maintained. SOLUTION: A drive part 4 is installed inside a control circuit. In the drive part 4, a series circuit which is composed of a current amplifier circuit constituting a totem pole circuit by connecting complementary FET's Q11 ', Q12 ' and a transistor Q13 in series is connected to a control-circuit power supply Vcc . A square-wave control signal is inputted from an oscillation circuit to common- connected gates of the FET's Q11 ', Q12 '. A polar synchronizing signal which is synchronized with the polarity of an AC power supply is inputted to the base of the transistor Q13 . When they are inputted, a period in which a turning- off operation is maintained for a period which is longer than a turning-off period in a period in which an ON/OFF control operation is repeated is set. During the set period, the impedance of the control circuit is increased as viewed from a capacitor C0 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply having a switching circuit for performing power conversion.

[0002]

2. Description of the Related Art Conventionally, a chopper circuit has been used as a power conversion circuit.
And a chopper circuit and an inverter circuit.
There is a power supply that shares the switching element of the
You. FIG. 14 shows a circuit of this power supply device.
In the circuit of the source device, the capacitor C₁And FETQ₁And FE
TQ_TwoA first switching circuit comprising a series circuit of
FETQ_ThreeAnd FETQ_FourA second switch composed of a series circuit of
Switching circuit and diode D_FiveAnd diode D₆Directly
Column circuits are connected in parallel with each other, and FET Q₁And FETQ_Two
And the diode D_FiveAnd diode D₆Connection point
Between the filter circuit F and the inductor L₁Exchange through
Power supply Vs is connected. And FETQ₁And FETQ
_TwoConnection point and FET Q_ThreeAnd FETQ_FourBetween connection points
Has a load L and an inductor L_TwoThe series circuit with
One end of L is FETQ₁And FETQ_TwoConnection points and
Connected to match. D₁~ D_FourIs FETQ
₁~ Q_FourParasitic diode, FET Q₁~ Q_Four
Are switching elements that cannot block reverse current.
You.

[0003] Thus to this power supply device, by a applying a drive signal V _Q1G ~V _Q4G from the control circuit 1 to Heto terminal of FETs Q ₁ to Q _4, FETs Q ₁ and FETs Q ₂
Period to turn on the FETs Q _2, Q ₃ when the polarity of the connection point side half cycle of the AC power source Vs to be negative, FET
An operation is performed in which a period in which Q ₁ and Q ₃ are turned on and a period in which all FETs Q _{1 to} Q ₄ are turned off are sequentially repeated. The FETs Q ₁ and period in which the polarity of the connection point side FETs Q ₂ turns on the FETs Q _1, Q ₄ when the half cycle of the AC power source Vs to be positive, the period of turning on the FETs Q _2, Q _4, FET
Operation period to turn off the Q ₁ to Q ₄ are sequentially repeated is made.

The illustrated power supply device is a boost chopper circuit.
A first power conversion circuit and a step-down chopper circuit
And a second power conversion circuit.
TQ ₁, Q_TwoAre shared by both power conversion switching circuits.
Have been. Next, FETQ₁, Q_TwoThe polarity of the connection point
The operation of the pole AC power supply Vs in a half cycle will be described.
You.

First, when the FETs Q ₁ and Q ₃ are turned on, a magnetic energy is stored in the inductor L ₁ as a choke of the boost chopper circuit, and the FETs Q ₂ and Q ₃ are turned on and the FETs Q _{1 to} Q ₄ are turned off. period is a period for emitting the magnetic energy stored in the inductor L _1. That is, it operates as a first power conversion circuit. Next, in the period of turning on the FETs Q _2, FETs Q ₃ becomes a period for accumulating magnetic energy in the inductor L ₂ as a choke of the step-down chopper circuit, the period for turning off the duration and FETs Q ₁ to Q ₄ turns on the FETs Q _1, Q ₃ is magnetic energy stored in the inductor L ₁ becomes the period of releasing.
That is, it operates as a second power conversion circuit.

Next, these will be described focusing on the current loop. For the sake of explanation, the AC power supply Vs and the inductor L
_{In one} series circuit, one end of the AC power supply Vs is connected to the FET Q
_1, the connection point of Q _2, the one end of the inductor L ₁ using a circuit connected to the anode side of the diode D _5. First FE
During the period when TQ ₂ and Q ₃ are turned on, as shown in FIG. 15A, the first power conversion circuit is an inductor L ₁ → diode D ₅ → capacitor C ₁ → FET Q ₂ → AC power supply Vs → inductor L _The state where a current flows through the closed loop ₁ and the capacitor C ₁ → FE
TQ ₃ → inductor L ₂ → load L → FETs Q ₂ → and a state in which current flows through the closed loop of the capacitor C ₁ which is a period T ₁ which simultaneously satisfied.

Next, while the FETs Q ₁ and Q ₃ are turned on,
As shown in FIG. 15 (b), a state in which a current flows through a closed loop of an inductor L ₁ → diode D ₅ → FET Q ₁ → AC power supply Vs → inductor L _{1 as} a _first power conversion circuit; As a circuit, inductor L ₂ →
A period T ₂ during which a state where a current flows through the closed loop of the load L → FET Q ₁ → FET Q ₃ → inductor L ₂ is simultaneously established.
It is.

Further, a period during which the FETs Q _{1 to} Q ₄ are turned off is
As the first power conversion circuit, as shown in FIG. 15C, the inductor L ₁ → the diode D ₅ → the capacitor C ₁
→ FET Q ₂ → AC power supply Vs → State where current flows through the closed loop of inductor L ₁ , and as the second power conversion circuit,
Inductor L ₂ → the state where the load L → FETQ ₂ → FETQ ₄ → current flows in the closed loop of the inductor L ₂ is the period T ₃ which simultaneously satisfied.

By the way the positive direction of the current due to the second power conversion circuit which flows into the FETs Q ₂ in the period T _1, the reverse current of the first power conversion circuit, by being superimposed flows FETs Q ₂ The current is reduced and switching losses are reduced. The positive direction of the current due to the first power conversion circuit which flows into the FETs Q ₁ in the period T ₂ also by the reverse current of the second power conversion circuit is superimposed, the current flowing through the FETs Q ₁ reduction As a result, switching loss is reduced.

[0010] and the positive direction of the current due to the second power conversion circuit flowing Furthermore the FETs Q ₂ in the period T _3, the reverse current of the first power conversion circuit, by being superimposed on the FETs Q ₂ The flowing current is reduced, and the switching loss is reduced. FIGS. 16A to 16C show a state in which a current flows when the AC power supply Vs has the opposite polarity to the above case (FIGS. 15A to 15C).

FIG. 17 shows waveforms at various points during the above operation.
FIG. 3A shows the inductor L ₁Current I_L1The same
Figure (b) shows the inductor L_TwoCurrent I_L2And FIG.
Current I_L2To I_L1(D) is the current obtained by subtracting
ETQ₁Current I_Q1(E) shows the FET Q_TwoCurrent
I_Q2FIG._ThreeCurrent I_Q3The same figure
(G) is FETQ_FourCurrent I_Q4(H) to (k) in FIG.
Is the drive signal V_Q1G~ V_{Q4 G}And t₀~ T₁Period is
T₁, T₁~ T_TwoPeriod is T_Two, T_Two~ T_ThreePeriod is T
_ThreeBecomes

[0012] Next, description or when the power supply voltage is low, the operation of such a case the inductance of the inductor L ₁ is large. In the same manner as described above, the operation of the AC power supply Vs in which the polarity at the connection point side of the FETs Q ₁ and Q ₂ is a negative polarity during a half cycle will be described focusing on the current loop. First, during the period when the FETs Q ₂ and Q ₃ are turned on, the second power conversion circuit is used as shown in FIG.
(A), the a capacitor C ₁ → FETQ ₃ → inductor L ₂ → load L → FETs Q ₂ → period T ₁ which state is established in which current flows through the closed loop of the capacitor C _1.

Next, while the FETs Q ₁ and Q ₃ are turned on,
As shown in FIG. 18B, the first power conversion circuit has a state in which a current flows through a closed loop of an inductor L ₁ → diode D ₅ → FET Q ₁ → AC power supply Vs → inductor L ₁ and a second power conversion circuit. As a circuit, inductor L ₂ →
A period T ₂ during which a state where a current flows through the closed loop of the load L → FET Q ₁ → FET Q ₃ → inductor L ₂ is simultaneously established.
It is.

[0014] In further period to turn off the FETs Q ₁ to Q _4, and the current flowing through the inductor L _1, the two states are present depending on the magnitude relationship between the current flowing through the inductor L _2. That the absolute value of the current inductor L ₁ is smaller than the absolute value of the current of the inductor L _2, a first power conversion circuit, alternating as shown in Fig. 18 (c) power source Vs
→ Inductor L ₁ → Diode D ₅ → FET Q ₁ → State in which a current flows in the closed loop of the AC power supply Vs. As a second power conversion circuit, inductor L ₂ → load L → FET Q ₁
→ a state where the current flows through the closed loop of the capacitor C ₁ → FETs Q ₄ there is a time period T ₃ which simultaneously satisfied.

[0015] The absolute value of the current inductor L ₁ is, if it matches the absolute value of the current inductor L _2, counteracted and the current from the current and the second power conversion circuit from the first power conversion circuit with each other the result, FETs Q _1, next sum 0 of the current flowing into the Q _2, virtually shared by both the power conversion circuit, within both the power conversion circuit, the current through the FETs Q _1, Q ₂ which are above the shared Does not constitute a closed loop of
As shown in FIG. 18D, the inductor L ₁ → the diode D ₅ → the capacitor C ₁ → the FET Q ₄ → the inductor L ₂ →
There is a load L → AC power source Vs → period T ₄ to a state in which a current flows in the closed loop of the inductor L ₁ is satisfied.

With respect to the first power conversion circuit constituting the boost chopper circuit as described above, periods T ₂ and T ₃ are periods during which energy is stored in inductor L ₁ acting as a choke of the boost chopper, and period T 2 ₄ is a period for emitting the energy stored in inductor L _1. Regarding the second power conversion circuit constituting the step-down chopper circuit, the period T ₁ is a period in which energy is stored in the inductor L ₂ acting as a choke of the step-down chopper, and the periods T ₂ , T ₃ and T ₄ are the inductors L _This is the period during which the energy stored in ₂ is released.

[0017] Incidentally the positive direction of the current due to the first power conversion circuit which flows into the FETs Q ₁ in the period T _2, the reverse current of the second power converter circuit, by being superimposed, through the FETs Q ₁ The current is reduced and switching losses are reduced. Furthermore the positive direction of the current due to the second power conversion circuit which flows into the FETs Q ₂ in the period T _3, the reverse current of the first power conversion circuit, by being superimposed, the current flowing through the FETs Q ₂ is The switching loss is reduced.

[0018] The result is a period of time T ₄ currents from both power conversion circuit is to be canceled each other, shared by the FET
The sum of the currents flowing into Q ₁ and Q ₂ becomes 0, and in effect,
Since the closed loop of the current passing through the shared FET is not formed inside each power conversion circuit, the FET Q ₁ and the FET Q _1
Since no current flows through ₂ , no power loss occurs.

FIGS. 19 (a) to 19 (c) show that the AC power supply Vs
In the above case (when the polarity is opposite to that of FIGS. 18A to 18C)
The state in which the flow flows is shown. FIG. 20 illustrates the above operation.
The waveform of each part is shown, and FIG. ₁
Current I_L1FIG. 2B shows the inductor L_TwoCurrent I_L2
And (c) shows the current I_L2To I_L1Current minus
FIG.₁Current I_Q1(E)
Is FETQ_TwoCurrent I_Q2FIG._Threeof
Current I_Q3(G) shows the FET Q_FourCurrent I_Q4The same
(H) to (k) show the drive signal V_Q1G~ V_{Q4 G}And t
₀~ T₁Period is T₁, T₁~ T_TwoPeriod is T_Two, T_Two
~ T_ThreePeriod is T_Three, T_Three~ T_FourPeriod is T_FourBecomes

As described above, the currents flowing through the FETs Q _{1 to} Q ₄ are set so that the currents flowing through the FETs Q _{1 to} Q ₄ do not overlap with each other with the same polarity.
Since the Q ₁ to Q ₄ is provided with a control circuit 1 for on / off control, it is possible to reduce the current flowing through each FETs Q ₁ to Q _4.

[0021]

[SUMMARY OF THE INVENTION Incidentally in the power supply period of the FETs Q ₁ to Q ₄ of the on / off varies as follows depending on the polarity of the AC power source Vs. That is, F
When the connection point between ETQ ₁ and Q ₂ is a negative electrode, FETs Q ₃ and Q 2
₂ while the FETs Q ₃ and Q ₁ are on,
The periods during which Q _{1 to} Q ₄ are turned off are sequentially set, and FETs Q ₁ ,
If the connection point Q ₂ 'is positive, the period to turn on the _{FETQ 4, Q 1, FETQ 4} , the period in which Q ₂ is turned on, Q ₁ to Q ₄
Are sequentially set, and the operation of setting these periods is repeated.

That is, when the connection point between the FETs Q ₁ and Q ₂ is a negative electrode, the FET Q ₄ does not perform on / off operation. Also FE
When the connection point between TQ ₁ and Q ₂ is positive, FET Q ₃ is turned on / off.
Does not turn off. Here, considering the circuit for driving the FET, in order to drive the respective FETs Q ₁ to Q _4, it is necessary to apply a predetermined drive voltage between the gate and source of the FETs Q ₁ to Q _4.

However, in the conventional circuit, the FET Q
₁ and FET Q ₂ , and FET Q ₃ and FET Q ₄ are connected in series, respectively. An inductor L ₂ and a load L are connected between a connection point between FET Q ₁ and FET Q _{2 and} a connection point between FET Q ₃ and FET Q _4. since bets is connected, the potential of the source, except FETs Q ₂ and FETs Q ₄ are the same,
Each takes a different potential.

The control circuit 1 is usually made by providing a certain reference potential. To drive an FET whose reference potential is at a different potential, the control circuit 1 is electrically insulated, and the signal is gate-sourced. Must be applied in between. Although there are various methods of electrically insulating, a method using a pulse transformer is commonly used.

FIG. 21 shows an example using this method. In this example, as the drive unit 3 provided in the control circuit 1, a current amplifying circuit composed of a totem pole circuit in which complementary transistors Q ₁₁ and Q ₁₂ are connected in series is used. ) (FIG. 2)
2 (b) shows the control signal in an enlarged manner. ) From an oscillation circuit (not shown), the transistors Q ₁₁ and Q ₁₂ are turned on / off, respectively, and the same signal as the control signal is generated between the collector and the emitter of the transistor Q ₁₂ . Due to the collector-emitter voltage V _Q12 , the capacitor C ₀ has a duty ratio of the control signal under the condition A shown in FIG. 22C which is determined by the primary side inductance of the pulse transformer PT, the capacitance value of the capacitor C ₀ , and the resistance component. _Is charged to a value (V _C0 ′) determined by the control signal, and charge and discharge are repeated by the control signal at this voltage. At this time, the exciting current I shown in FIG. 22 (e) flows through the primary winding of the pulse transformer PT.

As a result, the resistance Rb connected to the secondary winding of the pulse transformer PT via the resistance Ra is as shown in FIG.
The voltage V _G generated shown, this voltage is applied across the gate and source of the FETs Q. Also the input of the control signal is lost, the charging voltage of the capacitor C ₀ is discharged via the transistor Q _12, FIG. 2 by that time the discharge current to a voltage V _G
A voltage like B shown in FIG.

[0027] Here, immediately after the application of the control signal, the primary inductance of the pulse transformer PT, the capacitance value and the resistance component of Kodensa C _0, the behavior of the charging of the capacitor C ₀ and the inductance value of the primary inductance L ₀
When the resistance component is R ₀ , it is determined by the following equation. R ₀ ² > 4L ₀ / C ₀ ... Logarithmic (non-oscillating) [FIG.
(C)] R ₀ ² = 4L ₀ / C ₀ critical (boundary between non-oscillatory and vibratory) [FIG. 23 (b) R ₀ ² <4L ₀ / C ₀ .vibratory [FIG. 23 (a) ] oscillatory are like C in FIG. 20 (d), a problem that this case can not be driven without reaching the voltage necessary for driving the voltage V _G is generated.

Then, to make it logarithmic or critical,
It is sufficient to reduce the inductance L ₀ , reduce the capacitance of the capacitor C ₀ , or increase the resistance component R _0. However, it takes time to charge and discharge the capacitor C ₀ with one control signal, and the driving is performed. The rising and falling portions of the signal become dull, and the switching loss increases. Further, if the resistance component R ₀ increases, the resistance component R ₀ is shared voltage by the excitation current I, FIG from the voltage of the half of the voltage Fig after one signal voltage _{V G 25 (a) 25 (} b) As shown in (2), the FET Q cannot be driven reliably, and the switching loss increases.

When the capacitor C ₀ is increased, the charging current of the capacitor C ₀ immediately after the application of the control signal increases,
A problem of saturation of the pulse transformer PT occurs, and the size of the pulse transformer PT is increased in order to prevent the saturation. Also,
Reducing the inductance L ₀ also involves a problem of saturation and an increase in the size of the pulse transformer PT. Pulse transformer P
When T is saturated, as shown in FIG.
With increases rapidly, since the transfer of energy to the secondary side is not performed, since the waveform of the voltage V _G shown in FIG. 24 (b) is not a predetermined waveform is obtained, it can not be reliably driven the FETQ This causes problems such as an increase in switching loss and a change in the amount of power supplied to the load L.

To prevent saturation, a pulse transformer PT
When the size of the first power conversion circuit and the second power conversion circuit are increased, the cost and the overall size increase.
ET is shared, the number of parts is reduced, and each FET Q _1-
The current flowing through the Q ₄ so as not to be superimposed with the same polarity, to reduce the current flowing on / off control to the FETs Q ₁ to Q _4, and enables the switching element miniaturization, whole In this case, the effect of achieving a compact size and reducing costs is offset.

In the method using the pulse transformer PT, various problems occur immediately after the application of the control signal. 22 by the discharge current flowing also through the transistor Q ₁₂ from the capacitor C ₀ In yet immediately after the application end of the control signal
A voltage like B in (d) is generated. This voltage turns on the FET Q that is kept off. FETQ
Is turned on, for example, in the series circuit of the FETs Q ₃ and Q _{4 in} FIG. 12, when one of the FETs is originally turned on and the other is turned off, the stopped FET is turned on.
ETQ ₃ and Q ₄ are simultaneously turned on. Therefore switching losses are increased flows steep high current from the capacitor C _1, there is a problem that a profound stress on FETQ _3, Q _4.

As described above, in the method using the pulse transformer PT, a problem occurs immediately after the application of the control signal or after the application of the control signal is stopped. In the power supply device shown in FIG. 14 is the way, the FETs Q ₂ and Q ₄ as described above have the same potential, and each potential different from other two FETs Q ₁ and Q _3. Therefore, no matter where the reference potential of the control circuit 1 is set, it is necessary to drive at least two or more FETs after electrically insulating them.

[0033] Generally, the reference potential is a low-pressure side of the capacitor C _1, i.e. it is often with respect to the potential of the FETs Q ₂ and Q _4. . At that time, it is necessary to electrically insulate and drive the FETs Q ₂ , Q ₃ , Q ₄ . However, when detecting the state of the load L or the like, the connection point may be set to the connection point between the FETs Q ₁ and Q _{2. In} this case, the FETs Q ₂ , Q ₃ and Q
₄ needs to be electrically insulated.

In any case, since the FETs Q ₁ and Q ₂ are always turned on and off independently of the AC power supply Vs, it is assumed that the FETs Q ₁ and Q ₂ are driven electrically insulated by using the pulse transformer PT. Also, the above-mentioned problem occurs at the initial stage when the power is turned on.
Since ETQ ₁ and Q ₂ can be driven, there is no practical problem.

On the other hand, the FETs Q ₃ and Q ₄ alternately operate and stop alternately according to the polarity of the AC power supply Vs. Therefore, if it is assumed that the FETs Q ₃ and Q ₄ are driven by being electrically insulated by a pulse transformer, the AC power supply Vs In each cycle, the above-mentioned problem occurs, switching loss increases, and a problem arises in that efficiency is deteriorated. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a power supply device capable of stably operating a switching element for on / off control to reduce switching loss and improve efficiency. It is in.

Another object of the present invention is to provide a power supply device capable of reliably driving switching elements at different potentials by using a pulse transformer without increasing the size of the pulse transformer.

[0037]

According to a first aspect of the present invention, there is provided a power supply apparatus having at least one switching element and performing power conversion by switching the switching element, comprising: a pulse transformer; A capacitor connected in series to the primary winding of the pulse transformer; and control means for applying a rectangular wave signal between the capacitor and the primary winding. Turn on / off the switching element
A power supply that includes at least one drive unit that performs off control and sets a period in which the drive unit repeats on / off control of the switching element and a period in which the off state is maintained for a sufficiently longer time than the off period in the period. The apparatus is characterized in that a means is provided for setting the impedance of the control means to a high impedance as viewed from the capacitor during the period in which the off state is maintained.

According to a second aspect of the present invention, in the first aspect of the invention, the high impedance means is constituted by a second switching element. According to a third aspect of the present invention, in the power supply device including at least one switching element and performing power conversion by switching the switching element, a pulse transformer and a capacitor connected in series to a primary winding of the pulse transformer are provided. Control means for applying a rectangular wave signal between the capacitor and the primary winding.
At least one drive unit for controlling on / off of the switching element connected to the next side is provided, and a period during which on / off control of the switching element is repeated by the drive unit is more than an off period in the period. In a power supply device for setting a period in which the off state is maintained for a long time, a second switching which is turned on during the period in which the off state is maintained between the secondary winding of the pulse transformer and the switching element which is controlled to be on / off. An element is provided.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the second switching element comprises a voltage-responsive switching element. According to a fifth aspect of the present invention, in the third or fourth aspect, the pulse transformer is connected in parallel with the second switching element.
A rectifier is connected so that the next winding side is a cathode.

According to a sixth aspect of the present invention, in a power supply device having at least one switching element and performing power conversion by switching of the switching element, a pulse transformer and a primary winding of the pulse transformer are connected in series. And a control unit for applying a rectangular wave signal between the capacitor and the primary winding, and a drive unit for controlling on / off of the switching element connected to the secondary side of the pulse transformer. A power supply device that includes at least one or more and sets a period during which the drive unit repeats on / off control of the switching element and a period during which the off state is maintained for a sufficiently longer time than the off period in the period. , A means for short-circuiting both ends of the primary winding of the pulse transformer is provided.

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the short-circuit means is constituted by a switch means. In the invention according to claim 8, at least 1
In a power supply device comprising at least one switching element and performing power conversion by switching of the switching element,
A pulse transformer, a capacitor connected in series to a primary winding of the pulse transformer, and control means for applying a rectangular wave signal between the capacitor and the primary winding; At least one drive unit for controlling on / off of the switching element connected to the next side is provided, and a period during which on / off control of the switching element is repeated by the drive unit is more than an off period in the period. In a power supply device for setting a period in which the off state is maintained for a long time, the amplitude value of the rectangular wave signal of the control means is modulated so that the amplitude value of an on / off signal for driving the switching element is substantially constant. Means are provided.

According to a ninth aspect of the present invention, in the first or the second aspect of the present invention, a plurality of driving sections are provided corresponding to the plurality of switching elements, and at least two of the driving sections correspond to the corresponding switching elements. It is characterized in that a period during which the on / off control is repeated and a period during which the off-state is maintained operate exclusively in both driving units. Claim 1
In a preferred embodiment of the present invention, the control means of the driving section is constituted by a control signal source and a power amplifier circuit.

According to an eleventh aspect, in the tenth aspect, the current amplifying circuit comprises an NPN transistor and a P-type transistor.
Series circuit with NP transistor or N channel F
It is characterized by comprising a series circuit of an ET and a P-channel FET. According to a twelfth aspect of the present invention, in any of the first to eleventh aspects, the potentials of the switching elements connected to the primary side and the secondary side of the pulse transformer of the driving section are at different potentials.

According to a thirteenth aspect of the present invention, in any one of the first to twelfth aspects of the present invention, at least one set of a switching circuit in which a DC power supply and two switching elements that cannot block a reverse current are connected in series, A control circuit that repeatedly outputs a signal for turning on / off one switching element and outputs a signal for turning off the other switching element during the output period; and a series circuit that directly connects an inductor and a load. on/
While one of the switching elements driven by the off signal is on, power is supplied to the load by a closed circuit of a DC power supply, one of the switching elements, and a series circuit of an inductor and the load, and one of the switching elements is off. The drive unit is provided in the control circuit of the power supply device in which the current flows in a closed circuit of the series circuit of the other switching element and the inductor and the load that is turned off by the signal that is turned off during the off period. It is characterized by.

According to a fourteenth aspect of the present invention, in the thirteenth aspect, a plurality of power conversion circuits are formed by using a plurality of sets of switching circuits, and at least one of the switching elements constituting the power conversion circuits is provided. The switching element is shared by each power conversion circuit. According to a fifteenth aspect, in the fourteenth aspect, on / off of the switching elements in each switching circuit is controlled such that all currents flowing from the respective power conversion circuits to the switching elements shared by the power conversion circuits do not overlap with the same polarity. It is characterized by doing.

In the sixteenth aspect, the first to twelfth aspects are described.
In the invention of the first aspect, the first, second
A first switching circuit composed of a series circuit of
A second switching circuit composed of a series circuit of the switching elements is connected in parallel to a smoothing capacitor, and a connection point of the first and second switching elements is connected to the third and third switching elements.
A series circuit of an inductor and a load is connected between the connection point of the fourth switching element, and a series circuit in which the first and second rectifying elements are connected in the same direction is anti-parallel to the first switching circuit. The driving unit is connected to a control circuit of each switching element of a power supply device in which an AC power supply is connected between a connection point of the first and second switching elements and a connection point of the first and second rectification elements. It is characterized by having been provided. Claim 17
In the invention according to claim 16, in the invention according to claim 16, when the connection point side of the first and second switching elements to which the AC power supply is connected is a positive electrode, a period during which the second and third switching elements are simultaneously turned on, , The period in which the third switching element is simultaneously turned on, and the period in which all the switching elements are turned off are sequentially repeated, and the first and second periods to which the AC power supply is connected are repeated.
When the connection point side of the switching element is negative, the period in which the first and fourth switching elements are simultaneously turned on,
Each drive unit is configured so that a period in which the fourth switching element is turned on simultaneously and a period in which all switching elements are turned off are sequentially repeated.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. (Embodiment 1) FIG. 2 shows a main circuit configuration of a power supply device of the present embodiment. The circuit of the illustrated device has basically the same configuration as the conventional device of FIG. Since the configuration is the same as that of the conventional example, the same components as those of the circuit configuration shown in FIG.

However, in this embodiment, the control circuit 1
FET Q driven by receiving drive signal₁~ Q_FourOf the system
The reference potential of the control circuit 1 is applied to the circuit shown in FIG.
For example, FETQ₁, Q_TwoIf you set the connection point
FET Q at a potential different from the reference potential_Two, Q_Three, Q_FourTo
Needs a drive for that, but as mentioned above
In the circuit of FIG. 1 (FIG. 14), the FET Q_TwoIs the AC power supply Vs
There is no major problem because it always operates regardless of polarity.
And FETQ_TwoIn the conventional driving unit 3 shown in FIG.
Since there is no problem, the driving unit 3 in FIG._TwoFor
No, the remaining FET Q _Three, Q_FourPair with each other to drive
In response, a driving unit 4 shown in FIG.
You.

That is, in the driving section 4, the complementary FET Q
₁₁ ', Q _12' connects the current amplifier configuring the totem pole circuit connected in series, the series circuit of the transistor Q ₁₃ to the control circuit power supply _{Vcc, FETQ 11 ', Q 12} ' commonly connected gates of to enter the square-wave control signal from the oscillation circuit (not shown), the base of the transistor Q ₁₃ is adapted to enter a polarity synchronizing signal synchronized with the polarity of the AC power source Vs. The polarity synchronization signal is generated by a synchronization signal generation circuit (not shown) provided in the control circuit 1.

And FETQ₁₂’And transistor Q₁₃of
The primary winding of the pulse transformer PT is condensed in the series circuit.
Sa C₀Are connected in parallel through the secondary of the pulse transformer PT
A series circuit of a resistor Ra and a resistor Rb is connected to the winding.
Rb has FETQ_Three(Or Q _FourConnect the gate and source of
Has continued. Thus, in the present embodiment, the FET Q_Three(or
Is Q_Four) Is the switching operation shown in FIG.
Polarity synchronization synchronized with the polarity of the power supply Vs (positive half wave in the figure)
Transistor Q with signal₁₃Is driven as shown in FIG.
Is done. And transistor Q₁₃In the ON period of
The control signal is FETQ₁₁’, Q₁₂’Gate
Resistance Rb via the pulse transformer PT and the resistance Ra
The drive signal V shown in FIG._Q3G(Or V
_Q4G) Occurs, and this drive signal V_Q3G(Or V _Q4G)
More FETQ_Three(Or Q_Four) Is switching (ON / OFF)
F) works. This FET Q_Three(Or Q_Four) Operation pause
Sometimes transistor Q₁₃Is in the off state,
Sa C₀Charge of FET Q₁₂’Discharge path
Disappears and the capacitor C₀Potential V_C0Is a figure
It is kept constant as shown in FIG.

Therefore, when the operation is started next time, there is no charging process of the capacitor C ₀ , so that the problem immediately after the operation as in the conventional example described above does not occur, and the FET Q ₃ (or Q ₄ ) is controlled stably. be able to. Since the operation of the other circuits is the same as that of the conventional example, the description of the operation is omitted.

In this embodiment, the connection point between the FETs Q ₁ and Q _{2 is set} as the reference potential of the control circuit 1.
When the source lines of the FETs Q ₂ and Q ₄ are set to the reference potential, the driving section 4 in FIG. 1 may be provided for the FET Q ₃ . (Second Embodiment) In the first embodiment, the current amplifying circuit of the FETs Q ₁₁ 'Q ₁₂ ' is connected to the control circuit power supply Vcc via the transistor Q ₁₃ on the input side of the driving section 4. In the embodiment, as shown in FIG.
On the input side of the control circuit, a current amplifying circuit composed of a totem pole circuit of complementary transistors Q ₁₁ and Q ₁₂ is connected to the control circuit power supply V
connected to cc, the capacitor C in parallel to the transistor Q _12
0, which pulse the primary winding of the transformer PT, and connecting a series circuit of switching elements Q ₁₄ consisting of the triac, and trigger a switching element Q ₁₄ in the same polar synchronizing signal and the transistor Q ₁₃ of the first embodiment It is.

Since the overall configuration is the same as that of FIG.
The illustration and description thereof are omitted. The base of the control circuit 1
Sub-potential is set to FET Q₁, Q_TwoFET at the connection point of
Q_Three, Q _FourIt is assumed that each of the driving units 4 is provided.
Thus, the operation and effect in the present embodiment are the same as those in the first embodiment.
Is the same as (Embodiment 3) In the present embodiment, the configuration of the driving section 4 is shown in FIG.
As shown in the figure, a resistor R is connected to the secondary winding of the pulse transformer PT.
a, voltage response element Q_Fifteen, A series circuit of resistors Rb
In addition, the resistance Ra and the voltage response element Q_FifteenIn the series circuit of
Iod D₁₁Are connected in parallel, and complementary on the input side.
Transistor Q₁₁, Q₁₂From the totem pole circuit
Connected to the control circuit power supply Vcc
Jista Q₁₂In parallel with the primary winding of the pulse transformer PT
Capacitor C₀Are connected in series. That is, FIG.
1 and the conventional driving unit 3 on the secondary side of the pulse transformer PT.
The configuration is different.

Since the overall configuration is the same as that of FIG.
The illustration and description thereof are omitted. In this embodiment,
The reference potential of the control circuit 1 is set to FET Q₁, Q_TwoAt the connection point of
, FETQ_Three, Q_FourDrive units 4 are provided for
And Thus, the drive unit 4 operates according to the control signal.
Voltage V on the secondary side of the pulse transformer PT_PT2Figure 6
The voltage V is generated as shown in FIG._PT2Is the voltage response
element_FifteenExceeds the breakover voltage of
_FifteenTurns on, and the FET Q is connected across the resistor Rb._Three(Or
Q_Four) Drive signal V_Q3G(Or V_Q4G) Occurs and FE
TQ _Three(Or Q_Four) Is driven. And the drive signal V
_Q3G(Or V_Q4G) Becomes "L" level, the FET Q
_Three(Or Q_Four) Is the input capacitance of the diode D₁₁Through
And discharge, FETQ_Three(Or Q_Four) Is off. this
Time voltage response element Q_FifteenIs the current to maintain on (hold
Turns off because there is no current).

The above operation is repeated while the control signal is repeatedly input, and the drive signal V _Q3G (or V ₄ ) is applied to the gate of the FET Q ₃ (or Q ₄ ) as shown in FIG.
_Q4G ) will be applied. When the input of the control signal stops and the idle period of the FET Q ₃ (or Q ₄ ) is reached, the charge of the capacitor C ₀ is discharged through the primary winding of the pulse transformer PT and the transistor Q _12, and the discharge current at this time voltage is generated as shown in the conventional example by, but by setting the breakover voltage of the voltage responsive element Q ₁₅ to a voltage higher than the voltage responsive element Q ₁₅ not turned on, thus driving signal V _Q3G (or V _Q4G ) does not occur at both ends of the resistor Rb, and the _FET Q ₃ (or Q ₄ ) does not turn on. As a result, switching loss can be reduced, and efficiency is improved.

Here, the voltage response element Q_FifteenBreakover
The voltage range is FET Q_Three(Or Q _Four)
Voltage (driving signal V_Q3G(Or V_Q4G) of
Voltage) and below, capacitor C₀Discharge current due to
From the voltage generated on the secondary side of the pulse transformer PT
I do. X in FIG. 6A is a voltage responsive element Q._FifteenResponse range
Show.

[0057] as a voltage response element Q ₁₅ is SSS, SB
S, DIAC or the like may be used. (Embodiment 4) In this embodiment, the circuit shown in FIG. The circuit of Figure 7 are different in connecting a transistor Q ₁₆ which is turned on / off by polarity synchronizing signal to a conventional drive unit 3 in parallel with the primary winding of the pulse transformer PT of FIG.

Since the overall configuration is the same as that of FIG.
The illustration and description thereof are omitted. In this embodiment,
The reference potential of the control circuit 1 is set to FET Q₁, Q_TwoAt the connection point of
, FETQ_Three, Q_FourDrive units 4 are provided for
And Where transistor Q₁₃Driving polarity synchronization
The signal is FETQ_Three(Or FETQ _Four) Operation period
"L" when the polarity of the AC power supply Vs_Three(or
Is FETQ_Four) Poles of the AC power supply Vs corresponding to the idle periods
It is "H" at the time of sex.

[0059] Thus the transistor Q ₁₆ is short-circuited primary winding of on-driven pulse transformer PT by polarity synchronizing signal when the control signal is not input, pulse transformer P
The primary voltage of T is set to zero. Therefore, when a transition is made from the operation period of the FET Q ₃ (or Q ₄ ) to the idle period, the voltage generated on the secondary side of the pulse transformer PT due to the discharge current from the capacitor C ₀ can be suppressed, and unnecessary during the idle period can be suppressed. There is no ON operation, so that the switching loss of the switching element can be reduced, and the efficiency is improved.

(Embodiment 5) In the present embodiment, the circuit shown in FIG. The circuit shown in FIG. 8 is different from the conventional driving section 3 shown in FIG. 21 in that transistors Q ₁₁ and Q ₁₂ which constitute a current amplification circuit provided on the input side.
And a control circuit power supply Vcc.

Since the overall structure is the same as that of FIG.
The illustration and description thereof are omitted. In this embodiment,
The reference potential of the control circuit 1 is set to FET Q₁, Q_TwoAt the connection point of
, FETQ_Three, Q_FourDrive units 4 are provided for
And Thus, FETQ_Three(Or Q_Four) During the operation period
The corresponding polarity of the AC power supply Vs shown in FIG.
(Q_FourInput voltage of the current amplification circuit when the polarity is negative)
Pressure V ₁As shown in FIG. 9 (f) or (g).
Slow up by road 2.

That is, the polarity of the AC power supply Vs changes and F
When ETQ ₃ (or Q ₄ ) starts operating, the capacitor C
₀ charge is zero, one the input voltage V ₁ of the current amplifier circuit is applied to the primary side of the pulse transformer PT, to the secondary side as compared to the voltage when the charge stored in the capacitor C ₀ , The voltage generated at the resistor Rb increases. Then, the voltage generated by the resistor Rb can be slowed up by the voltage adjusting circuit 2 so as to be substantially constant.
ETQ ₃ (or Q ₄ ) can operate stably.

FIGS. _9H and _9I show the drive signals V _Q3G and V _Q4G of the _FETs Q ₃ and Q ₄ . Here, FIGS. 9 (b) and 9 (c)
_3D show drive signals V _Q3G and V _Q4G of the _FETs Q ₃ and Q ₄ when the conventional drive unit 3 is used, and FIGS.
The excitation currents I ₁₃ and I ₁₄ flowing through the primary winding of the pulse transformer PT during the operation of TQ ₃ and Q ₄ are shown. By thus suppressing the input voltage V ₁ of the current amplifying circuit as compared with the conventional example in this embodiment, the charging current to the capacitor C _0,
That is, the exciting current (FIG. 9 (j)) flowing through the primary winding of the pulse transformer PT is smaller than in the conventional example.

Therefore, in the case of the present embodiment, the switching loss can be reduced while the size of the pulse transformer PT is reduced, and the efficiency is improved. (Embodiment 6) In Embodiment 1 described above, the driving unit 4 is
Although the drive unit 4 is provided independently of TQ ₃ and Q ₄ , in the present embodiment, both of the FETs Q ₃ and Q ₄ are supported by sharing the capacitor C ₀ as shown in FIG. Drive units 4 ₁ and 4 ₂ thus configured.

[0065] That drive unit 4 ₁ for FETs Q _3, the control circuit power supply Vcc to the complementary FETQ ₁₁ ', Q _12' connecting the series circuit of the current amplifier circuit and a transistor Q ₁₃ consisting configured totem pole circuit and connects the capacitor C ₀ through the primary winding of the pulse transformer PT ₁ is in series circuit with the FETs Q ₁₂ 'and transistor Q _13, the secondary winding of the pulse transformer PT ₁ resistor and the resistor Ra ₁ a series circuit of Rb ₁ is connected in parallel to form by connecting between the gate and source of the FETs Q ₃ to the resistance Rb _1. FET Q ₄
Driver of use 4 _2, FET complementary to the control circuit power supply Vcc
A series circuit of the current amplifier and the transistor Q ₂₃ consisting configured totem pole circuit Q _21, Q _22,
FETs Q ₂₂ and the transistor Q and a capacitor C ₀ through the primary winding of the pulse transformer PT ₂ to the series circuit of the _23, the pulse transformer PT is the _second secondary winding resistance Ra ₂
And a series circuit of a resistor Rb ₂ connected in parallel, the resistor Rb ₂ are constituted by connecting between the gate and source of the FETs Q _4.

The driving units 4 ₁ and 4 ₂ corresponding to the FETs Q ₃ and Q ₄ respectively include an AC power supply Vs shown in FIG.
The control signal and the polarity synchronizing signal are supplied so that the FETs Q ₃ and Q ₄ alternately operate and pause alternately in accordance with the polarity of, and do not operate simultaneously. Since the overall configuration is the same as that of FIG. 2, illustration and description thereof are omitted here. In the present embodiment, the reference potential of the control circuit 1 is set at the connection point between the FETs Q ₁ and Q ₂ , and the driving units 4 ₁ and 4 are connected to the FETs Q ₃ and Q ₄ .
_It is assumed that ₂ is provided respectively.

[0067] In Thus, the AC power source FETQ ₄ is dormant, for example the period of positive half wave of Vs, FETQ ₃ will be to operate, the control signal of the driving unit 4 ₁ to the period FETQ
₁₁ ′ and Q ₁₂ ′, and an “H” polarity synchronization signal is applied to the base of the transistor Q ₁₃ ,
Transistor Q ₁₃ is turned on as shown in FIG. 11 (d), the drive signal V _Q3g shown in FIG. 11 (b) occurs in the secondary across the output by resistance Rb ₁ of the pulse transformer PT _1, the drive signal V FETs Q ₃ performs a switching operation by _Q3g.

On the other hand, for example, a period of a negative half-wave of the AC power supply Vs
Then FET Q_ThreePauses, FET Q _FourWorks
During this period, the control signal is applied to the drive unit 4_TwoFET Q_{twenty one},
Q_{twenty two}"H" polarity synchronization
Signal is transistor Q_{twenty three}Given to the base of the transi
Star Q_{twenty three}Turns on as shown in FIG.
SPT_TwoResistance Rb by the secondary output of_TwoFig. 11
The drive signal V shown in (c)_Q4GOccurs and the drive signal V_Q4G
FETQ_FourPerforms a switching operation.

Even if the FETs Q ₃ and Q ₄ repeat the operation and the rest, the capacitor C ₀ always keeps the pulse transformer PT
₁ or has the exciting current by the charge and discharge are repeated for PT _2, therefore the capacitor C ₀ is kept substantially constant voltage as shown in FIG. 11 (f). Therefore, the FETs Q ₃ and Q ₄
Of the AC power supply Vs for every half cycle, the shortage of the drive voltage immediately after the suspension, the saturation of the pulse transformers PT ₁ and PT ₂ , and the ON operation at the suspension, do not occur, and the FET Q _{3 is} stable. , will be able to drive the Q _4, without an increase in size of the pulse transformer, and enables the reduction of the switching loss, efficiency is improved.

(Seventh Embodiment) In the sixth embodiment, the FET
The capacitors C ₀ in the driving units 4 ₁ , 4 ₂ of Q ₃ , Q ₄
However, in the present embodiment, as shown in FIG. 12, the current amplifying circuit is also shared. In other words, the complementary transistors Q ₁₁ ,... _On the input sides of the driving units 4 ₁ , 4 ₂ corresponding to the FETs Q ₁ , Q ₂ , respectively.
Connected to the control circuit power supply Vcc as a circuit for sharing the current amplifier circuit comprising a totem pole circuit of Q _12, the driving unit 4
_1, the transistor Q ₁₂ capacitor C ₀ in parallel to the pulse transformer PT ₁ of the primary winding is connected a series circuit of switching elements Q ₁₄₁ consisting of the triac, the capacitor C ₀ in parallel to the driving section 4 _2, transistors Q ₁₂ , the primary winding of the pulse transformer PT _2, is connected a series circuit of switching elements Q ₁₄₂ consisting of the triac.

The driving units 4 ₁ and 4 ₂ corresponding to the FETs Q ₃ and Q ₄ respectively have an AC power supply Vs shown in FIG.
Operation FETs Q _3, Q ₄ are alternately according to polarity, repeatedly pauses, the polarity synchronizing signal so as not to operate is applied to the switching element Q _141, Q ₁₄₂ simultaneously and to the base of the transistor Q _11, Q ₁₂ is As shown in FIG. 13 (b), a control signal is continuously supplied and the current amplifier circuit always operates.

Since the overall configuration is the same as that of FIG. 2, illustration and description thereof are omitted here. In this embodiment, it is assumed that the reference potential of the control circuit 1 is set at the connection point between the FETs Q ₁ and Q ₂ , and the driving units 4 ₁ and 4 ₂ are provided for the FETs Q ₃ and Q ₄ , respectively. And Thus, the AC power supply, for example the period of positive half wave of Vs to pause FETs Q _4, will be FETs Q ₃ is operated, the switch element polarity synchronizing signal is applied to the gate of the switching element ₁₄₁ is in the period ₁₄₁ is FIG. 13
Turned as (c), the pulse is across the resistor Rb ₁ by the secondary output of the transformer PT ₁ drive signal V _Q3g as shown in FIG. 13 (e) occurs, F by the drive signal V _Q3g
ETQ ₃ performs a switching operation.

On the other hand, for example, a period of a negative half-wave of the AC power supply Vs
Then FET Q_ThreePauses, FET Q _FourWorks
During this period, the polarity synchronization signal of “H” is output from the switch element.
Q_{14 Two}Switch element Q₁₄₂Figure 1
As shown in FIG. 3 (d), the pulse transformer PT_TwoSecondary
Depending on output, resistance Rb_TwoAs shown in FIG.
The drive signal V_Q4GOccurs and the drive signal V_Q4GBy F
ETQ_FourPerforms a switching operation.

Even if the FETs Q ₃ and Q ₄ repeat the operation and the rest, the capacitor C ₀ always keeps the pulse transformer PT.
Charging and discharging by the excitation current of ₁ or PT ₂ are repeated, and therefore, the capacitor C ₀ maintains a substantially constant voltage as shown in FIG. Therefore, the FETs Q ₃ and Q ₄
Of the AC power supply Vs for every half cycle, the shortage of the drive voltage immediately after the suspension, the saturation of the pulse transformers PT ₁ and PT ₂ , and the ON operation at the suspension, do not occur, and the FET Q _{3 is} stable. , will be able to drive the Q _4, without an increase in size of the pulse transformer, and allows a reduction of the switching loss, efficiency is improved.

[0075]

According to the first and second aspects of the present invention, when the operation is started, the charging of the primary side capacitor of the pulse transformer can be suppressed. As a result, it is possible to stably control the switching element even immediately after the operation, reduce the switching loss, and improve the efficiency.

The third, fourth, and fifth aspects of the present invention
With the configuration described above, the voltage generated on the secondary side of the pulse transformer by the second switching element prevents the switching element to be turned on / off controlled from being driven during the period in which the off state is maintained. Therefore, the switching element can be stably controlled, so that the switching loss can be reduced and the efficiency can be improved.

According to the sixth and seventh aspects of the present invention, since the voltage on the primary side of the pulse transformer can be set to 0, no voltage is generated on the secondary side and the pulse transformer is turned off. It is possible to prevent the switching element to be controlled on / off from being driven during the period in which the switching element is maintained, to control the switching element stably, to reduce the switching loss, and to improve the efficiency. effective.

According to the eighth aspect of the present invention, the switching element to be controlled on / off can be operated stably, and the charging current to the capacitor can be reduced to saturate the pulse transformer. Can be avoided, and the size of the pulse transformer can be reduced, the switching loss can be reduced, and the efficiency can be improved.

According to the ninth aspect of the present invention, since the first and second aspects of the present invention are configured as described above, there is an effect that the components can be shared in a plurality of driving units, and the size can be reduced. According to the tenth and eleventh aspects of the present invention, as described above, the configuration of the control means of the drive unit can be configured with a simple circuit.

According to the twelfth to seventeenth aspects of the invention, the floating switching element can be reliably driven, and the size of the pulse transformer can be reduced, the switching loss can be reduced, and the efficiency can be improved. There is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a driving unit according to a second embodiment of the present invention.

FIG. 2 is an overall circuit diagram of the same.

FIG. 3 is a waveform diagram for explaining the operation of the above.

FIG. 4 is a circuit diagram of a driving unit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a driving unit according to a third embodiment of the present invention.

FIG. 6 is a waveform diagram for explaining the operation of the above.

FIG. 7 is a circuit diagram of a driving unit according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram of a driving unit according to a fifth embodiment of the present invention.

FIG. 9 is a waveform chart for explaining the operation of the above.

FIG. 10 is a circuit diagram of a driving unit according to a sixth embodiment of the present invention.

FIG. 11 is a waveform chart for explaining the operation of the above.

FIG. 12 is a circuit diagram of a driving unit according to a seventh embodiment of the present invention.

FIG. 13 is a waveform diagram for explaining the operation of the above.

FIG. 14 is an overall circuit diagram of a conventional discharge lamp lighting device.

FIG. 15 is an explanatory diagram of the operation of the above.

FIG. 16 is an operation explanatory view of the above.

FIG. 17 is a waveform chart for explaining the operation of the above.

FIG. 18 is an operation explanatory view of the above.

FIG. 19 is a diagram illustrating the operation of the above.

FIG. 20 is a waveform chart for explaining the operation of the above.

FIG. 21 is a circuit diagram of a driving section of a conventional example.

FIG. 22 is a waveform diagram for explaining the operation of the above.

FIG. 23 is a waveform chart for explaining the above operation.

FIG. 24 is a waveform diagram for explaining the operation of the above.

FIG. 25 is a waveform diagram for explaining the operation of the above.

[Explanation of symbols]

Vcc control circuit power _{Q 11 ', Q 12' FET} Q 3, Q 4 FET Q 13 transistor C ₀ capacitor PT pulse transformer 4 driver

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 17/687 D

Claims (17)

[Claims] 1. A power supply device comprising at least one switching element and performing power conversion by switching the switching element, comprising: a pulse transformer; a capacitor connected in series to a primary winding of the pulse transformer;
Control means for applying a rectangular wave signal between the capacitor and the primary winding; and at least one drive unit for controlling on / off of the switching element connected to the secondary side of the pulse transformer. A period during which on / off control of the switching element is repeated by the driving unit;
In a power supply device for setting a period in which the off state is maintained for a time sufficiently longer than the off period in the period, a means for setting the impedance of the control means to a high impedance as viewed from the capacitor is provided in the off period. A power supply device characterized by the above-mentioned. 2. The high-impedance means is a second means.
2. The power supply device according to claim 1, wherein the power supply device comprises: 3. A power supply device having at least one switching element and performing power conversion by switching the switching element, comprising: a pulse transformer; a capacitor connected in series to a primary winding of the pulse transformer;
Control means for applying a rectangular wave signal between the capacitor and the primary winding; and at least one drive unit for controlling on / off of the switching element connected to the secondary side of the pulse transformer. A period during which on / off control of the switching element is repeated by the driving unit;
In a power supply device for setting a period in which the off state is maintained for a time sufficiently longer than the off period in the period, the off state is maintained between the secondary winding of the pulse transformer and the switching element that is controlled to be on / off. A power supply device comprising a second switching element that is turned on during a predetermined period. 4. The power supply device according to claim 3, wherein said second switching element comprises a voltage-responsive switching element. 5. The power supply device according to claim 3, wherein a rectifying element is connected in parallel with said second switching element such that a secondary winding side of said pulse transformer serves as a cathode. 6. A power supply device having at least one switching element and performing power conversion by switching the switching element, comprising: a pulse transformer; a capacitor connected in series to a primary winding of the pulse transformer;
Control means for applying a rectangular wave signal between the capacitor and the primary winding; and at least one drive unit for controlling on / off of the switching element connected to the secondary side of the pulse transformer. A period during which on / off control of the switching element is repeated by the driving unit;
In a power supply apparatus for setting a period in which the off period is maintained for a sufficiently longer time than the off period in the period, means for short-circuiting both ends of the primary winding of the pulse transformer during the off period is provided. And power supply. 7. The power supply device according to claim 6, wherein said short-circuit means is constituted by a switch means. 8. A power supply device comprising at least one switching element and performing power conversion by switching the switching element, comprising: a pulse transformer; a capacitor connected in series to a primary winding of the pulse transformer;
Control means for applying a rectangular wave signal between the capacitor and the primary winding; and at least one drive unit for controlling on / off of the switching element connected to the secondary side of the pulse transformer. A period during which on / off control of the switching element is repeated by the driving unit;
In a power supply apparatus for setting a period in which the off state is maintained for a time sufficiently longer than the off period in the period, the rectangular shape of the control means is adjusted so that the amplitude value of an on / off signal for driving the switching element is substantially constant. A power supply device comprising means for modulating the amplitude value of a wave signal. 9. A period in which a plurality of driving units are provided corresponding to the plurality of switching elements, and at least two of the driving units repeat on / off control of the corresponding switching element and a period in which the switching unit is kept off. 3. The power supply device according to claim 1, wherein the power supply units operate exclusively in both drive units. 4. 10. The power supply device according to claim 1, wherein the control means of the drive unit comprises a control signal source and a power amplifier circuit. 11. The power supply device according to claim 10, wherein said current amplifying circuit comprises a series circuit of an NPN transistor and a PNP transistor or a series circuit of an N-channel FET and a P-channel FET. 12. A primary part of a pulse transformer of a driving unit, and
12. The power supply device according to claim 1, wherein the potentials of the switch elements connected to the next side are at different potentials. 13. At least one unit comprising a DC power supply and two switching elements which cannot block a reverse current connected in series.
A set of switching circuits, a control circuit for repeatedly outputting a signal for turning on / off one switching element of the switching circuit and outputting a signal for turning off the other switching element during the output period, and an inductor and a load. A direct-current power supply, one switching element, and a direct-connected series circuit, wherein one of the switching elements driven by the on / off signal is on.
Power is supplied to the load by the closed circuit of the series circuit of the inductor and the load, and while one of the switching elements is off, the other switching element and the series circuit of the inductor and the load that are turned off by the signal that turns off are closed. 13. The power supply device according to claim 1, wherein the drive unit is provided in the control circuit of the power supply device in which a current flows in a circuit. 14. A power conversion circuit comprising a plurality of sets of switching circuits, and at least one of the switching elements constituting the power conversion circuit is shared by each power conversion circuit. The power supply device according to claim 13, wherein 15. The on / off state of the switching element in each switching circuit so that all currents flowing from the power conversion circuits to the switching element shared by the power conversion circuits do not overlap with the same polarity.
The power supply according to claim 14, wherein the power supply is controlled to be off. 16. A first switching circuit comprising a series circuit of first and second switching elements which cannot block a reverse current, and a series circuit of third and fourth switching elements which cannot block a reverse current. And a second switching circuit configured in parallel with a smoothing capacitor,
A connection point between the first and second switching elements;
A series circuit of an inductor and a load is connected between the connection points of the switching elements, and a series circuit in which first and second rectifying elements are connected in the same direction is connected in anti-parallel to the first switching circuit. The drive section is provided in a control circuit of each switching element of a power supply device in which an AC power supply is connected between a connection point of the first and second switching elements and a connection point of the first and second rectification elements. The power supply device according to claim 1, wherein: 17. When the connection point of the first and second switching elements to which the AC power supply is connected is positive, a period during which the second and third switching elements are simultaneously turned on, and the first and third switching elements. Are simultaneously turned on and a period in which all the switching elements are turned off is sequentially repeated. When the connection point side of the first and second switching elements to which the AC power supply is connected is a negative electrode, the first and fourth switching are performed. Each drive unit is configured such that a period in which the elements are simultaneously turned on, a period in which the second and fourth switching elements are simultaneously turned on, and a period in which all the switching elements are turned off are sequentially repeated. 17. The power supply device according to claim 16, wherein: