JPH1169622A - Power supply circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption, by shortening the particular time required for transferring a power supply voltage to a load with a transmitting means during the period from the time immediately before the time to operate a load to the time immediately before the time to converge the power supply voltage, and thereby transferring the power supply voltage to the load within a short period of time. SOLUTION: A control circuit 2' outputs a regular control signal to a regulator 3 in the timing immediately before the start of time slot and the regulator 3 supplies the power supply voltage supplied from the power supply 1 to the loads 5a, 5b to immediately start the loads 5a, 5b. The control circuit 2' outputs a high speed rising signal to the gate terminal of FET6 during the period from the time immediately before the time to drive the loads 5a, 5b to the time immediately before the time to stabilize the power supply voltage of a load 5c. As a result, the collector terminal and base terminal of an NPN transistor 4 are terminated, charges are quickly transferred to an electrolyte capacitor C4 to increase the base current within a short period, and it is then transferred to the load 5c via the emitter terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called TDMA, which is a time division multiplex communication mainly employed in a PHS or the like.
(Time division multiple access) This relates to a power supply circuit for supplying power to a circuit that requires a relatively long time from the start of power supply to a stable operation in a communication device or the like. The present invention relates to a power supply circuit capable of reliably operating a circuit.

[0002]

2. Description of the Related Art A power supply circuit can be applied to a power supply circuit of any device as long as it takes a relatively long time until the operation becomes stable after the power supply is started. For the sake of explanation, a description will be given in consideration of a case where the present invention is applied to a TDMA communication apparatus.

[0003] In TDMA communication, a fixed time period (frame) is divided into a number of time intervals (time slots).
This is a method in which a plurality of terminals apparently communicate at the same time by using individual time slots as communication channels.

[0004] In recent years, some mobile phone systems which have been rapidly developing have adopted the TDMA communication system. In addition, in order to reduce the size and weight of the mobile phone itself, the battery capacity is reduced. On the other hand, there is a strong demand for a longer standby time and a longer talk time, while providing a power supply circuit for supplying power to each circuit of the mobile phone only for each time slot used for communication. Some have reduced the consumption of

[0005] On the other hand, some circuits of mobile phones require a long time from the start of power supply until the operation is stabilized. A conventional power supply circuit will be described with reference to FIGS. FIG. 3 is a circuit diagram of a conventional power supply circuit, and FIG.
FIG. 2 is a timing chart illustrating an operation of a conventional power supply circuit.

[0006] As shown in FIG. 3, the conventional power supply circuit mainly includes a power supply 1, a control circuit 2, a regulator 3, an NPN transistor 4, and a plurality of loads 5.

In FIG. 3, the loads 5a and 5b are loads that are relatively insensitive to fluctuations in power supply voltage, and the load 5c is susceptible to fluctuations in power supply voltage.
It is assumed that the circuit is a circuit such as a voltage controlled oscillator (VCO).

Hereinafter, each part will be described in detail. Power supply 1
The cathode is grounded, and the anode is connected to one of the terminals of the regulator 3 (referred to as “power input terminal”) and grounded via an electrolytic capacitor C1.

The control circuit 2 outputs a regulator control signal to the regulator 3 before the start of the time slot used by the load 5 for communication, and at the end of the time slot, the regulator control signal ( Reg-Cont) is not output to the regulator 3.

[0010] Specifically, the timing of the start of the output of the regulator control signal is a certain time (t) before the start of the time slot, and the certain time (t) is the starting time. Is the time required for the power supply voltage of the slowest circuit to stabilize.

While the regulator 3 receives the input of the regulator control signal, the regulator 3 supplies the power supplied from the power supply input terminal to a terminal connected to the load 5 (hereinafter, referred to as a terminal).
(Referred to as a “power supply output terminal”).

The other two terminals of the regulator 3 are configured such that one is grounded via the capacitor C2 and the other is directly grounded.

The power output terminal of the regulator 3 is grounded via an electrolytic capacitor C3.
It is directly connected to the loads 5a and 5b to supply power. Further, the power output terminal is connected to the collector terminal (C) of the NPN transistor 4 and the base terminal (B) of the NPN transistor 4 via the resistor R3.

The NPN transistor 4 outputs power supplied from the collector terminal (C) via the emitter terminal (E) while constant power is supplied to the base terminal (B). The collector terminal (C) of the NPN transistor 4 is directly connected to the power output terminal of the regulator 3, and the base terminal (B) is connected to the power output terminal of the regulator 3 via the resistor R3. The base terminal (B) is connected to the electrolytic capacitor C
4 is grounded.

Furthermore, a load 5c is connected to the emitter terminal (E) of the NPN transistor 4.

The power of the regulator 3 is directly input to the loads 5a and 5b, whereas the power of the regulator 3 is connected to the load 5c via the NPN transistor 4. This is because, in FIG. 3, since the load 5c is susceptible to the fluctuation of the power supply voltage, the influence of the power supply ripple and noise is cut off.

Since the potential of the power supply is expected to decrease by about 1 V by inserting the NPN transistor 4, the power supply of the regulator 3 is connected to the loads 5a and 5b without passing through the NPN transistor 4. It can be entered directly.

In the NPN transistor 4, when power is supplied from the power output terminal of the regulator 3 to the collector terminal (C), charges are stored in the electrolytic capacitor C4 via the resistor R3, and the potential of the electrolytic capacitor C4 is reduced. Rises, but the electrolytic capacitor C4
Since the base current flows in accordance with the rise in the potential of the emitter, the emitter voltage serving as the power supply voltage of the load 5c rises with a time constant mainly determined by using the resistor R3 and the electrolytic capacitor C4 as parameters. Becomes

Next, the operation of the conventional power supply circuit will be described with reference to FIG. In FIG. 4, FIG.
4B shows a regulator control signal output from the control circuit 2, FIG. 4B shows a change in the power supply voltage of the load 5c whose activation is relatively slow, and FIG. 4C shows an operable time of the load 5c. 4 (d) shows the timing of the time slot used by the load 5.

The time before the control circuit 2 activates the load 5c via the NPN transistor 4 before the arrival timing of the time slot shown in FIG. A regulator control signal is output to the regulator 3 as shown in FIG.

Then, the regulator 3 outputs the power input from the power source 1 to the power input terminal from the power output terminal,
The signal is output to the load 5c via the NPN transistor 4 and directly to the load 5a and the load 5b.

Then, power is supplied to the loads 5a and 5b earlier than the arrival of the time slot to be used, and the load 5a and the load 5b are activated. The load 5c is delayed by a time mainly determined by the time constant of the resistor R3 and the electrolytic capacitor C4,
Power is supplied via the.

In other words, the voltage of the power supply supplied to the load 5c gradually increases as shown in FIG. 4B, and the load 5c is turned on just before the start of the time slot. As shown in FIG. 4 (c), an operation state is entered. In this way, one of the TDMA time slots is received.

[0024]

As described above, the conventional power supply circuit must start supplying the entire power supply earlier than the time slot to be actually received, in accordance with the circuit part whose startup is slow. In addition, there is a problem that power consumption cannot be suppressed.

The present invention has been made in view of the above circumstances, and provides a power supply circuit capable of reducing the power consumption of the entire circuit by separately supplying power for quickly starting a circuit portion having a slow start. With the goal.

[0026]

According to a first aspect of the present invention, there is provided a power supply circuit having transmission means for transmitting a power supply voltage to a load in a specific time. Between the time just before the load should be operated and the time just before the power supply voltage converges, by shortening the specific time in the transmitting means, and transmitting the power supply voltage to the load in a short time, Power consumption can be reduced.

According to a second aspect of the present invention for solving the problems of the conventional example, the power supply circuit according to the first aspect has the following features.
The transmission means includes an NPN transistor, a resistor connected between the collector terminal and the base terminal of the NPN transistor, and a capacitor having one end connected to the base terminal of the NPN transistor and the other end grounded. Means, wherein the specific time is a specific time specified by the resistor and the capacitor. To shorten the specific time in the transmitting means, a short-circuit is substantially established between the collector terminal and the base terminal of the NPN transistor. This is characterized in that the power consumption can be reduced.

According to a third aspect of the present invention, there is provided a regulator for outputting a power supply voltage, a resistor provided between a collector terminal and a base terminal, and a base terminal connected via a capacitor. NPN which outputs a power supply voltage input from the regulator to the collector terminal via the emitter terminal when the capacitor is charged and a base current flows by accumulating electric charge in the capacitor.
A power supply circuit comprising: a transistor; a load receiving supply of a power supply voltage from an emitter terminal of the NPN transistor; and a control circuit for outputting a regulator control signal for controlling a timing at which the regulator outputs a power supply voltage to the regulator. The source terminal is connected to the collector terminal of the NPN transistor.
An FET having a drain terminal connected to the base terminal of the PN transistor and a gate terminal connected to the control circuit is provided, and the control circuit is configured to connect the load to the load more than when a time slot in which the load is used is started. A regulator control signal is output to the regulator from a first point in time before the time when the power supply voltage supplied from the emitter terminal of the NPN transistor is stabilized to a second point in time when the used time slot ends. By doing so, during the period from the first time point to the second time point, the power supply voltage is output from the regulator, and the time from the first time point to immediately before the power supply voltage is stabilized is a high-speed rising time. A control circuit for outputting a rising signal to a gate terminal of the FET, wherein the FET receives a signal from the control circuit. When through the door terminal receives an input of high-speed starting signal, the is characterized by a FET for substantially short-circuit between the source and drain terminals, power consumption can be reduced.

[0029]

Embodiments of the present invention will be described with reference to the drawings. A power supply circuit (this circuit) according to an embodiment of the present invention supplies electric power to a load with a slow start by using an FET to rapidly transfer electric charge for a certain period of time to reduce the start-up time. As a result, the time for supplying power to the entire circuit by a simple circuit can be shortened as a result, and power consumption can be reduced.

This circuit will be described with reference to FIGS.
FIG. 1 is a circuit diagram of the present circuit, and FIG. 2 is a timing chart illustrating the operation of the present circuit. As shown in FIG. 1, this circuit mainly includes a power supply 1, a control circuit 2 ', a regulator 3, an NPN transistor 4, a load 5, and an FET 6.

Each part will be specifically described below.
, The regulator 3, the NPN transistor 4, and the load 5 are the same as those of the related art, and the description thereof is omitted here. In the claims, the resistor R3, the electrolytic capacitor C4, and the NPN transistor 4 of the circuit shown in FIG. 1 are collectively referred to as "transmission means".

The control circuit 2 'determines the timing immediately before the start of the time slot to be used ("first" in the claims).
), The regulator control signal (Reg-Cont) is output to the regulator 3, and the regulator control signal (Reg-Cont) is output to the regulator 3 at the timing when the time slot ends (referred to as “second time” in the claims). Will not be output.

Further, the control circuit 2 'outputs a high-speed start-up signal (CH-Gup) to the gate terminal (G) of the FET 6 at the timing when the output of the regulator control signal is started, so that the load 5c of the load 5c whose start-up time is relatively long is reduced. The output of the high-speed start-up signal is stopped after a lapse of a time when the power supply voltage becomes about 90% of the convergence state.

Here, the pulse width of the high-speed start-up signal (the time from the start of activation until the power supply voltage reaches 90% of the converged state) can be adjusted by changing the setting of the control circuit 2 '.
An external CR circuit may be used for adjustment.

The source terminal (S) of the FET 6 is NP
The collector terminal (C) of the N-transistor 4 and its drain terminal (D) are connected between the base terminal (B) of the NPN transistor 4 and the electrolytic capacitor C4, and the control voltage is applied to the gate terminal (G). Is applied, the resistance between the source terminal (S) and the drain terminal (D) becomes extremely small.

It is to be noted that each load 5 receives a power supply via a resistor R, and a terminal for receiving a power supply voltage of each load 5 is grounded via a capacitor C. Although there is a known method of increasing power supply isolation, here, for the sake of simplicity,
Description of such a circuit is omitted.

Next, the operation of this circuit will be described. As shown in FIG. 2, immediately before the time slot to be used, the control circuit 2 'controls the regulator control signal (Reg-c).
ont) and a high-speed start-up signal (CH-Gup).

Then, the regulator 3 receiving the input of the regulator control signal supplies the power supplied from the power supply 1 to the loads 5a and 5b as in the conventional case,
The collector terminal (C) of the NPN transistor 4 and the resistor R
3, the base terminal (B) of the NPN transistor 4
And the power supply to the source terminal (S) of the FET 6. Then, the loads 5a and 5b are immediately activated.

On the other hand, when the FET 6 receives the input of the high-speed rising signal to the gate terminal (G), the resistance value between the source terminal (S) and the drain terminal (D) decreases, and The supplied power is directly supplied to the base terminal (B) of the NPN transistor 4 via the drain terminal (D).

Then, the electric charge is rapidly stored in the electrolytic capacitor C4, the base current of the NPN transistor 4 increases, and the electric charge is rapidly transmitted from the emitter terminal (E).
Power is supplied to the load 5c.

Then, the load 5c is started, and when the power supply voltage of the load reaches about 90% of the converged state, the control circuit 2 'does not output the high-speed start-up signal. Then, the FET 6 does not transmit power from the source terminal to the drain terminal (D), and the load 5c is supplied with power by the NPN transistor 4 as in the related art.

However, thereafter, power is supplied to the load 5c via the NPN transistor 4, and the potential is stabilized (FIG. 2).
(C)), the operation of the load 5c becomes stable (FIG. 2)
(D)). Eventually, at the end of the time slot to be used, the control circuit 2 'stops outputting the regulator control signal, and the power is not supplied to the load 5.

According to this circuit, a simple circuit is provided for the load 5c having an NPN transistor circuit for preventing the influence of the fluctuation of the power supply voltage, so as to shorten the start-up time so that the state can be instantaneously shifted to an operable state. As a result, electric power is temporarily supplied immediately before the time slot and power is supplied, so that there is an effect that power consumption in a system that is periodically started can be reduced.

[0044]

According to the first aspect of the present invention, the specific time required for the transmitting means to transmit the power supply voltage to the load is from just before the time when the load should operate to immediately before the power supply voltage converges. And the power supply circuit for transmitting the power supply voltage to the load in a short time, there is an effect that the time for supplying the power supply voltage to the transmission means can be reduced and the power consumption can be reduced.

According to the second aspect of the present invention, the transmitting means has an NPN transistor, a resistor connected between its collector terminal and the base terminal, one end connected to the base terminal, and the other end grounded. The specific time is a specific time specified by the resistor and the capacitor. To shorten the specific time, NP
The power supply circuit according to claim 1, wherein the power supply circuit is realized by substantially short-circuiting the collector terminal and the base terminal of the N transistor, so that the time required to supply the power supply voltage to the transmission means can be reduced, and the power consumption can be reduced. There is.

According to the third aspect of the present invention, the control circuit outputs a regulator control signal to the regulator from the first time to the second time, and the regulator supplies power to the collector terminal of the NPN transistor. At the same time, a high-speed start-up signal is output to the gate terminal of the FET from the first point in time until immediately before the power supply voltage of the load is stabilized, so that the FET is a power supply circuit that short-circuits the collector terminal and the base terminal of the NPN transistor substantially. Therefore, by the action of the FET, the electric charge is rapidly accumulated in the capacitor connected to the NPN transistor, the timing at which the base current flows is advanced, and the power supply voltage supplied to the collector terminal of the NPN transistor is transmitted through the emitter terminal. To the load to reduce the time required for the power supply voltage to stabilize. By shortening the time for which the power supply voltage is supplied, there is an effect that power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power supply circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the present circuit.

FIG. 3 is a circuit diagram of a conventional power supply circuit.

FIG. 4 is a timing chart illustrating an operation of a conventional power supply circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Power supply 2, 2 '... Control circuit, 3 ... Regulator, 4 ... NPN transistor, 5 ... Load, 6 ... F
ET

Claims (3)

[Claims] 1. A power supply circuit comprising a transmission means for transmitting a power supply voltage to a load in a specific time period, wherein the power supply circuit includes: A power supply circuit, wherein the power supply circuit transmits a power supply voltage to a load in a short time by shortening the specific time in the transmission means. 2. An NPN transistor, a resistor connected between a collector terminal and a base terminal of the NPN transistor, one end connected to a base terminal of the NPN transistor, and the other end grounded. A specific time, which is a specific time specified by the resistor and the capacitor, and a method for reducing the specific time in the transmission means:
2. The power supply circuit according to claim 1, wherein the power supply circuit is realized by substantially short-circuiting a collector terminal and a base terminal of the NPN transistor. 3. A regulator for outputting a power supply voltage, a resistor provided between a collector terminal and a base terminal, a base terminal grounded via a capacitor, and a charge stored in the capacitor so that a base current flows. To become and,
An NPN transistor that outputs a power supply voltage input from the regulator to the collector terminal via an emitter terminal, a load receiving a power supply voltage from the emitter terminal of the NPN transistor, and a timing at which the regulator outputs the power supply voltage. A power supply circuit having a control circuit for outputting a regulator control signal to be controlled to the regulator, wherein a source terminal is connected to a collector terminal of the NPN transistor, a drain terminal is connected to a base terminal of the NPN transistor, and the control circuit An FET having a gate terminal connected thereto is provided, and the control circuit is provided for a time during which a power supply voltage supplied from the emitter terminal of the NPN transistor to the load is stabilized from a time point at which a time slot in which the load is used is started. Before From 1 time point to the second time point is the timing of the time slot is completed to the use,
By outputting a regulator control signal to the regulator, the regulator outputs a power supply voltage from the first time to the second time, and the power supply voltage is stabilized from the first time. The time until immediately before is a control circuit that outputs a high-speed start-up signal to the gate terminal of the FET. A power supply circuit, wherein the power supply circuit is a FET that substantially short-circuits between the FET and a drain terminal.