JPH1168618A - Synchronization acquisition circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the memory capacity of a synchronization acquisition circuit. SOLUTION: A branch section 110 obtains correlation between short codes of I and Q phase reception signals S111A, S111B to generate a correlation power signal. A synchronization object selection circuit 130 selects N-sets of high-order correlation power of higher values from the correlation power denoted by the correlation power signal and N-sets of correlation power values stored in an object storage memory 140 according to an object selection phase signal from a phase generating circuit 120 for an M frame period, and holds the selected values in the object storage memory 140. A phase selection circuit 150 adds a correlation power value of the same phase denoted by the correlation power signal to the correlation power values stored in the object storage memory 140 according to an added phase signal from the phase generating circuit 120. A synchronization discrimination circuit 160 discriminates a phase corresponding to the highest correlation power to be a frame synchronization position after the lapse of a period of an L frame period, while a long code identification section 200 identifies a long code, based on the phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a DS-CDMA.
(Direct Sequence-Code Division Multiple Access)
The present invention relates to a synchronization acquisition circuit used on a mobile station receiving side of a mobile radio communication system using the system.

[0002]

2. Description of the Related Art In a mobile radio communication system using the asynchronous cellular system between DS-CDMA base stations, channels using the same frequency band from a plurality of base stations are asynchronously multiplexed and received by the mobile station. You. In this case, information transmitted from the base station is spread using a long code unique to the base station so that the mobile station can determine which base station is used. Therefore, in order to communicate with a specific base station, the mobile station must first establish frame synchronization with that base station, identify a long code unique to the base station, and perform despreading using this long code. There is. One of the methods for establishing the base station frame synchronization in a short time is described in the following document.

Higuchi et al., "Two-Step High-Speed Initial Synchronization Method of Long Code in DS-CDMA Base Station Asynchronous Cellular System," IEICE Technical Report, CS96-19, RCS96-12, page 27, IEICE. (May 1996) "Synchronization acquisition method (cell search method) described in the above document
Will be described below. The frame period of the control channel from the base station to the mobile station is set to one long code period, and each frame includes symbols despread using only a short code common to the base stations. When performing a cell search, the mobile station first detects a correlation between a received signal and a short code on a receiving side during one frame period, calculates a correlation power value, and sequentially stores the correlation power value in a memory. This allows
For the received control channel of each base station, a peak of the correlation power value can be found for each reception phase of the short code spreading symbol.

[0004] The mobile station determines the phase having the maximum correlation power value within one frame as the frame synchronization position of the control channel of the base station desired to be connected. In an actual mobile communication environment, in order to remove the influence of inter-channel interference and fading, correlation is detected for a plurality of frame periods,
The correlation power value is calculated, the correlation power values in each phase are averaged, and the phase at which the maximum correlation power value is obtained is set as the frame synchronization position. Next, the mobile station identifies a long code for the control channel having the frame synchronization position. In the identification of the long code, the correlation detection is performed while changing the long code with respect to the obtained frame synchronization position, and the long code when the threshold value is exceeded is determined as the long code of the reception control channel. This ends the synchronization acquisition.

[0005]

However, in the above cell search method, when detecting the frame synchronization position, the correlation in all chip phases is detected over a plurality of frame periods, the correlation power value is calculated, and the averaging is performed. After that, the chip phase having the maximum correlation power value is set as the frame synchronization position, and the memory for storing the chip phase and the correlation power value is required as many as the number of chips in the frame period. There was a drawback that it would become something.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks of the prior art and to provide a synchronization acquisition circuit capable of acquiring synchronization with a small memory.

[0007]

According to the present invention, in order to solve the above-mentioned problem, a frame includes a symbol transmitted from a plurality of base stations using a CDMA system and spread in a frame with only a short code common to the base stations. In a synchronization acquisition circuit for acquiring synchronization with a reception signal received by multiplexing a transmission signal asynchronously, the circuit acquires a correlation with each short code in the reception signal and generates a correlation power value thereof. Means, and a phase generation means for sequentially generating a chip phase based on the input of the synchronization acquisition start signal when a synchronization acquisition start signal instructing the start of synchronization acquisition is input, and a correlation power value and the correlation power value. When the correlation power value is generated by the candidate holding unit that holds the phase value of the chip phase at the time of generation by a predetermined number of sets, and the branch unit, Of the correlation power values and the correlation power values held by the candidate holding means, a correlation power value having a larger value is selected by the number of sets described above, and all the selected correlation power values and the correlation power value generation are selected. Synchronization candidate selecting means for updating the held content of the candidate holding means with the phase value of the chip phase at the time, and the correlation held by the candidate holding means when a predetermined period has elapsed from the input of the synchronization acquisition start signal. A synchronization determining unit that determines a phase value corresponding to the largest correlation power value among the power values as a frame synchronization position.

Further, according to the present invention, a transmission signal transmitted from a plurality of base stations using a CDMA system and including a symbol spread in a frame with only a short code common to the base stations is asynchronously multiplexed and received. In a synchronization acquisition circuit that performs synchronization acquisition on a reception signal, the circuit includes a branch unit that obtains a correlation with each short code in the reception signal and generates a correlation power value thereof, and a synchronization acquisition instruction that starts synchronization acquisition. When a start signal is input, a phase generation means for sequentially generating a chip phase based on the beginning of each first period with a predetermined first period as a cycle, a correlation power value and a correlation power value of the correlation power value. Candidate holding means for holding a predetermined number of sets of the phase value of the chip phase at the time of generation, and a first period from the time of input of the synchronization start signal. When a correlation power value is generated by the branching means, a correlation power value having a large value is selected from the correlation power value and all the correlation power values held by the candidate holding means by the number of sets described above, Synchronization candidate selecting means for updating the content held by the candidate holding means with all selected correlation power values and the phase value of the chip phase at the time of generation of the correlation power value; and a predetermined synchronization candidate from the first period. In the second period, when a correlation power value is generated by the branch means, this correlation power value is held in the candidate holding means when the correlation power value and the phase value of the chip phase at the time of generation are the same correlation power value. A phase selecting means for adding the correlation power value to the stored correlation power value, and a correlation parameter having the largest value among the correlation power values held in the candidate holding means when the second period has elapsed. And having a synchronization determining means for determining a phase value corresponding to over value and the frame synchronization position.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a synchronization acquisition circuit according to the present invention;

First, a first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a synchronization acquisition circuit according to the first embodiment. The synchronization acquisition circuit receives control channel signals transmitted from a plurality of base stations, and generates an I-phase reception signal S100B and a Q-phase reception signal generated from the received signals.
From S100C, determine the frame synchronization position of the desired control channel, identify the long code, and
It outputs a S160A and a long code signal S200A, and has a frame synchronization detection unit 100 and a long code identification unit 200.

The frame synchronization detection section 100 generates a frame synchronization position signal S160A, and includes a branch section 110 comprising a matched filter 111 and a power operation circuit 112. The matched filter 111 performs a predetermined correlation operation on the input I-phase reception signal S100B and Q-phase reception signal S100C, and obtains the obtained correlation values as an I-phase correlation value signal S111A and a Q-phase correlation value signal S111B, respectively. This is output to the power operation circuit 112. The power operation circuit 112 outputs the I-phase correlation value signal from the matched filter 111.
A sum of squares operation is performed on S111A and the Q-phase correlation value signal S111B, and the result is output to the synchronization candidate selection circuit 130 and the phase selection circuit 150 as a correlation power signal S112A.

The phase generation circuit 120 sequentially generates chip phases for an M frame period (M times the period of one frame) based on a synchronization acquisition start signal S100A input from the outside, and converts the chip phase into a candidate selection phase signal. The chip phase is output to the synchronization candidate selection circuit 130 as S120A, and chip phases are sequentially generated with M frames as cycles during the subsequent L frame cycle (L times cycle of one frame), and this is used as the added phase signal S120B. When the output of the added phase signal S120B is completed, a frame synchronization detection end signal S120C indicating the end of the frame synchronization position detection operation is generated and output to the synchronization determination circuit 160.

Here, the chip phase is obtained by adding an index representing a phase position (phase value) from the beginning of the M frame period to a code in a chip unit. . Therefore, the phase position from the beginning of the M frame period at the time when the chip phase is output can be specified based on the phase value of the chip phase.

The synchronization candidate selection circuit 130 includes a phase generation circuit 12
Every time the phase value indicated by the candidate selection phase signal S120A (chip phase) input from 0 changes, the value indicated by the correlation power signal S112A from the power operation circuit 112 at that time is changed to the correlation power value corresponding to the phase value From the correlation power value and the N correlation power values held in the candidate holding memory 140, the upper N correlation power values having the largest correlation power are selected, and the selected correlation power value and the like are selected as phase candidates. It is output to the candidate holding memory 140 as a signal S130A.

Each time the phase value indicated by the added phase signal S120B (chip phase) input from the phase generation circuit 120 changes, the phase selection circuit 150 outputs the correlation power signal S112A input from the power operation circuit 112 at that time. Is the correlation power value corresponding to the phase value, and the correlation power value is the correlation power value held in the candidate holding memory 140 and corresponds to the same phase value as the phase value indicated by the added phase signal S120B. The correlation power value is output to the candidate holding memory 140 as the added power signal S150A.

The candidate holding memory 140 has a memory capable of holding N sets of correlation power values and phase values, the contents of which are reset by the synchronization acquisition start signal S100A. Then, when the phase candidate signal S130A is input from the synchronization candidate selection circuit 130, the memory content is updated by the signal, and the addition power signal S1
When 50A is input, the relevant portion of the memory content is updated by the signal. Also, the candidate holding memory 14
0 is a held content signal indicating the currently held memory content
S140A is always output to the synchronization candidate selection circuit 130, the phase selection circuit 150, and the synchronization determination circuit 160.

When the frame synchronization detection end signal S120C is input from the phase generation circuit 120, the synchronization determination circuit 160
The correlation power value having the largest correlation power is selected from the N correlation power values held in the candidate holding memory 140, and the phase value corresponding to this correlation power value is set as the frame synchronization position signal S160A as the external and long code. Identification unit 20
Output to 0.

The long code identification unit 200 has a means for generating a plurality of types of long codes determined in advance.
When 60A is input, a long code is generated according to the phase value indicated by the signal, and the I-phase received signal S100B and Q-phase received signal S1 from the outside are generated while sequentially changing the long code.
This is to detect the correlation with 00C, determine the long code of the control channel based on the detected correlation value, and output it as a long code signal S200A to the outside.

Next, the operation of the synchronization acquisition circuit according to the first embodiment will be described. The frame synchronization detection unit 100 of the synchronization acquisition circuit includes a synchronization acquisition start signal S100 input from the outside.
A, synchronization acquisition is started, and during the first half M frame period, N frame synchronization position candidates are selected, and the second half L frame candidate is selected.
During the frame period, the optimum frame synchronization position is selected from the N frame synchronization position candidates.

In FIG. 1, when a synchronization acquisition start signal S100A is inputted at a predetermined timing from the outside, the phase generation circuit 120 of the frame synchronization detection unit 100 adds the candidate selection phase signal S120A to the adder, as shown in FIG. A phase signal S120B and a frame synchronization detection end signal S120C are sequentially generated and output. More specifically, the phase generation circuit 120 sequentially generates chip phases for M frame periods with reference to the synchronization acquisition start signal S100A, and outputs this to the synchronization candidate selection circuit 130 as a candidate selection phase signal S120A. Then, during the L frame period following the M frame period, chip phases are sequentially generated with the M frame as a period, and this is added to the addition phase signal S1.
Output to the phase selection circuit 150 as 20B.

Therefore, during the L frame period, M
Chip phases having the same phase value are repeatedly output in the frame period. Further, when the output of the added phase signal S120B ends, the phase generation circuit 120 generates a frame synchronization detection end signal S120C and outputs it to the synchronization determination circuit 160. Note that the values of M and L can be set for one frame, but are usually set for a plurality of frames so that the effects of inter-channel interference and fading can be removed.

On the other hand, the matched filter 111 in the branch unit 110 of the frame synchronization detecting unit 100 receives control channel signals from a plurality of base stations using the CDMA system asynchronously multiplexed and receives them. The obtained I-phase reception signal S100B and Q-phase reception signal S100C are sequentially input. Here, it is assumed that the control channel frame of each base station includes a symbol spread only with a short code common to the base stations. FIG. 3 shows an example of this frame configuration. A period F1 is a period including a symbol spread only with a short code common to base stations, and a period F2 is a long code unique to each base station. Is a period in which the symbol spread in the period is included.

The matched filter 111 synchronizes the sequentially input I-phase reception signal S100B and Q-phase reception signal S100C with the chip phase generated by the phase generation circuit 120 by, for example, a matched filtering method. A correlation value is generated every time. Therefore, the received I-phase received signal S100B and Q-phase received signal S100C of each control channel are received.
The correlation value is sequentially obtained for each period spread by the short code. The matched filter 111 sequentially outputs the generated correlation values to the power calculation circuit 112 as an I-phase correlation value signal S111A and a Q-phase correlation value signal S111B, respectively.

The power operation circuit 112 includes a matched filter
111, the I-phase correlation value signal S111A and the Q-phase correlation value signal S1
When 11B is input, the I-phase correlation value signal S111A and the Q-phase correlation value signal S111B are each squared, and the sum is added to execute a square sum operation. Then, the result obtained by the sum of squares operation is output to correlation candidate selection circuit 130 and phase selection circuit 150 as correlation power signal S112A. The power calculation circuit 112 also executes a sum of squares operation in synchronization with the chip phase, and performs a correlation power signal.
It is assumed that the value of S112A is held until the next chip phase is input.

As described above, the synchronization candidate selection circuit 130 receives the candidate selection phase signal S120A from the phase generation circuit 120 during the M frame period. Synchronization candidate selection circuit 130
When the phase value indicated by the candidate selection phase signal S120A changes, the value of the correlation power signal S112A input from the power operation circuit 112 at that time is changed to the phase value θ _{N + 1} indicated by the candidate selection phase signal S120A. Power value P at
1 _{N + 1,} and from the holding content signal S140A constantly output from the candidate holding memory 140, the candidate holding memory
N correlation power values (P _{1 to} P
_N ) and their corresponding phase values.

Next, the synchronization candidate selection circuit 130 sorts the correlation power values P _{N + 1} and the correlation power values P _{1 to} P _N , and arranges them in descending order of correlation power to select the top N correlation power values. Then, the N correlation power values and the corresponding phase values are output to the candidate holding memory 140 as the phase candidate signal S130A. Candidate holding memory 14
When the phase candidate signal S130A is inputted, the memory contents are updated with N sets of correlation power values and phase values indicated by the phase candidate signal S130A.

As described above, the synchronization candidate selection circuit 130
During the frame period, the above-described operation is repeatedly performed every time the phase value indicated by the candidate selection phase signal S120A changes, and N phase values serving as synchronization position candidates are selected based on the magnitude of the correlation power. In this case, if the M frame period is set to be a multiple of one frame, the effects of inter-channel interference and fading can be eliminated. Further, the memory capacity of the candidate holding memory 140 is sufficient if it can store N sets of correlation power values and phase values. The value of N is usually determined by simulation or the like according to the performance requirements of the system. The synchronization candidate selection circuit 130 terminates its operation when the period of the M frame period has elapsed, and then the phase selection circuit
150 starts working.

The phase selection circuit 150 includes a synchronization candidate selection circuit.
During the L frame period from the end of the operation of 130, the added phase signal S120B is input from the phase generation circuit 120. Each time the phase value indicated by the added phase signal S120B changes, the phase selection circuit 150
Is defined as the correlation power value P _{N + 1 at the} phase value θ _{N + 1} indicated by the added phase signal S120B, and the held contents constantly output from the candidate holding memory 140. From the signal S140A, N sets of correlation power values and phase values (P _{1 to} P _N , θ _{1 to} θ _N ) held in the candidate holding memory 140 are grasped, and the phase value θ ₁
Some through? _N determine whether the phase value theta _n having the same value as the phase value theta _{N + 1} is present.

When a phase value θ _n having the same value as the phase value θ _{N + 1} exists, the phase selection circuit 150 adds the correlation power value P _{N +} to the correlation power value P _n corresponding to the phase value θ _{n. 1} adds, to output to the candidate holding memory 140 the phase value theta _n corresponding thereto correlation power values obtained and by adding as an addition power signal S150A. Candidate holding memory 140, when the addition power signal S150A from the phase selecting circuit 150 is input, the correlation power value stored previously in a correlation power value corresponding to the phase value theta _n indicated by the sum power signals S150A Instead, the correlation power value indicated by the added power signal S140A is held.

However, the phase selection circuit 150 calculates the phase value θ
If there is no phase value having the same value as _{N + 1} , the process is stopped there, and the process waits until the phase value indicated by the added phase signal S120B changes next. In this case, the addition power signal S150A is not output from the phase selection circuit 150, and the candidate holding memory 140
There is no change in the content.

As described above, the phase selection circuit 150 changes the phase value indicated by the addition phase signal S120B every time the phase value indicated by the addition phase signal S120B changes during the L frame period after the input of the first addition phase signal S120B.
The above operation is repeatedly performed on the N correlation power values held in the candidate holding memory 140. As a result, the correlation power value held in the candidate holding memory 140 increases when the correlation power value having the same phase value is generated during the L frame period, so that the influence of inter-channel interference and fading is reduced. Removed. Further, since the processing target is limited to N sets of correlation power values and phase values, the memory capacity of the candidate holding memory 140 can be reduced, and the circuit scale can be reduced. The phase selection circuit 150 ends its operation when the period of the L frame period has elapsed, and the synchronization determination circuit 160 starts its operation.

When the frame synchronization detection end signal S120C is input from the phase generation circuit 120, the synchronization determination circuit 160 outputs the held content signal S140 output from the candidate holding memory 140.
From A, N sets of correlation power values and phase values stored in the candidate holding memory 140 are grasped. Then, a correlation power value having the largest correlation power is selected from the N correlation power values, and a phase value corresponding to this correlation power value is set as a frame synchronization position signal S160A, and the long code identification unit 200
And output to the outside. The mobile station is connected to the base station of the control channel corresponding to the frame synchronization position. Note that the phase selection circuit 150 may be omitted, and the synchronization determination circuit 160 may determine a phase value that is a candidate for a frame synchronization position after the operation of the synchronization candidate selection circuit 130 is completed.

The long code identification unit 200 includes a synchronization determination circuit
When the frame synchronization position signal S160A is input from 160,
A long code synchronized with the phase indicated by the frame synchronization position signal S160A is generated, and correlation detection is performed on the input I-phase reception signal S100B and Q-phase reception signal S100C while sequentially changing the long code in a predetermined order. . And
When the correlation value exceeds a predetermined threshold, the long code is determined as a long code of the control channel,
This long code is output to the outside as a long code signal S200A.

As described above, according to the first embodiment of the present invention, the number of phase values as the synchronization position candidates is limited to N, so that the candidate holding memory 140 stores N sets of correlation power values and It is sufficient to provide a memory capable of storing the phase value, and it is not necessary to provide a number of memories corresponding to the number of chip phases in the frame period. Therefore, the circuit scale can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a synchronization acquisition circuit according to the second embodiment. The synchronization acquisition circuit receives control channel signals transmitted from a plurality of base stations with two antennas, respectively, and generates an I-phase reception signal generated from the reception signals.
From S300B, Q-phase reception signal S300C, I-phase reception signal S300D, and Q-phase reception signal S300E, the frame synchronization position of a desired control channel is determined, a long code is identified and a frame synchronization position signal S370A, a frame synchronization branch signal S3
70B and a long code signal S400A, and outputs a frame synchronization detection unit 300 and a long code identification unit.
400.

The frame synchronization detecting section 300 includes two branch sections corresponding to received signals received by two antennas. The first branch unit 310 includes a matched filter
The second branch section 320 is composed of a matched filter 321 and a power computation circuit 322. And the matched filter 31
1 and 321 are matched filters 111 shown in FIG.
Power operation circuits 312 and 322 are the same as power operation circuit 112 shown in FIG. 1, respectively.

Therefore, the first branch section 310 generates the correlation power signal S312A from the I-phase reception signal S300B and the Q-phase reception signal S300C received by one antenna, and outputs the correlation power signal S312A to the synchronization candidate selection circuit 340 and the phase selection circuit The second branch section 320 generates a correlation power signal S322A from the I-phase reception signal S300D and the Q-phase reception signal S300E received by the other antenna, and outputs this to the synchronization candidate selection circuit 340 and This is output to the phase selection circuit 360. In the present embodiment, the number of branch units is set to two for the sake of simplicity, but the present invention is not limited to this.

The phase generation circuit 330 is the same as the phase generation circuit 120 shown in FIG. 1. When the synchronization acquisition start signal S300A is input from outside, the phase selection circuit 330 converts the candidate selection phase signal S330A during the first M frame periods. And outputs it to the synchronization candidate selection circuit 340, and during the subsequent L frame period, generates an addition phase signal S330B and outputs it to the phase selection circuit 360,
Further, when the period of the L frame period has elapsed, a frame synchronization detection end signal S330C indicating the end of the frame synchronization position detection operation is generated and output to the synchronization determination circuit 370.

The synchronization candidate selection circuit 340 includes a phase generation circuit 33
Every time the phase value indicated by the candidate selection phase signal S330A (chip phase) input from 0 changes, the value indicated by the correlation power signal S312A from the first branch unit 310 and the correlation from the second branch unit 320 at that time point Power signal S322A
Are used as correlation power values. The correlation power value is determined in accordance with a predetermined procedure from the two correlation power values and the N correlation power values held in the candidate holding memory 350 obtained from the held content signal S350A. Is selected, and the selected correlation power value or the like is output to the candidate holding memory 350 as the phase candidate signal S340A.

Each time the phase value indicated by the added phase signal S330B (chip phase) input from the phase generation circuit 330 changes, the phase selection circuit 360 generates the correlation power signal S312A from the first branch section 310 at that time. The indicated value and the second
The value indicated by the correlation power signal S322A from the branch unit 320 is defined as the correlation power value, and the two correlation power values are stored in the candidate holding memory 350 obtained from the holding content signal S350A according to a predetermined procedure. The value is added to any of the values, and the added correlation power value and the like are output to the candidate holding memory 350 as an added power signal S360A.

The candidate holding memory 350 has a memory capable of holding N sets of correlation power values, phase values, and branch numbers. The memory contents are reset by the synchronization acquisition start signal S300A. Then, the synchronization candidate selection circuit 340
When the phase candidate signal S340A is input from the phase selection circuit 360, the content of the memory is updated by the signal, and when the added power signal S360A is input from the phase selection circuit 360, the relevant portion of the memory content is updated by the signal. . The candidate holding memory 350 always outputs the currently held memory contents as a held content signal S350A to the synchronization candidate selection circuit 340, the phase selection circuit 360, and the synchronization determination circuit 370.

When the frame synchronization detection end signal S330C is input from the phase generation circuit 330,
The correlation power value having the largest correlation power is selected from the N correlation power values held in the candidate holding memory 350, and the phase value and the branch number corresponding to this correlation power value are designated by the frame synchronization position signal S370A, It is output to the external and long code identification unit 400 as a frame synchronization branch signal S370B.

The long code identification unit 400 has means for generating a plurality of types of predetermined long codes.
When 70A and the frame synchronization branch signal S370B are input, a long code according to the phase indicated by the signal is generated, and the I-phase reception signal and the Q-phase reception signal indicated by the frame synchronization branch signal S370B are sequentially changed while changing the long code. , A long code of the control channel is determined based on the detected correlation value, and this is output to the outside as a long code signal S400A.

Next, the operation of the synchronization acquisition circuit according to the second embodiment will be described. The operation of this synchronization acquisition circuit is basically the same as that of the synchronization acquisition circuit shown in FIG.
The difference is that synchronization acquisition is performed using a set of I-phase reception signal S300B, Q-phase reception signal S300C, and I-phase reception signal S300D and Q-phase reception signal S300E.

In FIG. 4, the phase generation circuit 330 of the frame synchronization detection section 300 receives the synchronization acquisition start signal S300A from the outside at a predetermined timing, similarly to the case of the phase generation circuit 120 shown in FIG. , Its synchronization acquisition start signal
A chip phase is sequentially generated for M frame periods with reference to S300A, and is output to the synchronization candidate selection circuit 340 as a candidate selection phase signal S330A. Then, during the subsequent L frame period, chip phases are sequentially generated with M frames as a period, and this is output to the phase selection circuit 360 as an added phase signal S330B. Further, when the output of the added phase signal S330B ends, the phase generation circuit 330 generates a frame synchronization detection end signal S330C and outputs it to the synchronization determination circuit 370.

On the other hand, an I-phase reception signal S300B and a Q-phase reception signal S300C generated from a control channel reception signal received by one antenna are sequentially input to a first branch section 310 of the frame synchronization detection section 300. , 2nd branch section
To 320, an I-phase reception signal S300D and a Q-phase reception signal S300E generated from a control channel reception signal received by the other antenna are sequentially input. Here, the frame configuration of each control channel is the same as that of the first embodiment shown in FIG. The two antennas are arranged so as to obtain an antenna diversity effect.

The first branch section 310 correlates the input I-phase reception signal S300B and Q-phase reception signal S300C by the matched filter 311 and the power calculation circuit 312 in the same manner as the branch section 110 shown in FIG. Power signal
S312A is generated and output to the synchronization candidate selection circuit 340. Similarly to the case of the branch unit 110 shown in FIG. 1, the second branch unit 320 also uses the matched filter 321 and the power operation circuit 322 to input the I-phase reception signals S300D and Q
A correlation power signal S322A is generated from the phase reception signal S300E and output to the synchronization candidate selection circuit 340.

As described above, the candidate selection phase signal S330A is input from the phase generation circuit 330 to the synchronization candidate selection circuit 340 during the M frame period. Synchronization candidate selection circuit 340
When the phase value indicated by the candidate selection phase signal S330A changes, the value indicated by the correlation power signal S312A input from the first branch unit 310 at that time is changed to the phase value θ _N indicated by the candidate selection phase signal S330A. ₊₁ and the correlation power value P1 _{N + 1} corresponding to the branch number B1 of the first branch unit 310
The value indicated by the correlation power signal S322A input from the second branch unit 320 is defined as the phase value θ _{N + 1} and the correlation power value P corresponding to the branch number B2 of the second branch unit 320.
2 Defined as _{N + 1,} and from the holding content signal S350A constantly output from the candidate holding memory 350,
N sets of correlation power values, phase values, and branch numbers (P _{1 to} P _N , θ _{1 to} θ _N , B ₁
Figure B2).

Next, the synchronization candidate selection circuit 340 sorts the correlation power values P1 _{N + 1} , P2 _{N + 1} , and P _{1 to} P _N and arranges them in descending order of correlation power.
The correlation power values are selected, and the N correlation power values and the corresponding phase values and branch numbers are output to the candidate holding memory 350 as the phase candidate signal S340A. Upon receiving the phase candidate signal S340A from the synchronization candidate selection circuit 340, the candidate holding memory 350 updates the memory contents with N sets of correlation power values, phase values, and branch numbers indicated by the phase candidate signal S340A.

As described above, the synchronization candidate selection circuit 340
During the frame period, each time the phase value indicated by the candidate selection phase signal S330A changes, the above operation is repeatedly executed, and N phase values serving as synchronization position candidates are selected based on the magnitude of the correlation power. In this case, if the value of M is set to a multiple of one frame, the influence of inter-channel interference and fading can be eliminated. The memory capacity of the candidate holding memory 350 is sufficient if it can store N sets of correlation power values, phase values, and branch numbers. Note that the value of N is usually determined by simulation or the like according to the performance requirements of the system. The synchronization candidate selection circuit 340 ends its operation when the period of the M frame period has elapsed, and then the phase selection circuit 360 starts its operation.

As described above, the phase selecting circuit 360 supplies the added phase signal S33 from the phase generating circuit 330 during the L frame period.
0B is input. When the phase value indicated by the added phase signal S330B changes, the phase selection circuit 360 outputs the correlation power signal input from the first branch unit 310 at that time.
The value indicated by S312A is defined as the phase value θ _{N + 1} indicated by the added phase signal S330B and the correlation power value P1 _{N + 1} corresponding to the branch number B1 of the first branch unit 310, and the second branch unit
The value indicated by the correlation power signal S322A input from 320 is
Phase value θ _{N + 1} and branch number of second branch section 320
The correlation power value P2 corresponding to B2 is defined as P2 _{N + 1,} and the held content signal constantly output from the candidate holding memory 350.
From S350a, N sets of correlation power values stored in the candidate holding memory 350, the phase value, and the branch number (P ₁ ~
P _N , θ _{1 to} θ _N , B1 or B2).

Next, the phase selection circuit 360 checks whether or not a phase value θ _n having the same value as the phase value θ _{N + 1} exists among the _N phase values (θ _{1 to} θ _N ). And the phase value θ
When the phase value theta _n having the same value as _{N + 1} exists, then the branch numbers corresponding to the phase value theta _n is B1, the correlation in the correlation power value P _n corresponding to the phase value theta _n adding the power value P1 _{n + 1,} then the branch numbers corresponding to the phase value theta _n is B2 adds the correlation power value P2 _{n + 1} on the correlation power value P _n, the phase value theta _n When there are two branch numbers B1 and B2 in the branch numbers corresponding to the branch numbers B1 and B2, the correlation power values P1 _{N + 1} and P2 _{N + 1} are added to the correlation power values corresponding to the branch numbers B1 and B2, respectively.

Next, the phase selection circuit 360 outputs the correlation power value obtained by the addition, the corresponding phase value and the branch number to the candidate holding memory 350 as an addition power signal S360A. When the added power signal S360A is input, the candidate holding memory 350 receives the added power signal S3A.
The correlation power value indicated by the added power signal S360A is held in place of the previously stored correlation power value corresponding to the phase value and the branch number indicated by 60A.

However, the phase selection circuit 360 determines whether there is no phase value θ _n equal to the phase value θ _{N + 1} among the _N phase values (θ _{1 to} θ _N ), and Value (θ _{1 to} θ
_Even if there is a phase value θ _n having the same value as the phase value θ _{N + 1 in N} ), if the branch numbers are different, the processing is stopped there and the phase value indicated by the added phase signal S330B is returned. Wait for the next change. In this case, the addition power signal S360A is not output from the phase selection circuit 360, and the content of the candidate holding memory 350 does not change.

As described above, the phase selection circuit 360 operates every time the phase value indicated by the added phase signal S330B changes during the L frame period after the input of the first added phase signal S330B.
The above operation is repeatedly performed on the N correlation power values stored in the candidate holding memory 350. As a result, the correlation power value held in the candidate holding memory 350 increases when the correlation power value having the same phase value is generated during the L frame period, so that the influence of inter-channel interference and fading is reduced. Removed. Further, since the processing target is limited to N sets of correlation power values, phase values, and branch numbers, the memory capacity of the candidate holding memory 350 can be reduced, and the circuit scale can be reduced. When the period of the L frame period has elapsed, the phase selection circuit 360 ends its operation, and the synchronization determination circuit 370 starts its operation.

When the frame synchronization detection end signal S330C is input from the phase generation circuit 330, the synchronization determination circuit 370 determines the correlation having the largest correlation power among the N correlation power values stored in the candidate holding memory 350. The power value is selected, and the phase value and the branch number corresponding to the correlation power value are used as a frame synchronization position signal S370A and a frame synchronization branch signal S370B, respectively, as a long code identification unit.
400 and output to outside. The mobile station is connected to the base station of the control channel corresponding to the frame synchronization position by using the antenna corresponding to the branch indicated by the frame synchronization branch signal S370B. Note that the phase selection circuit 360 may be omitted, and after the operation of the synchronization candidate selection circuit 340 is completed, the synchronization determination circuit 370 may determine a candidate phase value of the frame synchronization position.

The long code identification unit 400 includes a synchronization determination circuit
When the synchronous position signal S370A and the frame synchronous branch signal S370B are input from the 370, the synchronous position signal S370A
And generates a long code synchronized with the phase indicated by the frame synchronization branch signal S370B while sequentially changing the long code in a predetermined order with respect to the I-phase reception signal and the Q-phase reception signal input to the branch indicated by the frame synchronization branch signal S370B. Perform detection.
When the correlation value exceeds a predetermined threshold value, the long code is determined as the long code of the control channel, and this long code is output to the outside as a long code signal S400A.

As described above, according to the second embodiment, even when a plurality of branch units are provided, the synchronization candidate selection circuit 340, the candidate holding memory 350, and the phase selection circuit 360 are provided for each branch unit. Since they are shared, the circuit scale does not increase. Also, the candidate holding memory 350
Requires only a memory capable of storing N sets of correlation power values, phase values, and branch numbers, so that the circuit scale can be reduced.

[0059]

As described above, according to the present invention, a frame synchronization position with respect to a desired control channel is selected by detecting each part spread by a short code for a plurality of asynchronous control channel signals. In this case, since the number of frame synchronization position candidates is limited to N, it is sufficient to provide a memory capable of storing N sets of correlation power values and phase values. Therefore, it is not necessary to provide the number of memories corresponding to the number of chip phases in the frame period unlike the related art.
The circuit scale can be greatly reduced.

Further, when a plurality of asynchronous control channels are received by different antennas and a frame synchronization position for a desired control channel is selected from the received signals,
Since the synchronization candidate selection means, candidate holding memory, phase selection means, etc. are shared, the circuit scale does not increase, and a memory capable of storing N sets of correlation power values, phase values, and branch numbers is provided. Is enough. Therefore, the circuit scale can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a synchronization acquisition circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing signals output from a phase generation circuit 120 in FIG.

FIG. 3 is a diagram showing a frame configuration of an I-phase reception signal S100B and a Q-phase reception signal S100C in FIG. 1;

FIG. 4 is a block diagram showing a synchronization acquisition circuit according to the first embodiment of the present invention.

[Description of Signs] 100, 300 Frame Synchronization Detection Units 110, 310, 320 Branch Units 111, 311, 321 Matched Filters 112, 312, 322 Power Operation Circuit 120, 330 Phase Generation Circuit 130, 340 Synchronization Candidate Selection Circuit 140, 350 Candidate holding memory 150, 360 Phase selection circuit 160, 370 Synchronization judgment circuit 200, 400 Long code identification unit

Claims (8)

[Claims] A transmission signal transmitted from a plurality of base stations using a CDMA system and including a frame and a symbol spread only with a short code common to the base stations is asynchronously multiplexed and received. A synchronization acquisition circuit for acquiring synchronization with each short code in the received signal and generating a correlation power value thereof; and a synchronization acquisition start signal for instructing start of synchronization acquisition. Is input, a phase generating means for sequentially generating a chip phase based on the input of the synchronization acquisition start signal, a correlation power value and a phase value of the chip phase at the time of generation of the correlation power value are determined in advance. A candidate holding means for holding the set of sets, and when the correlation power value is generated by the branch means, the correlation power value is held by the candidate holding means. The correlation power value having the larger value is selected from all the correlation power values that have been set, by the number of sets, and the candidate holding is performed based on all the selected correlation power values and the phase value of the chip phase when the correlation power value is generated A synchronization candidate selecting means for updating the held content of the means, and when a predetermined period has elapsed since the input of the synchronization acquisition start signal, the largest correlation power value among the correlation power values held by the candidate holding means. A synchronization determining means for determining a phase value corresponding to the correlation power value as a frame synchronization position. 2. A transmission signal transmitted from a plurality of base stations using the CDMA system and including a symbol spread in a frame with only a short code common to the base stations is asynchronously multiplexed and received. A synchronization acquisition circuit for acquiring synchronization with each short code in the received signal and generating a correlation power value thereof; and a synchronization acquisition start signal for instructing start of synchronization acquisition. When the input is inputted, a phase generating means for sequentially generating a chip phase with a cycle of a predetermined first period as a reference and a start of each first period as a reference, a correlation power value and a time when the correlation power value is generated Candidate holding means for holding a predetermined number of sets of the phase values of the chip phases in the first and second phases, and in the first period from the time of inputting the synchronization acquisition start signal. When the correlation power value is generated by the branch unit, a correlation power value having a large value is selected by the number of sets from among the correlation power value and all the correlation power values held by the candidate holding unit. Synchronization candidate selecting means for updating the held content of the candidate holding means with all the selected correlation power values and the phase value of the chip phase at the time of generating the correlation power value; Prescribed second
In the period, when the correlation power value is generated by the branch means, the correlation power value is held in the candidate holding means when the correlation power value and the phase value of the chip phase at the time of generation are the same correlation power value. A phase selecting means for adding the correlation power value to the selected correlation power value, and a phase corresponding to the largest correlation power value among the correlation power values held by the candidate holding means when the second period has elapsed. A synchronization determination circuit for determining a value as a frame synchronization position; 3. A transmission signal transmitted from a plurality of base stations using the CDMA system and including a symbol spread in a frame with only a short code common to the base stations is multiplexed asynchronously by a plurality of antennas and received. A synchronization acquisition circuit that performs synchronization acquisition on a received signal, the circuit comprising: a plurality of branch means for obtaining a correlation with each short code in the reception signal and generating a correlation power value; and starting synchronization acquisition. A phase generation means for sequentially generating a chip phase based on the input of the synchronization acquisition start signal when the synchronization acquisition start signal is input, a correlation power value and a phase of the chip phase when the correlation power value is generated Candidate holding means for holding a predetermined number of sets of values and the number of the branch means for which the correlation power value has been generated; When a correlation power value is generated in any of the cases, a correlation power value having a large value is selected from the correlation power value and all the correlation power values held by the candidate holding means by the number of sets, and the selection is performed. Synchronization candidate selection means for updating the held contents of the candidate holding means with all the correlation power values obtained, the phase value of the chip phase at the time of generation of the correlation power value, and the number of the branch means at which the correlation power value was generated. When a predetermined period elapses from the input of the synchronization acquisition start signal, the phase value corresponding to the largest correlation power value among the correlation power values held by the candidate holding means is set to the correlation value. A synchronization acquisition circuit, comprising: synchronization determination means for determining a frame synchronization position of a received signal input to a branch means having generated a power value. 4. The synchronization acquisition circuit according to claim 1, wherein the predetermined period is one frame period or a multiple of one frame period. 5. The synchronization acquisition circuit according to claim 1, wherein said branch means, candidate holding means, and synchronization candidate selection means operate in synchronization with a chip phase sequentially generated by said phase generation means. A synchronization acquisition circuit characterized in that: 6. A transmission signal transmitted from a plurality of base stations using the CDMA scheme and including a symbol spread in a frame with only a short code common to the base stations is asynchronously multiplexed by a plurality of antennas and received. A plurality of branch means corresponding to the plurality of antennas for obtaining a correlation with each short code in the received signal and generating a correlation power value thereof. A phase generation means for sequentially generating a chip phase with a predetermined first period as a cycle and a start of each of the first periods as a reference when a synchronization capture start signal instructing the start of the synchronization capture is input And the correlation power value, the phase value of the chip phase at the time of generation of the correlation power value, and the number of the branch means in which the correlation power value was generated. Candidate holding means for holding a predetermined number of sets; and, when a correlation power value is generated in any of the branch means during the first period from the input of the synchronization acquisition start signal, the correlation power A large correlation power value is selected by the number of sets from among the values and all the correlation power values held by the candidate holding means, and all the selected correlation power values and the correlation power value at the time of generation of the correlation power value are selected. Synchronization candidate selecting means for updating the content held in the candidate holding means by the phase value of the chip phase and the number of the branch means in which the correlation power value was generated; and a predetermined second predetermined time period after the first period has elapsed. 2
In the period, when the correlation power value is generated by the branching means, the correlation power value is determined to be the same as the correlation power value, and the phase value of the chip phase at the time of generation and the number of the branching means are the same correlation power value. Phase selecting means for adding to the correlation power value held in the candidate holding means; and, when the second period has elapsed, the correlation power having the largest value among the correlation power values held in the candidate holding means. A synchronization determination circuit that determines a phase value corresponding to the value as a frame synchronization position of a received signal input to the branch unit that has generated the correlation power value. 7. The synchronization acquisition circuit according to claim 2, wherein said first period is one frame period or a multiple of one frame period, and said second period is said first period or said one period. A synchronization acquisition circuit having a multiple of the first period. 8. The synchronization acquisition circuit according to claim 2, wherein said branch means, candidate holding means, synchronization candidate selection means, and phase selection means synchronize with a chip phase sequentially generated by said phase generation means. And a synchronization acquisition circuit.