JPH1167698A - Semiconductor chip and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor chip, which can separate the semiconductor chip from a semiconductor wafer without damaging it and by which fluid material is difficult to flow out in a manufacturing process. SOLUTION: In an RIE process, an interlayer film 42 of a chip isolation region 34 is removed in dot forms, and multiple small holes for cut assisting hole 90 are formed. Thus a resist which is applied later seldom flows into the holes for cut assisting hole 90. Recessed parts generated on the upper face of a first USG layer 44 formed on the small holes for cut assisting hole 90 are also in the from of the small dot. Thus, the large amount of an SOG layer 46 applied on the per face of the first USG layer 44 is prevented from flowing into the recessed parts. Even if cracks and the like occur at the time of cutting the semiconductor wafer, the advance of an occurred crack and the like can be stopped in any holes for cut assisting holes 90, 92, 94 and 96.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, and more particularly to a method of manufacturing a semiconductor chip having a chip separation step of separating a semiconductor chip from a semiconductor wafer in a predetermined chip separation region of the semiconductor wafer.

[0002]

2. Description of the Related Art There is known a technique for obtaining a plurality of dies (semiconductor chips) by cutting a single wafer on which a large number of semiconductor elements are formed with a dicing saw or the like. FIG. 8 shows the operation of cutting a die from a silicon wafer (in the case of full cutting). First, as shown in FIG. 8A,
The wafer 2 is attached to a plastic film 4 having a surface coated with an adhesive. Next, as shown in FIG. 8B, the bonded wafer 2 is completely cut by the dicing saw 6.

When cutting the die 8 from the wafer 2, cutting lines 10 and 12 (see FIG. 9) of the wafer 2 are used to prevent a part (particularly, upper part) of the die 8 from being damaged by the dicing saw 6. 8A, the cutting assist groove 1 as shown in FIG.
8 are provided. The cutting assist groove 18 is formed by etching at the same time as the insulating layer 24 (see FIG. 10A) of the wafer 2 is etched.

As described above, by providing the cutting assisting grooves 18, a large number of dies 8 can be cut out from the wafer 2 without being damaged (see FIG. 9).

[0005]

However, the above-mentioned conventional methods have the following problems. The cutting assist groove 18 is formed by etching simultaneously with the etching step of the insulating layer 24 of the wafer 2. Therefore, if there is a step of forming an aluminum wiring or the like after this etching step, a part of the resist 22 formed as shown in FIG. 10A for patterning the aluminum wiring 20 is cut off as shown in FIG. 10B. It flows into the dent created by the auxiliary groove 18.

When the aluminum wiring 20 is etched using such a resist 22 as a mask, FIG.
As shown in FIG. 2C, the aluminum wiring 2 near the cutting assist groove 18 is formed.
The shape 0 is different from the desired shape. In this case, the function of the obtained die 8 may be hindered.

In some cases, an SOG (Spin On Glass) method is used to planarize the insulating layer 24 serving as a base of the aluminum wiring 20. The SOG method is a method of applying an insulating material having fluidity so as to fill a concave portion (not shown) on the upper surface of the insulating layer 24. At this time, the applied insulating material flows into the cutting assist groove 18. Therefore, the flattening of the insulating layer 24 may not be performed as expected.

The present invention solves such a problem,
Separation assisting recesses (cutting assist grooves) that can separate (cut) semiconductor chips (die) from a semiconductor wafer without damaging them, and that are difficult to flow a fluid material such as a resist or an insulating material for SOG. It is an object of the present invention to provide a semiconductor chip having the same and a method for manufacturing the semiconductor chip.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor chip, comprising: an insulating layer etching step of etching an insulating layer formed on a semiconductor wafer; A chip separating step of separating the semiconductor chip, wherein at least one insulating layer etching step prior to the chip separating step, the insulating layer in the chip separating region includes a plurality of separation assists. The recess is formed by etching.

According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor chip according to the first aspect, wherein the plurality of separation assisting recesses are replaced by a plurality of linear recesses.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor chip according to the first aspect, wherein the plurality of separation assisting recesses are a plurality of point-like recesses.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor chip according to any one of the first to third aspects, two or more insulating layers are etched in two or more insulating layer etching steps. A plurality of separation assisting concave portions are formed, respectively.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor chip according to the fourth aspect, the plurality of separation assisting recesses are formed in two insulating layers vertically contacting each other in the chip separation region. In this case, a plurality of separation assisting recesses formed in each of the insulating layers are formed at positions where they do not vertically overlap.

According to a sixth aspect of the present invention, there is provided a semiconductor chip separated from a semiconductor wafer in a predetermined chip separating area of the semiconductor wafer, the semiconductor chip having at least one insulating layer formed in a predetermined shape by etching. In the chip, the insulating layer in the chip separation region includes
A plurality of separation assisting recesses formed by etching are provided.

[0015]

According to a first aspect of the present invention, in the method of manufacturing a semiconductor chip, a plurality of separation assisting recesses are etched in the insulating layer in the chip separating region in at least one insulating layer etching step prior to the chip separating step. It is characterized by being formed by.

Therefore, when the semiconductor chip is separated from the semiconductor wafer, the progress of damage can be prevented in any of the plurality of separation assisting concave portions. Also, since a plurality of separation assisting recesses are provided in the chip separation area, the opening area of each separation assisting recess can be reduced as compared with the case where one separation assisting recess is provided in the chip separation area. it can. Therefore, a fluid material such as a resist or an insulating material for SOG does not easily flow into the separation assisting recess.

That is, there is provided a method of manufacturing a semiconductor chip having a separation assisting concave portion which can separate a semiconductor chip from a semiconductor wafer without damaging the semiconductor chip and into which a fluid material such as a resist or an insulating material for SOG does not easily flow. Can be realized.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor chip, the plurality of separation assisting recesses are replaced with a plurality of linear recesses. Therefore, the progress of damage when separating the semiconductor chip from the semiconductor wafer can be more reliably prevented. Therefore, the semiconductor chips can be more reliably separated from the semiconductor wafer without being damaged.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor chip, the plurality of separation assisting recesses are replaced by a plurality of point-like recesses. Therefore, the opening area of each of the separation assisting concave portions can be further reduced. For this reason, the fluid material is less likely to flow into the separation assisting recess.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor chip.
In the above-described insulating layer etching step, a plurality of separation assisting concave portions are respectively formed in two or more insulating layers. Therefore, the progress of damage when separating the semiconductor chip from the semiconductor wafer can be more reliably prevented. Therefore, the semiconductor chips can be more reliably separated from the semiconductor wafer without being damaged.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor chip, wherein a plurality of separation assisting recesses are formed in each of two insulating layers vertically contacting each other in a chip separation region. It is characterized in that the auxiliary concave portion is formed at a position where it does not overlap vertically.

Therefore, when forming the separation assisting concave portion in the upper layer, the same portion as the separation assisting concave portion formed in the lower layer is not removed again by etching. Therefore, unlike the case where the same portion is removed again, the semiconductor chip is not adversely affected by excessive etching.

According to a sixth aspect of the present invention, in the semiconductor chip, a plurality of separation assisting concave portions formed by etching are provided in the insulating layer in the chip separating region.

Therefore, when the semiconductor chip is separated from the semiconductor wafer, the progress of damage can be prevented in any of the plurality of separation assisting concave portions. Also, since a plurality of separation assisting recesses are provided in the chip separation area, the opening area of each separation assisting recess can be reduced as compared with the case where one separation assisting recess is provided in the chip separation area. it can. Therefore, a fluid material such as a resist or an insulating material for SOG does not easily flow into the separation assisting recess.

That is, it is possible to realize a semiconductor chip which can be separated from a semiconductor wafer without damaging the semiconductor chip and which has a separation assisting concave portion into which a fluid material such as a resist or an insulating material for SOG does not easily flow. Can be.

[0026]

FIG. 1 is a view showing a part of a plane configuration of a wafer 30 which is a semiconductor wafer before cutting out a die 32 which is a semiconductor chip according to an embodiment of the present invention. FIG. 2 is a drawing showing a cross section II-II in FIG. In this embodiment, the die 32 is a MOS-FE
T (Metal Oxide Semiconductor-Field Effect Tran
sistor) will be described as an example.

As shown in FIG. 1, a large number of dies 32 are arranged on a wafer 30 by chip separation regions 34 arranged vertically and horizontally. Chip separation area 3
4, a plurality of point-like concave portions (separation auxiliary concave portions) are formed with cutting auxiliary holes 96 (94).

In FIG. 1, each of the chip separation regions 34 arranged vertically and horizontally has a cutting assist hole 96.
Although the example in which the (94) are arranged in three rows is shown, the number of rows of the cutting assistance holes 96 (94) is not limited to this.
It should be noted that in practice, the cutting assist holes 96 (9
4) is often arranged.

As shown in the cross section of FIG. 2, the chip separating region 34 of the wafer 30 is generally formed by stacking interlayer films 42, 49, 55 and passivation films 56 as insulating layers on a silicon substrate 40. have. The broken line 41 in the figure indicates the silicon substrate 40 and the interlayer film 42.
Represents the boundary with

In the interlayer film 42, a large number of cutting assist holes 90, which are point-like concave portions reaching the silicon substrate 40, are formed.

An interlayer film 49 is formed so as to fill the cutting assisting hole 90. The interlayer film 49 includes an interlayer film 4
A large number of cutting auxiliary holes 92, which are point-like concave portions reaching the number 2, are formed. The cutting auxiliary holes 92 are formed in the lower interlayer film 4.
2 is provided at a position that does not overlap with the cutting assisting hole 90 formed in FIG.

An interlayer film 55 is formed so as to fill the hole 92 for assisting cutting. In the interlayer film 55, a large number of cutting assist holes 94, which are point-like concave portions reaching the interlayer film 49, are formed. The cutting assist hole 94 is provided at a position that does not overlap with the cutting assist hole 92 formed in the lower interlayer film 49.

The passivation film 5 provided on the uppermost part
6 is provided with a large number of cutting assistance holes 96 which are point-like concave portions continuous with the cutting assistance holes 94. Therefore, the cutting assisting holes 94 and the cutting assisting holes 96 are provided at positions that vertically overlap.

Next, a method of manufacturing such a wafer 30 will be described with reference to FIGS. 3A to 5B and FIG. First, a gate (not shown) is formed on a predetermined portion of the die 32 (see FIG. 1) above the silicon substrate 40 shown in FIG. 3A, and an interlayer film 42 is formed so as to cover the gate. The interlayer film 42 is formed of BPSG (boron-phosphorus-silicate glass) by a CVD method (a vapor phase growth method involving a chemical reaction) or the like.
Is formed by depositing.

Thereafter, in an RIE (reactive ion etching) process which is an insulating layer etching process for making contact (not shown) with the silicon substrate 40 at a predetermined portion of the die 32, an interlayer film of the chip separation region 34 is formed. 42 is removed in the form of a dot to form a hole 90 for assisting cutting. The etching is performed until the bottom of the cutting assisting hole 90 slightly bites into the silicon substrate 40.

Thereafter, a first aluminum wiring (not shown) is formed on a predetermined portion of the die 32 (see FIG. 1). As described above, the cutting assistance holes 90 in the chip separation region 34 are
Since it is formed in the shape of fine dots, the resist (not shown) used for forming the first aluminum wiring is cut into the holes 90 for assisting cutting.
It doesn't flow much. Therefore, unlike the conventional case (see FIG. 10C), the shape of the first aluminum wiring does not become different from the desired shape.

Next, an interlayer film 49 shown in FIG. 3B is formed so as to cover the first aluminum wiring. Interlayer film 49
Is formed, the previously opened cutting assistance hole 90 is filled back. The interlayer film 49 is formed of the first USG layer 44, SO
It is obtained by forming the G layer 46 and the second USG layer 48 in this order.

That is, first, the first USG layer 44 is formed. The first USG layer 44 is made of USG by a CVD method or the like.
(Undoped silicate glass). Next, using the SOG (Spin On Glass) method,
An SOG layer 46 made of an insulating material is applied so as to fill the recesses on the upper surface of the first USG layer 44. Thereby, the upper surface of the first USG layer 44 can be substantially flattened. Next, a second USG layer 48 is formed on the upper surface of the first USG layer 44 that has been substantially planarized. Thus, the interlayer film 49 having a flat upper surface can be obtained.

As described above, since the cutting assisting hole 90 in the chip separating area 34 is formed in a fine dot shape,
The concave portions formed on the upper surface of the first USG layer 44 formed thereon are also small dots. Therefore, the first USG
The SOG layer 46 applied on the upper surface of the layer 44 does not flow into the concave portion in a large amount. Therefore, the flattening of the interlayer film 49 is not impaired as in the related art.

Next, RIE, which is an insulating layer etching step for making contact with the above-mentioned first aluminum wiring, is performed.
In the (reactive ion etching) step, as shown in FIG. 4A, the interlayer film 49 in the chip separation region 34 is removed in a dot shape, and a cutting assisting hole 92 is formed. Etching is
The process is performed until the bottom of the cutting assisting hole 92 reaches an extent that reaches the interlayer film 42.

The cutting auxiliary holes 92 are formed in the lower interlayer film 4.
2 is provided at a position that does not overlap with the cutting assisting hole 90 formed and backfilled. Therefore, when forming the upper cutting auxiliary hole 92, the cutting auxiliary hole 90 formed and buried in the lower interlayer film 42 is not removed again by etching. For this reason, the silicon substrate 40 is not excessively etched as in the case where the buried backing hole 90 is etched again.

Thereafter, a second aluminum wiring (not shown) is formed on a predetermined portion of the die 32 (see FIG. 1). As in the case of the first aluminum wiring (described above), since the cutting assisting holes 92 in the chip separation region 34 are formed in fine dots, a resist (FIG. (Not shown) rarely flows into the cutting assistance holes 92. For this reason, unlike the conventional case, the shape of the second aluminum wiring does not become different from the desired shape.

Next, an interlayer film 55 shown in FIG. 4B is formed so as to cover the second aluminum wiring. Interlayer film 55
Is formed, the previously opened cutting assistance hole 92 is filled back. Similarly to the above-described interlayer film 49, the interlayer film 55 includes the first USG layer 50, the SOG layer 52, and the second USG layer 5.
4 in this order.

That is, first, the first USG layer 50 is formed. The first USG layer 50 is formed by depositing USG by a CVD method or the like. Next, using the SOG method, the concave portions on the upper surface of the first USG layer 50 are filled,
An SOG layer 52 made of an insulator is formed. Next,
On this, the second USG layer 5 is formed. Thus, the interlayer film 55 having a flat upper surface can be obtained.

As in the case of the above-described interlayer film 49, since the cutting assisting holes 92 in the chip isolation region 34 are formed in fine dots, the first USG layer 5 formed thereon is formed.
The concave portion formed on the upper surface of 0 is also a fine dot. Therefore, the SOG layer 5 applied on the upper surface of the first USG layer 50
2 does not flow into the concave portion in a large amount.
Therefore, the flattening of the interlayer film 55 is not impaired as in the related art.

Next, RIE, which is an insulating layer etching step for making contact with the above-mentioned second aluminum wiring, is performed.
In the (reactive ion etching) step, as shown in FIG. 5A, the interlayer film 55 in the chip separation region 34 is removed in a dot-like manner, and a cutting assist hole 94 is formed. Etching is
The process is performed until the bottom of the cutting assisting hole 94 reaches the interlayer film 49.

The cutting auxiliary holes 94 are formed in the lower interlayer film 4.
9 is provided at a position that does not overlap with the cutting assisting hole 92 formed and backfilled. Therefore, when forming the upper cutting assist hole 94, the cutting assist hole 92 formed in the lower interlayer film 49 and backfilled is not removed again by etching. For this reason, the interlayer film 49 is not excessively etched as in the case where the buried backing hole 92 is etched again.

Thereafter, a third aluminum wiring (not shown) is formed on a predetermined portion of the die 32 (see FIG. 1). As in the case of the first aluminum wiring (described above), the cutting assisting holes 94 in the chip separation region 34 are formed in fine dots, so that the resist (FIG. (Not shown) rarely flows into the cutting assistance holes 94. For this reason, unlike the conventional case, the shape of the third aluminum wiring does not become different from the desired shape.

Next, as shown in FIG. 5B, a passivation film 56 is formed so as to cover the entire substrate. By forming the passivation film 56, the cutting assistance hole 94 opened previously is filled back. Passivation film 5
6 is PSG (phosphorus-silicate glass) by CVD or the like
And the like are deposited.

Next, RIE which is an insulating layer etching step for making contact with the third aluminum wiring is performed.
In the (reactive ion etching) step, as shown in FIG. 2, the passivation film 5 in the chip separation region 34 is formed.
6 is removed in the form of a dot to form a cutting assisting hole 96. The cutting assisting hole 96 is provided at a position overlapping with the cutting assisting hole 94 formed in the lower interlayer film 49 and backfilled. The etching is performed until the bottom of the hole reaches the interlayer film 49. Therefore, by this etching, the cutting auxiliary hole 94 buried in the previous step is dug again. That is, as a result, the cutting auxiliary holes 96 and the cutting auxiliary holes 94 are vertically continuous holes. Thus, the wafer 30 is formed.

Next, a chip cutting step (chip separation step) for cutting the die 32 from the formed wafer 30 (see FIG. 1) will be described. The procedure of the chip cutting step is the same as the procedure shown in FIGS. 8A and 8B. That is, the wafer 30 is attached to a plastic film (not shown) having a surface coated with an adhesive, and the attached wafer 30 is cut by a dicing saw (not shown).

Using a dicing saw having a width smaller than the width of the chip separation region 34 shown in FIG. 1, the wafer 30 is cut in the chip separation region 34. FIG. 2 shows a portion 36 of the chip separation region 34 of the wafer 30 which is removed by the dicing saw. When the wafer 30 is cut, even if cracks (cracks) or the like are generated near the portion 36 removed by the dicing saw, the progress of the generated cracks or the like is determined by the cutting assist holes 90, 92, 94, 9.
6 can be stopped. For this reason, the die 32 can be cut from the wafer 30 without damaging it.

In the above-described embodiment, as shown in FIG. 2, the passivation film 56 in the chip isolation region 34 is removed in a dot-like manner to form a cutting assisting hole 96. As shown in FIG. 6, the passivation film 56 in the chip separation region 34 may be entirely removed to form one cutting assist recess 98 covering the entire chip separation region 34.

In the above-described embodiment, the case where the plurality of separation assisting recesses are a plurality of cutting assisting holes (a plurality of point-like recesses) (wafer 30) has been described as an example.
As shown in (2), the plurality of separation assisting recesses may be a plurality of cutting assisting grooves 102 (a plurality of linear recesses) (wafer 100).

FIG. 7 shows the wafer 10 before the die 32 is cut out.
2 is a drawing showing a part of the plane configuration of FIG. The cross-sectional structure of the chip separation region 34 of the wafer 100 is substantially the same as FIG. 2 or FIG. Also, as shown in FIG.
At 00, a large number of dies 32 partitioned by chip separation areas 34 arranged vertically and horizontally are arranged. In the chip separation area 34, a plurality of linear concave portions (separation assisting concave portions) are provided. An auxiliary groove 102 is formed.

In FIG. 7, for each of the chip separation regions 34 arranged vertically and horizontally, the cutting assisting grooves 102 are provided.
Are arranged in three rows, but the number of rows of the cutting assistance grooves 102 is not limited to this. It is to be noted that, in many cases, the cutting assisting grooves 102 having a larger number of rows are actually arranged in the same manner as in the case of the above-described wafer 30 (see FIG. 1).

In each of the above embodiments, a semiconductor chip having four insulating layers has been described as an example, but the present invention is not limited to this. The present invention can be applied to a semiconductor chip having five or more insulating layers or a semiconductor chip having one to three insulating layers.

In each of the above embodiments, the case where a plurality of separation assisting concave portions are formed in all the insulating layers has been described as an example, but the present invention is not limited to this. For example, a configuration may be adopted in which the plurality of separation assisting concave portions are formed in every other layer among the plurality of insulating layers. Further, the plurality of separation assisting concave portions may be formed in only one specific layer among the plurality of insulating layers.

In each of the above-described embodiments, all of the separation assisting recesses of each layer in one semiconductor wafer are point-like recesses, and all the separation assisting recesses of each layer in one semiconductor wafer are linear recesses. However, the present invention is not limited to this. For example, in one semiconductor wafer, the separation assisting recess of a certain layer may be configured as a dot-shaped recess, and the separation assisting recess of another layer may be configured as a linear recess. Further, as the separation assisting concave portion of one layer, it is also possible to adopt a configuration in which a dot-shaped concave portion and a linear concave portion are mixed.
Further, if the shape is such that the flowable material does not easily flow, a separation assisting concave portion other than the point-shaped concave portion or the linear concave portion can be used.

In the above-described embodiment, the MOS
-The case where the present invention is applied to the FET has been described as an example,
The present invention is not limited to this. The present invention relates to transistors other than MOS-FET, IC, LS
I and the like can be generally applied to semiconductor chips.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of a planar configuration of a wafer 30 before cutting out a die 32 which is a semiconductor chip according to an embodiment of the present invention.

FIG. 2 is a drawing showing a cross section II-II of the wafer 30 shown in FIG.

FIGS. 3A and 3B are cross-sectional views illustrating a method of manufacturing a wafer 30. FIGS.

FIGS. 4A and 4B are cross-sectional views illustrating a method of manufacturing a wafer 30. FIGS.

FIGS. 5A and 5B are cross-sectional views for explaining a method of manufacturing a wafer 30. FIGS.

FIG. 6 shows a passivation film 5 in a chip separation region 34.
6 is a cross-sectional view showing an example in which 6 is entirely removed.

FIG. 7 is a view showing a part of a planar configuration of a wafer 100 according to another embodiment of the present invention.

8A and 8B are drawings (cross-sectional views) showing a state of a conventional operation of cutting a die from a silicon wafer.

FIG. 9 is a drawing (plan view) showing a state of a conventional die cutting operation from a silicon wafer.

FIGS. 10A, 10B, and 10C are cross-sectional views showing a part of a manufacturing process of a conventional silicon wafer.

[Explanation of symbols]

 34... Chip separation area 42... Interlayer film 44... First USG layer 46... SOG layer 90.・ Cutting auxiliary hole 94 ・ ・ ・ ・ ・ Cutting auxiliary hole 96 ・ ・ ・ ・ ・ Cutting auxiliary hole

Claims (6)

[Claims] 1. A semiconductor chip comprising: an insulating layer etching step of etching an insulating layer formed on a semiconductor wafer; and a chip separating step of separating a semiconductor chip from the semiconductor wafer in a predetermined chip separating region of the semiconductor wafer. In a manufacturing method, in at least one insulating layer etching step prior to a chip separating step, a plurality of separation assisting concave portions are formed by etching in the insulating layer in the chip separating region. Manufacturing method. 2. The method for manufacturing a semiconductor chip according to claim 1, wherein the plurality of separation assisting recesses are formed as a plurality of linear recesses. 3. The method of manufacturing a semiconductor chip according to claim 1, wherein said plurality of separation assisting recesses are a plurality of point-like recesses. 4. The method for manufacturing a semiconductor chip according to claim 1, wherein the plurality of separation assisting recesses are respectively formed in two or more insulating layers in two or more insulating layer etching steps. To do. 5. The method of manufacturing a semiconductor chip according to claim 4, wherein the plurality of separation assisting recesses are respectively formed in two insulating layers vertically contacting each other in the chip separation region.
A plurality of separation assisting recesses formed in each of the insulating layers are formed at positions that do not vertically overlap. 6. A semiconductor chip separated from a semiconductor wafer in a predetermined chip separation region of the semiconductor wafer, the semiconductor chip having one or more insulating layers formed in a predetermined shape by etching. A plurality of separation assisting recesses formed by etching in the insulating layer in the region.