JPH1166146A - Designing method for logic circuit and cad system for same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To design a path-transistor logic circuit with a minimum number of transistors and a minimum number of path stages by connecting the input terminals and control terminal of a multiplexer so that the 1st logic group of a logic expression including high-order variables is outputted from the output terminal of the multiplexer. SOLUTION: A given combination logic expression is converted to optimum form suitably mapped to the logic circuit, and primary mapping is performed to match a logic level. In the logic expression, a 1st logic group including 1st logic functions and at least one high-order variable shared by the 1st logic functions is specified and a multiplexer having input terminals, at least one control terminal and an output terminal is arranged in the logic circuit. Then the 1st logic functions and at least one high-order variable are inputted and the input terminals and control terminal of the multiplexer are so connected that the 1st logic group is outputted from the output terminal of the multiplexer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic circuit using a pass transistor, and more particularly, to a logic circuit having a combination of at least one pass transistor and at least one multi-input logic gate. Further, the present invention relates to a method of designing a logic circuit for performing a desired logic operation by using a small number of transistors and a small number of pass stages by taking advantage of pass transistors and a multi-input logic gate. Here, the number of pass stages indicates the number of stages of a pass transistor and a multi-input logic gate through which a signal passes in a logic circuit. The present invention further relates to a logic circuit using a pass transistor and capable of efficiently executing a logic operation, and a system using such a logic circuit. The present invention further relates to a method for efficiently executing a logical operation using a logic circuit including a pass transistor.

[0002]

2. Description of the Related Art It is known to use a so-called "pass transistor logic circuit" in order to reduce the number of elements and power consumption and improve the operation speed. The pass transistor logic circuit uses a pass transistor including a switching element. The conduction between the input terminal and the output terminal of the switching element is turned on or off according to the voltage of the control terminal. Each pass transistor is realized by connecting switching elements such that whether or not a logic signal applied to an input terminal is transmitted to an output terminal is determined by a conduction or non-conduction state of each switching element. Generally, a plurality of pass transistors are connected in series and / or in parallel to configure a pass transistor logic circuit that performs a desired logical operation. As the switching element, for example, a MOS transistor is used. In this case, the gate, source, and drain of each MOS transistor correspond to a control terminal, an input terminal, and an output terminal, respectively. An n-channel or p-channel MOS transistor or a combination of n-channel and p-channel MOS transistors is used as a pass transistor. n-
Pass transistors using a combination of channel and p-channel MOS transistors are often referred to as "transmission gates" or "transfer gates."

It is also known to form a logic circuit using a combination of one or more transfer gates and logic gates such as an inverter, a multi-input NOR gate, and a multi-input NAND gate.

The applicant of the present invention has proposed, in Japanese Patent Application Laid-Open No. 9-93118, a composite pass transistor logic circuit composed of a combination of a plurality of pass transistor logic circuits (pass transistor logic operation system) and a multi-input logic circuit.

However, a practical technique for designing an integrated circuit in which various functions required by various users are constituted by using a logic circuit including a pass transistor has not been established. For example, Japanese Patent Application Laid-Open No. Hei 1-216
In the technology disclosed in 622, a logic circuit composed of a combination of a transfer gate and a logic gate is created as a logic cell, and a desired LSI is designed by the combination of the logic cells. However, while some simple logic circuits are disclosed, such as an exclusive OR, an exclusive NOR, and a full adder, specific techniques for designing various logic circuits required for actual applications are not described. Was not disclosed.

One of the known techniques for designing a pass transistor logic circuit is to use a BDD (binary decision diagram). For example, variables a, b, c
The following logical expression (1) including the following can be expressed in BDD as shown in FIG.

[0007]

(Equation 1)

The BDD can be mapped to a pass transistor logic circuit as shown in FIG. Here, the process of replacing a logical expression with a corresponding logical circuit is referred to as mapping. In the logical expression (1),

[Outside 1] Indicates an exclusive OR operation for convenience.

When the same logical expression is represented by BDD, the size of the graph changes depending on the order of variables included in the same logical expression. For example, the logic circuit in FIG. 3 and the logic circuit in FIG. 5 perform equivalent logical operations, but differ in the order of variables handled by the BDD. The logic circuit of FIG. 3 is represented by a BDD graph as shown in FIG. 4, and the logic circuit of FIG.
This can be expressed as shown in FIG. In the logic circuit of FIG. 3 and the corresponding BDD graph of FIG. 4, the order of the variables is optimal. In contrast, the logic circuit of FIG. 5 and the corresponding BDD graph of FIG. 6 have the worst order of variables.

If the number of inputs of the logical operation, that is, the number of variables of the logical expression is n, the order of the variables is theoretically 2 ^{n at} maximum. It is practically impossible to select an optimum order from such a large number of orders that variables can take, since the process of selecting the optimum order takes a very long time. On the other hand, if the processing time required to determine the order of the variables is limited, the obtained order of the variables is inadequate, greatly deviating from the optimal order, and an inappropriate BDD
There is a risk that the number of gates forming the logic circuit mapped from the graph may increase unrealistically.

Various methods are known for determining the order of variables in BDD. For example, 2J of a collection of papers at the 42nd Information Processing Society of Japan (early 1991) National Convention
In -5, “Ordering Method of Variables Focusing on“ Width ”of Common Binary Decision Diagram” (Shinichi Minato) (hereinafter referred to as a first conventional example), BDD is defined as a k-th input variable and (k + 1)
The number of edges passing through the cross section when cut into two with the second input variable is defined as “width”. In the process of determining variables, when input variables are selected in order from top to bottom, among input variables remaining as candidates, the one that minimizes this “width” is selected. In this method, assuming that the number of input variables is n and the number of nodes of the BDD is G, the order of input variables can be determined in a calculation time of about O (n ² · G). Here, O (n ² · G) is the time required for n ² · G calculations.

Next, IEEE 0-7803-3036
-6/95 “Multi-Level Pass-Transistor Logic fo
r Low-Power ULSIs ”(Kazuo Yano et al.) (hereinafter referred to as a second conventional example) first extracts a portion sharing the same logical function from the original BDD, and then extracts the same number of“ Replace with a new BDD with "leaves". Then, create logic about the control input of the replaced BDD node,
Adjust to match the original logic.

[0013]

However, in the above-mentioned first conventional example, AND and / or OR are required due to the structure of the BDD.
Since the logic circuits are connected in series by pass transistors, the number of pass transistors in the logic circuit increases. Further, in order to determine the order of input variables within a practical calculation time, it is necessary to limit the number of input variables to tens and the number of nodes to tens of thousands. Furthermore, the solution of the order of the input variables obtained by the above calculation is still far from the optimal solution.

Next, in the second conventional example, although the logical expression can be mapped to a pass transistor logic circuit having a small number of pass transistor stages, it is necessary to provide a buffer at the control input of each pass transistor. Not reduced. In addition, since the degree of freedom in the process of replacing the part having the common logic with the new BDD is too large,
It is not suitable for use in designing a large-scale integrated circuit with a CAD (computer-aided design) system.

Further, in each of the first and second conventional examples, the desired logic circuit is constituted by using a conventional pass transistor logic circuit including a multi-stage multiplexer constituted by pass transistors. This makes it unsuitable for use in designing complex pass transistor logic circuits that include both pass transistors and one or more multi-input logic gates. That is, it has not been possible to efficiently design a complex pass transistor logic circuit while taking advantage of it. Therefore, in the complex pass transistor logic circuit mapped after optimizing the logic expression in the first or second conventional example, the number of transistors required for the logic circuit may increase or the number of pass transistors may increase. There is.

The present invention has been made to solve the above-mentioned conventional problems, and has as its object to provide a design method and a CAD system for designing a pass transistor logic circuit with a minimum number of transistors and a minimum number of pass stages. I do.

The present invention also provides a pass transistor logic circuit in which various logic operations are efficiently realized, an electronic system using such a logic circuit, and a method for efficiently executing various logic operations. The purpose is to provide.

According to one aspect of the present invention, a method of mapping a logical expression representing a logic to be implemented by a logical circuit to a specific type of logical circuit in which pass transistors are effectively used, and such a method. A method for designing a logic circuit including a mapping process is provided. Further, a CAD system is provided for use in performing such a method.

According to another aspect of the present invention, there is provided a method of designing a logic circuit including a process of converting a logical expression into an optimal form so that the logical expression can be easily mapped to a logical circuit in which pass transistors are effectively used. Given.

According to still another aspect of the present invention, a method of mapping a combinational logic expression to a logic circuit comprising a multiplexer combining pass transistors and an inverting logic gate so that the logic circuit comprises a small number of transistors. Is provided. In addition, a CAD system for use in implementing such a design method is provided.

In accordance with yet another aspect of the present invention, a product term including various numbers of logic functions is converted into a logic circuit including a combination of one or more multi-input logic gates and an appropriate number of multiplexers.
A method is provided for mapping to a small number of transistors and pass stages. Further, a CAD system for use in performing such a method is also provided. Further, there is provided a logic circuit for performing a logical operation represented by a logical expression including a product term having various numbers of logical functions, the logic circuit including a small number of transistors and the number of pass stages. Further, an electronic system using such a logic circuit is provided. Furthermore, logical operations represented by logical expressions involving product terms having various numbers of logical functions are:
A method is provided for performing efficiently.

According to another aspect of the present invention, a logic expression including a logic group having upper variables is used in a logic circuit including a combination of one or more multi-input logic gates and one or more multiplexers. A mapping method is provided so that the number of stages is equal to the number of stages. Here, upper variables are positive literals (x) and negative literals in a plurality of logical functions.

[Outside 2] Are also called complementary variables or dimorphic variables. In addition, a CAD system for use in performing such a method is provided. Further, one or more multi-input logic gates and one or more multi-input logic gates for performing a logical operation represented by a logical expression including a logical group having an upper variable.
In the logic circuit having the above combination of multiplexers, a logic circuit including a small number of transistors and the number of pass stages is provided. Further, an electronic system using such a logic circuit is provided. Further, a method is provided for efficiently executing a logical operation represented by a logical expression including a logical group having a higher variable using a logical circuit having a combination of one or more multi-input logical gates and one or more multiplexers. Can be

According to another aspect of the present invention, a logical expression including a logical group having an upper variable includes a combination of two types of multi-input logical gates and one or more multiplexers.
A method is provided for mapping to a logic circuit including a small number of transistors and stages. In addition, a CAD system for use in performing such a method is provided. Furthermore, a logic circuit having a combination of two types of multi-input logic gates and one or more multiplexers for executing a logic operation represented by a logic expression including a logic group having a higher variable, the logic circuit having a small number of transistors and paths A logic circuit including a number of stages is provided. Further, an electronic system using such a logic circuit is provided. Further, there is provided a method for efficiently executing a logical operation represented by a logical expression including a logical group having upper variables using a logical circuit having a combination of two types of multi-input logical gates and one or more multiplexers. Is done.

[0024]

According to one aspect of the present invention, there is provided a method for designing a logic circuit for mapping a logic expression, comprising: a first plurality of logic functions in the logic expression;
Identifying a first logic group that includes at least one upper variable shared by the first plurality of logic functions; and having a plurality of input terminals, at least one control terminal, and an output terminal in the logic circuit. Arranging a multiplexer, and inputting the first plurality of logic functions and the at least one upper variable, such that a first logic group is output from an output terminal of the multiplexer; And a control method for designing a logic circuit having a logic expression mapping step including a step of connecting a logic terminal to a control terminal.

Preferably, the specific step further specifies a second plurality of logical functions in the logical expression and a common variable shared by the second plurality of logical functions,
The mapping step further comprises: arranging a multi-input logic gate having a plurality of input terminals and output terminals in a logic circuit; and inputting a sum of the common variable and the second plurality of logic functions, Connect the input terminals of the multi-input logic gate such that the output of the logic group is output from the output terminal of the multi-input logic gate.

Furthermore, there is provided a CAD system for designing a logic circuit for mapping a logic expression, wherein
Means for specifying a first logical group including a first plurality of logical functions and at least one upper variable shared by the first plurality of logical functions; and means for mapping a logical expression. Means for arranging a multiplexer having a plurality of input terminals, at least one control terminal and an output terminal in a logic circuit, and inputting the first plurality of logic functions and the at least one upper variable, A CAD system is provided that includes means for connecting an input terminal and a control terminal of a multiplexer such that one logical group is output from an output terminal of the multiplexer.

Further, there is provided a method for designing a logic circuit for mapping a logic expression, comprising: arranging a multiplexer having a plurality of input terminals, at least one control terminal, and an output terminal in the logic circuit; Inputting a plurality of logic functions and at least one upper variable,
And a first logical group of logical expressions comprising at least one upper variable shared by the first plurality of logical functions is output from an output terminal of the multiplexer. A design method for connecting a terminal and a control terminal is provided.

In order to obtain a high-performance logic circuit that can operate at high speed with low power consumption with a small number of transistors, a logic group of a type suitable for mapping by using pass transistors in a logical expression includes a pass transistor. It is desirable to map a given logical expression to a logic circuit, as mapped using.

For example, including the variable a in the complementary form,
A logical expression in which one product term contains variable a in non-inverted (positive logic) form and the other product term is the sum of product terms containing variable a in inverted (negative logic) form

[Outside 3] (Where C and E are arbitrary logical functions,... Represents an AND operation, and + represents an OR operation), the logical group is composed of two paths whose output terminals are connected to each other. It is efficiently mapped to a logic circuit having a two-input one-stage multiplexer (hereinafter, referred to as a “unit multiplexer”) constituted by transistors. Specifically, a variable a (a signal corresponding to the variable a)
Are input to the control terminal of the multiplexer, and the logical functions C and E (signals corresponding to the logical functions C and E) sharing the variable a are input to the two input terminals of the multiplexer, and as a result, the logical group ( Signal corresponding to the logical group) is output from the output terminal of the multiplexer. Here, the above variables (complementary variables or dimorphic variables) are referred to as “upper variables”. When the logic group including the upper variable is mapped to the multiplexer constituted by the pass transistors as described above, the total number of transistors used and the power consumption are mapped to the same logic group using, for example, a multi-input logic gate. It is reduced as compared with the case of performing.

In the above formula, lowercase letters such as a represent variables, and uppercase letters such as C and E represent logic functions. The logical function may be a simple function including only a single variable or a complex function represented by a product or a sum of many variables. Further, a term represented by a product of a plurality of variables or logic functions such as a · C and a bar · E in the above logical expression is referred to as a “product term”. Here, "bar" represents negation, and "a bar" represents a negation literal of a. If C and E are simple variables, the above product term will be a simple product term with multiple variables. Conversely, all elements of the product term may be logical functions (rather than simple variables).

As another example, the sum of the product terms each including the two variables complementarily,

[Outside 4] (Where C, D, E and F are any logical functions), i.e., any of the four possible combinations of two variables where each variable is in either positive or negative logic form Consider what each product term contains. In this case, the logical group includes two unit multiplexers in which the output terminals of the two first-stage unit multiplexers are respectively connected to the input terminals of the second-stage unit multiplexer.
A stage multiplexer can be used to efficiently map to a logic circuit. In this example, variables a and b in the logical expression are
These are upper variables, and these variables are input to the control terminal of the multiplexer. In detail, logic functions C, D, E and F are input to four input terminals of two first-stage unit multiplexers each having two input terminals, and a variable b is input to two first-stage unit multiplexers. Mapping is performed such that the variable a is input to each control terminal and the variable a is input to the control terminal of the unit multiplexer in the second stage. An upper variable of a logical group that can be efficiently mapped using two or more stages of multiplexers as in the above example is referred to as a “multiple upper variable”. As can be understood from the above description, a logic group including multiple high-order variables is efficiently mapped to a logic circuit using a multi-stage multiplexer including a small number of transistors and the number of stages.

[0032]

[Outside 5] The logical group represented by the logical expression having the sum of three combinations of the four possible combinations of positive and negative logical forms of two variables is efficiently mapped using a two-stage multiplexer. Is done. Again,
Variables a and b act as multiple upper variables.

Further, a logical expression including three or more multiple upper variables is mapped using three or more stages of multiplexers. However, in practice, the number of pass transistors that can be connected in series is limited. Therefore, the number of stages of the multiplexer is limited.

In the case of a logic circuit designed using both a pass transistor and a multi-input logic gate, a part of a logical expression realized by the logic circuit in a specific format suitable for mapping using the multi-input logic gate Preferably, a multiple-input logic gate is used to map
For example, a simple NAND logic containing multiple variables is preferably mapped using a multi-input logic gate.
Variables commonly included in a plurality of product terms (hereinafter, such variables are referred to as “common variables”) are mapped using a common multi-input logic gate. It is preferable to when the product terms are individually mapped. By using a common multi-input logic gate, divergence of AND or NAND terms is prevented. As a result, the logic is implemented with a small number of transistors. Further, since the common variables are input in parallel to the multi-input logic gate, the number of pass stages of the logic circuit is also reduced.

For example, in the case of a logical group of the form represented by a logical expression a.C + a.D = a. (C + D) including a product term commonly including the variable a, the logical functions C and D share the common variable a. doing. In this case, the variable a
Is input to one of the input terminals of the AND gate, and the sum of the logical functions C and D obtained by appropriately mapping the logical functions C and D is input to the other input terminal of the AND gate. Groups are mapped efficiently. When the logical level matching described later is performed, N
An AND gate or a NOR gate is used as a multi-input logic gate for mapping logic including a common variable.

More specifically, for example, a.b.c.
If d, a, b, c, e, a, b, c, f and a, b, g are given as product terms, the grouped product terms a, b, c, (d + e ) Variables a, b,
c and the grouped product terms b bar · (a bar · c
The variable b bar in the bar f + ag) is a common variable.
In this case, a, b, c and (d + e) are input to the input terminal of one multi-input logic gate, and b bar and (a bar, c bar, f + a, g) are input to another multi-input logic gate. Input terminal.

Further, when designing a logic circuit including a pass transistor and a multi-input logic gate, it is more preferable to consider the above two points at the same time. For example, it is preferable to map a logic group including one or more upper variables using a multiplexer including a combination of pass transistors, and map a logic group including one or more common variables using a multi-input logic gate.

Actually, the above-mentioned mapping processing is executed by the CPU.
And in the process of designing a logic circuit using a CAD system including a storage device. In actual operation using the CAD system, the mapping process is executed by the CPU, and electronic information corresponding to the circuit is generated and stored in an appropriate location in the storage device. The above information is finally converted into mask data after various processes, and a mask is created according to the mask data. By using these masks, an actual circuit is realized in the form of a semiconductor integrated circuit. In a design process using a CAD system, generally, before mapping a logic group to a circuit using a multiplexer and a multi-input logic gate, a logic group including an upper variable in a logic expression to be realized by the logic circuit, The logical group containing the variable is found (identified). This discovery (identification) is performed in various ways. For example, a process of optimizing a logical expression, which will be described in detail later, also includes a process of finding a logical group including an upper variable and a logical group including a common variable.

According to another aspect of the present invention, there is provided a method of designing a logic circuit for mapping a logic expression,
(A) selecting at least a part of a logical expression including a plurality of product terms each including a plurality of variables; and (b) at least one complementary to at least two of the product terms.
(C) grouping the at least two product terms with the upper variable and including at least one upper variable and at least two logic functions sharing the upper variable. A first aspect of the present invention provides a design method including: optimizing a logical expression including at least one cycle in a first process including forming a logical group; and mapping the optimized logical expression to a logic circuit.

Preferably, the optimizing step further includes the step of: (a) selecting at least a part of a logical expression including a plurality of product terms each including a plurality of variables; and (b) at least one of the plurality of product terms. Identifying at least one set of common variables that are commonly included in the two; and
(C) grouping the at least two product terms to form a second logical group including the at least one common variable and a plurality of second logical functions sharing the common variable. The process includes at least one cycle.

Further, there is provided a CAD system for designing a logic circuit for mapping a logic expression, wherein (a)
Selecting at least a part of a logical expression including a plurality of product terms each including a plurality of variables; (b) identifying at least one upper-order variable complementary to at least two of the product terms; And (c) grouping the at least two product terms with the upper variable to form a logical group including at least one upper variable and at least two logical functions sharing the upper variable. 1 at least one cycle,
A CAD system is provided that includes a logic expression optimizing unit and a unit that maps the optimized logical expression to a logic circuit.

Further, there is provided a method of designing a logic circuit for mapping a logic expression, wherein (a) selecting at least a part of the logic expression including a plurality of product terms each including a plurality of variables, (b) ) Identifying at least one set of common variables that are commonly included in at least two of the plurality of product terms; and (c) grouping the at least two product terms to form the common variable and the common variable. Optimizing a logical expression including at least one cycle of forming a logical group including a plurality of logical functions sharing variables, and mapping the optimized logical expression to a logical circuit including a multiplexer. Are provided.

Further, there is provided a CAD system for designing a logic circuit for mapping a logic expression, wherein (a)
Selecting at least a part of a logical expression including a plurality of product terms each including a plurality of variables, and (b) identifying at least one set of common variables commonly included in at least two of the plurality of product terms. And at least one cycle comprising: (c) grouping the at least two product terms to form a logical group including the common variable and a plurality of logical functions sharing the common variable. A CAD system is provided that includes a logical expression optimizing unit and a unit that maps the optimized logical expression to a logical circuit including a multiplexer.

In order to design a logic circuit in which pass transistors and multiple-input logic gates are effectively used, before mapping, a given logic expression representing a logic operation performed by the logic circuit is optimized. It is desirable that the logic circuit be effectively and easily mapped in a particular manner. This optimization is performed by a CAD system.

The present invention provides a method for easily mapping a logical expression to a logical circuit in which a multiplexer is effectively used.
A technique for creating a logical group including one or more upper variables is provided. The technique preferably creates logical groups that include multiple superior variables, if possible. For this purpose, we introduce the concept of the number of types of logical combinations of variables in product terms included in logical expressions.

For example, the product terms a · b · c, a · b bar ·
In the case of a logical expression including d, a-bar-b-c and a-bar-b-bar-f, two variables a and b act as multiple higher-order variables. In this equation, the logical combinations of the variables related to the set of the variables a and b are ab, abbar, abarb, and abarbbar. Therefore, in this example, the number of types of logical combinations of variables related to the pair of variables a and b is four. The number of types of combinations between any one of the variables a and b and any one of the variables c, d, e, and f is 1. Therefore, each of the variables c, d, e, and f is No.
In the example of a logical expression including product terms a, b, c, a, b, b, d, and a, bar, b, in which two variables a and b act as multiple upper variables, the logical combination for variables a and b is a
B, a · b bar, and a bar · b. Therefore, the number of logical combination types for the set of variables a and b is 3.

As can be understood from the above discussion, the variables included in the set of variables having a larger number of types of logical combinations have the possibility of being upper variables. Therefore, the one included in the set of one or more variables having the maximum number of logical combination types
The above variables are the first candidates for specifying the upper variables. Further, one or more variables included in the set of one or more variables having the second largest number of combination types are the second candidates.

The number of logical combination types, when combined for a particular variable, may change depending on the particular variable under consideration. For example, a, b, c, d, a, b, c, e,
When a bar, b bar, c bar, f, and a, b bar, g are given as product terms, if all variables are treated equally, the set of three variables a, b, and c becomes "a, b, c "and" a bar, b bar, c bar ". That is, the number of logical combination types is two. On the other hand, the logical combination of the same set of variables regarding the variable a is “a, b, c”, “a bar,
b bar, c bar "and" a, b bar ", that is, the number of logical combination types is 3. Similarly, the number of combination types for the variable b is 3. On the other hand, the combination for the variable c is" a ". , B, c "and" a bar, b bar, c bar ", that is, the number of combination types is 2. When logic is combined with respect to a specific variable, a combination that does not include one of the variables in the set is included. Is also considered an allowed combination as long as the combination includes the variable under consideration.

Therefore, when the number of combination types is determined by combining a specific set of variables with respect to a specific variable, the number of logical combination types may change according to the variable under consideration. When a variable included in a set having a larger combination type number is selected as a candidate for a higher-order variable, it is preferable that selection be performed based on the combination type number of each variable.

Therefore, in the process of grouping the above four product terms, if a and b are selected as upper variables, the logical group becomes

[Outside 6] Becomes This logical group is composed of multiple upper variables a and b and three logical functions cd, d + c,
Including e, g and c-bar-f. Therefore, this logic group is efficiently mapped to the logic circuit using the two-stage multiplexer.

Such optimization is performed by changing the variables in the product term by 1
A logic expression given to be realized by a logic circuit, including a step of specifying the upper variable and a step of grouping two or more product terms by the selected upper variable to form a logical group including the upper variable Is performed on all or a specific part. Further, the optimization process can be repeatedly executed in a plurality of cycles in order to increase the degree of optimization. In the second and subsequent optimization cycles, a specific part is selected and optimized according to the result of the preceding optimization process.

If the specification is performed only by determining whether the variable is included in a set of variables having a larger number of combinations, the number of variables having the same value may be too large. In such a case, the number of times included in a set of variables having a large number of combination types can be adopted as a criterion for specifying a variable as a higher-order variable. When a given logical expression is optimized by repeatedly performing a process of creating a logical group including a higher-order variable, adoption of such a selection criterion increases the possibility of achieving a higher-level optimization process. .

In the combination type method according to the embodiment of the present invention, an upper variable is selected based on the number of times included in a set of variables having a large number of combination types.

Further, the present invention provides a method for easily mapping a logical expression to a circuit by effectively using a multi-input logical gate.
A technique for creating a logical group including common variables is provided.

It is easy to find the common variables contained in a particular set of product terms. For example, it is found by calculating the AND of the product terms. However, deciding which product terms should be grouped together requires careful consideration. For example, when a logical expression includes three or more product terms, common variables may differ depending on which product terms are grouped. For example, in the case of the logical expression a · b · c · d + a · b · c · e + a · d · f · g, when the first and second product terms are grouped,
The variables a, b, and c are common variables. On the other hand, when the first and third product terms are grouped, the variables a and d become common variables. When the second and third product terms are grouped, the variable a becomes a common variable. When the first, second, and third product terms are grouped, the variable a becomes a common variable. In general, when the same number of product terms are grouped in different ways, it is desirable to employ a group that includes more common variables. On the other hand, when the product terms are grouped in different ways and each group has the same number of common variables, it is usually desirable to select the group that contains a larger number of product terms. However, in general, the number of common variables decreases as the number of product terms grouped together increases.

In the embodiment of the present invention, two techniques for optimizing a logical expression by creating a logical group including one or more common variables, namely, a bottom-up common variable method and a top-down common variable method, are used. Provided.

In the bottom-up common variable method, the product terms are first grouped into groups each containing two product terms so that the group contains a larger number of common variables. Then, the common variables specified in the first cycle are regarded as product terms, and the common variables included in each product term are specified and further grouped. Therefore, in this technique, when the processing is repeated, the number of product terms grouped increases.

On the other hand, in the top-down common variable method, the product terms are first grouped into 2 ^v groups. Here, v is the allowable number of pass transistors used in the logic circuit. For example, if v = 2 and there are 32 product terms, a common variable is specified for a set of 8 product terms, and these product terms are grouped. In this technique, therefore, common variables between a larger number of product terms are first identified. Then, within each group, the product terms of each group are further grouped into 2 ^v groups by specifying more common variables from the reduced product terms.
Therefore, in this technique, as the process is repeated,
The number of common variables increases.

For example, a logical expression

[Outside 7] , The first and second product terms are grouped together and the third and fourth product terms are grouped together such that the group has common variables a, b, c and b bar, ceremony,

[Outside 8] Is converted to In the first logical group, the logical functions d and e, each being a single variable, are the common variables a, b
And c. On the other hand, in the second logical group, the logical functions a bar, c bar, f and a, g share the common variable b bar. Each of these two logic groups is efficiently mapped to a logic circuit in which multiple-input logic gates are advantageously used.

Processing for creating a logical group including upper variables,
Alternatively, it is also possible to execute only one of the processes for creating a logical group including a common variable. However, it is more desirable to perform both processes to obtain more benefits. When these two techniques are properly combined with each other, the logical expressions are optimized in a more desirable manner, and the advantages of both techniques are achieved. That is, it is possible to improve the operation speed of the circuit by reducing the total number of transistors used in the logic circuit and reducing the number of pass stages. The grouping of product terms into logical groups that include superior variables can be performed in various ways, and the grouping of product terms into logical groups that include common variables can also be performed in various ways. These various processes can be combined in various orders.

In the common variable / combination type method according to one embodiment of the present invention, the above-described common variable method and combination type method are combined. In this technique, a logical group including common variables is first created according to the common variable method. Next, the common variable specified in the above grouping process is regarded as a product term, and a combination type method is executed on these product terms so as to form a logical group including the upper variables. In the present technology in which the common variable method and the combination type method are combined, the product terms are first grouped in a form that can prevent the divergence of the common variables, and then the upper variables are specified. This makes it possible to effectively use both the multi-input logic gate and the multiplexer.

Alternatively, grouping by the combination type method is first executed, and then the logical functions in the obtained group are further grouped according to the common variable method. This technique, hereinafter referred to as the combination type / common variable method, is also useful for optimization. This technique is further divided into a combination type / bottom-up common variable method and a combination type / top-down common variable method depending on whether the common variable method is executed bottom-up or top-down.

It is also preferable to alternately execute the combination type method and the common variable method, for example, once. The logic expression optimized by this method is mapped to a logic circuit in which a multiplexer of a specific number of stages and a multi-input logic gate are alternately arranged, and the two are effectively combined.

According to another aspect of the present invention, there is provided a method for mapping a combinational logic expression to a logic circuit, comprising: dividing the logic circuit into at least three consecutive positive logic, negative logic, and positive logic regions; A first non-inverting logic gate having at least one input terminal and an output terminal is disposed on an input side of the negative logic region; a multiplexer having an input terminal, at least one control terminal and an output terminal is disposed in the negative logic region; Arranging a second non-inverting logic gate having at least one input terminal and an output terminal on the output side of the negative logic region; and inputting a non-inverting output signal from an output terminal of the first non-inverting logic gate. Or connecting the input terminals of the multiplexer to directly input an input signal; and outputting the output signal from the first non-inverting logic gate and the second By inverting the at least one input signal is input to the at least one input terminal of the inverting logic gate, the mapping method comprising the steps of: aligning the logic level of the logic circuit, is provided.

Preferably, the method further comprises the step of connecting one of the at least one input terminal of the second non-inverting logic gate to:
The output signal from the output terminal of the multiplexer is connected so as to be input non-inverted, and the inversion of the input signal to the second non-inverted logic gate includes the inversion of the direct input signal input to the input terminal of the multiplexer. And so on.

Further, there is provided a CAD system for mapping a combinational logic expression to a logic circuit, comprising: means for dividing the logic circuit into at least three continuous positive logic, negative logic, and positive logic areas; and at least one input terminal. A first non-inverting logic gate having an input terminal, an output terminal, and a multiplexer having an input terminal, at least one control terminal, and an output terminal disposed in the negative logic region; Means for arranging a second non-inverting logic gate having an output terminal on the output side of the negative logic area;
Means for inputting the output signal from the output terminal of the first multi-input logic gate in a non-inverted manner, or connecting the input terminal of the multiplexer so as to directly input the input signal;
And an output signal from the non-inverting logic gate of the first non-inverting logic gate and at least one input terminal of the second non-inverting logic gate,
Means for matching a logic level in the logic circuit by inverting at least one input signal.
A system is provided.

In the case of a logic circuit including only pass transistors, inversion of the logic level does not occur. Therefore, in this case, the given logical expression can be mapped to the logical circuit without considering the inversion of the logical level. However, in a pass transistor logic circuit, as a signal passes through the pass transistor, the logic amplitude is attenuated, and this attenuation limits the number of pass transistors connected in series. As a result, in order to recover the logic amplitude, it is necessary to insert a circuit element such as an inverter for every predetermined number of stages and to recover the logic amplitude attenuated by the pass transistor to the original level. Since the inverter causes the inversion of the logic level, it is necessary to perform the mapping in consideration of the inversion of the logic level. In order to recover the attenuation of the logic amplitude, a circuit element such as a buffer which does not cause the inversion of the logic level can be employed. However, the use of buffers increases the total number of transistors, so inverters are preferred. If the logic circuit is composed of pass transistors and one or more multi-input logic gates, the attenuation of the logic amplitude is restored by the multi-input logic gate. Further, in this case, the NAND for inverting the signal
Alternatively, a multi-input logic gate such as a NOR gate is preferable to a logic that does not cause inversion of a logic level such as an AND or OR gate from the viewpoint of reducing the total number of transistors. Therefore, the mapping is performed in consideration of the inversion of the logic level.

One technique for performing mapping in consideration of logic level inversion is to perform mapping without considering logic level inversion (primary mapping), and then to match logic levels (logic level matching). That is. In the primary mapping, the given logical expression is
The mapping is performed using a circuit element that does not cause inversion of the logic level, such as a buffer, an AND gate, or an OR gate (hereinafter, such a type of element is referred to as a “non-inversion logic gate”). The logic level is adjusted after at least the main part of the given logic expression forms a mapped logic circuit. In this logic level matching, a non-inverted logic gate is a circuit element that causes a logic level inversion, such as an inverter, a NAND gate, or a NOR gate (hereinafter, such an element is referred to as an “inverted logic gate”). Is replaced by In the primary mapping process, since the inverted logic gate is not used, it is not necessary to consider the inversion of the logic level. Therefore, the given logical expression is mapped in a short time by simple processing. Thereafter, the non-inverted logic gate is replaced with an inverted logic gate with logic level matching, so that the final logic circuit is realized with a small number of transistors.

In the primary mapping, when the output of the non-inverting logic gate is connected to the input terminal of the multiplexer, the connection is made non-inverting. That is, the connection is made without passing through an inverted logic gate such as an inverter. Similarly, when the output of the multiplexer is connected to the input terminal of the non-inverting logic gate, the connection is made so that inversion of the logic level does not occur. In addition to the signal from the output terminal of the non-inverting logic gate, other input signals such as variables and constants are input to the input terminal of the multiplexer without passing through the non-inverting logic gate. here,
Such a signal is called a "direct input signal".

In the logic level matching, the logic circuit obtained by the primary mapping is divided at the non-inverting logic gate, and the positive logic area and the negative logic area are formed alternately. This process involves first forming a positive logic region and a negative logic region alternately, then placing a non-inverting logic gate between the adjacent positive and negative logic regions and placing a multiplexer in each of the positive and negative logic regions. This may be done by arranging and mapping a given logical expression into it. In the simplest case, for example, three consecutive positive logic, negative logic and positive logic regions are formed, then non-inverting logic gates are placed on the input and output sides of the negative logic region, and the multiplexer is placed in the negative logic region. Placed in Further, the signal output from the non-inverting logic gate arranged on the input side of the negative logic area is inverted, and the signal input to the non-inverting logic gate arranged on the output side of the negative logic area is inverted.

Here, the processing of the "inverted signal" refers to the processing executed on the CAD system, and does not refer to the processing of actually inserting an inverter in the circuit. Thus, the non-inverted logic gate is replaced by the inverted logic gate. The above process is equivalent to a process in which an inverter is temporarily inserted into a circuit, and then each set of non-inverting logic gates and one or more inverters is replaced by an equivalent inversion logic gate containing fewer transistors. is there. Specifically, the AND and OR gates on the input side of the negative logic area are replaced with NAND and NOR gates, respectively, and the AND and OR gates on the output side of the negative logic area are replaced with zero AND gate (= NOR gate) and zero OR gate. (= NAND gate). The input and output buffers are all replaced by inverters. Further, a signal directly input to the input terminal of the multiplexer in the negative logic region is also inverted. Therefore, these signals are transmitted to the input terminal of the logic gate on the output side of the negative logic area via the multiplexer. As a result, the signal transmitted through the multiplexer and input to the logic gate on the output side of the negative logic area is also inverted.

In practice, when a given logic function is directly mapped to a logic circuit, the resulting logic circuit has high efficiency and high performance (small number of transistors, low power consumption, and high operation speed). Not always achieved. In order to avoid such problems, it is desirable to optimize a given logical expression before mapping so that the logical expression is mapped to the logic circuit very efficiently. That is,
As shown in FIG. 7, it is desirable to design a logic circuit as follows. First, in step S12 of FIG. 7, a given logical expression is optimized. Next, in step S14,
The optimized logical expression is primarily mapped to a logical circuit.
Finally, in step S16, the logic level is adjusted.

The primary mapping process can be executed such that the mapping is performed from the lowest group to the highest group in the logical expression or from the highest group to the lowest group. . here,
The “top group” refers to a group having the strongest influence on the value of the logical expression, and the “bottom group” refers to a group having the weakest influence. The highest group is mapped closest to the output of the logic circuit, and the lowest group is mapped closest to the input of the logic circuit. This means that the mapping is performed from the input side of the logic circuit to the output side or from the output side to the input side. In order to perform mapping in such an organized order, it is necessary that the logical expression to be mapped has a hierarchical structure at least at some point. For example, as will be described in detail later, in the combination type method, the common variable method, and the common variable / combination type method, a product term in a given logical expression is formed into a logical group including a high-order variable. Either or both of the processing of grouping the product terms in the logical expression and the processing of grouping the product terms in the logical expression so as to form a logical group including a common variable are repeatedly performed, whereby the logical expression has a hierarchical structure. Optimized to have

Another method of mapping a logical expression taking into account the inversion of the logic level in the inverting logic gate is as follows:
This is a method in which logic level matching is performed simultaneously during the mapping process, taking into account the inversion of the logic level from the beginning of the mapping process. An advantage of this method is that a logic circuit including inverted logic gates is formed with a smaller number of processing steps than a method in which logic level matching is performed after the primary mapping process.

Also in this case, the mapping process is the same as the case where the logical level matching is performed after the primary mapping, except that the logical level matching is performed simultaneously.

More specifically, the circuit is divided by logic gates such that positive logic areas and negative logic areas are alternately arranged, and inverted logic gates are arranged at boundaries between the respective positive logic areas and negative logic areas. For example, when an AND gate is needed to map a logic group containing a common variable at the input side of the negative logic area, a NAND gate is placed there instead of the AND gate and the output signal is inverted. On the other hand, when an AND gate is required on the output side of the negative logic area, the AND gate is provided there.
Zero AND gate (= NOR gate) instead of gate
Place. When an OR gate is required on the input side of the negative logic area, a NOR gate is employed instead of the OR gate. When an OR gate is required at the output of the negative logic area,
There, a NAND gate is arranged instead of the OR gate. When the input signal is directly input to the negative logic area, the signal is inverted.

In the top-down mapping method according to the embodiment of the present invention, a logical expression having a hierarchical structure is mapped from the highest order group to the lowest order group in consideration of logic level inversion in an inverted logic gate. Specifically, the final stage of the logic circuit is determined according to a given logical expression to be realized. If the logic is expressed in a positive logic format, the last stage of the circuit is made in a positive logic region, while if the logic is expressed in a negative logic format, the last stage of the circuit is made in a negative logic region. Then, when mapping from the output side to the input side of the logic circuit, every time an inverted logic gate is arranged in the circuit, a positive logic area and a negative logic area are alternately formed.
When mapping the highest-order group, if this highest-order group has only a logical function sharing one or more higher-order variables, a multiplexer having an inverter on the output side is arranged at the output of the logic circuit. When the top-level group contains only one logical function containing one or more common variables,
If the output of the logic circuit is of a positive logic type, a NOR gate is arranged at the output of the logic circuit, and if the output of the logic circuit is of a negative logic type, a NAND gate is arranged. If the top-level group contains only one logical function with no common variables,
An inverter is placed at the output of the logic circuit. When the top-level group contains multiple independent lower-level logical groups,
If the final output is in positive logic format, NA
An ND gate is arranged, and if the final output is a negative logic type, N
An OR gate is arranged.

According to another aspect of the present invention, there is provided a method of mapping a logical expression having first and second product terms including n and m (m> n) logical functions to a logical circuit. A first having at least n input terminals and output terminals
Arranging a multi-input logic gate of the first multi-input logic gate, and inputting a logic function of a first product term directly to an input terminal of the first multi-input logic gate so that the first product term is a first multi-input logic. Connecting to output from the output terminal of the gate; a second multi-input logic gate having less than m input and output terminals; and a first input terminal, a first input terminal for inputting a constant. Arranging a unit multiplexer having two input terminals, a control terminal, and an output terminal; and connecting the first input terminal and the control terminal of the unit multiplexer to input at least two logical functions of a second product term. And inputting the input terminal of the second multi-input logic gate,
Inputting the at least two logic functions through the output terminal of the unit multiplexer such that the second product term is output from the output terminal of the second multi-input logic gate, thereby changing the logic function of the second product term. Connecting to input.

A CAD system for mapping a logical expression having first and second product terms including n and m (m> n) logical functions to a logic circuit, wherein at least n Means for arranging a first multi-input logic gate having an input terminal and an output terminal, wherein a logic function of a first product term is directly input, and the first product term is an output terminal of the first multi-input logic gate Means for connecting the input terminals of the first multi-input logic gate as output from the second multi-input logic gate having less than m input and output terminals; and
Means for arranging a first unit multiplexer having a first input terminal, a second input terminal for inputting a constant, a control terminal, and an output terminal; and a first input terminal and a control terminal of the unit multiplexer. Means for inputting at least two logic functions of the product term of two, and an input terminal of the second multi-input logic gate, wherein the second product term is output from an output terminal of the second multi-input logic gate. Means for inputting the at least two logic functions through an output terminal of a unit multiplexer to connect to input a logic function of a second product term.

A logic circuit for executing a logical operation represented by a logical expression having first and second product terms including n and m (m> n) logical functions, A first multi-input logic gate having at least n input terminals and an output terminal, and outputting the first product term from the output terminal by directly inputting a logic function of the first product term to the input terminal; a second having less than m input and output terminals
And a first input terminal, a second input terminal for inputting a constant, a control terminal, and an output terminal connected to one of the input terminals of the second multi-input logic gate. , Inputting at least two logic functions of the second product term through a first input terminal and a control terminal,
A unit multiplexer for inputting a logic function of the second product term to an input terminal of the second multi-input logic gate and outputting the second product term from an output terminal of the second multi-input logic gate; Is provided.

Further, an electronic system including a logic circuit for executing a logical operation represented by a logical expression having first and second product terms including n and m (m> n) logical functions A first multi-input having at least n input terminals and an output terminal, and outputting the first product term from the output terminal by directly inputting a logical function of the first product term to the input terminal A logic gate, a second multi-input logic gate having less than m input and output terminals, a first input terminal, a second input terminal for inputting a constant, a control terminal, and a second multi-input logic gate. Having an output terminal connected to one of the input terminals of the input logic gate and inputting at least two logic functions of the second product term through the first input terminal and the control terminal to provide a second product The logical function of the term to the input of the second multi-input logic gate Input to the second product term electronic system that includes a logic circuit having a unit multiplexer to be output from the output terminal of the second multi-input logic gates are provided.

Further, there is provided a method for executing a logical operation represented by a logical expression having first and second product terms including n and m (m> n) logical functions. Directly inputting a logical function of the product term to an input terminal of the first multiple-input logic gate and outputting the first product term from an output terminal of the first multiple-input logic gate; Inputting at least two logical functions to a first input terminal and a control terminal of a unit multiplexer having a second input terminal connected to input a constant; and transmitting the at least two logical functions to the unit multiplexer. By inputting through the output terminal, the logic function of the second product term is input to the input terminal of the second multi-input logic gate, and the second product term is output from the output terminal of the second multi-input logic gate. Having steps and How to perform logical operations is provided.

First, primary mapping is performed, and then, even when logic level matching is performed, or when logic level matching is performed in the mapping process, a given logical expression is used in many cases with pass transistors. When mapping to a logic circuit including an input logic gate, it is desirable to appropriately combine a multi-input logic gate and a pass transistor to minimize the total number of transistors and the number of stages of the obtained logic circuit.

When mapping a logical expression to a logical circuit,
Generally, product term mapping is required. In mapping the bottom group, each product term contains only variables. When mapping groups other than the lowest group, each product term includes one or more variables and one or more logic functions mapped by other logic circuits. Alternatively, it includes a plurality of logic functions. For example, in the case of a logical group including a common variable, if the sum of logical functions sharing the common variable is regarded as one logical function, the logical group can be regarded as a product term including the logical function and the common variable. The simplest form of a logical function is a single variable. Therefore, "the product term including the logical function" includes the product of the variables.

When such a product term is mapped to a logic circuit by using a pass transistor and a multi-input logic gate, the multi-input logic gate and the pass transistor are appropriately set in accordance with the number of logic functions included in the product term. , It is desirable to minimize the number of transistors and the number of stages. For example, if a product term is mapped using only a multi-input logic gate, the multi-input logic gate needs to have as many input terminals as the number of logic functions in the product term. However, the number of transistors included in a multi-input logic gate increases with the number of input terminals. Further, the number of stages increases according to the number of input terminals, and the operation speed decreases. To avoid this problem, it is generally desirable to limit the number of input terminals of a multi-input logic gate to three or four. When the product term to be mapped contains more logic functions than the upper limit, pass transistors are combined with multi-input logic gates.

More specifically, if the total number of variables or logic functions included in the product term is 2 or more, if the total number of input terminals of the multi-input logic gate is not more than the allowable maximum number, a multi-input logic gate is arranged. , The logic function is input to its input terminal. on the other hand,
If the total number of logic functions is larger than the maximum allowable number of input terminals of the multi-input logic gate, the output of the pass transistor is connected to the input terminal of the multi-input logic gate, and the input terminal and the control terminal of the pass transistor are multi-input. Similarly to the input terminal of the logic gate, a multi-input logic gate and a pass transistor are combined so as to receive a logic signal corresponding to a logic function.

In general, rather than a single pass transistor,
Preferably, a combination of pass transistors in the form of a multiplexer is employed. When the unit multiplexer is used, a constant is input to one of the two input terminals, and the output terminal is connected to one of the input terminals of the multi-input logic gate.
The other input and control terminals of the unit multiplexer are used to receive the logic function of the product term. That is, two logic functions can be input to the multi-input logic gate via the unit multiplexer. One logic function is input from one input terminal of the multiplexer, and the other logic function is input to a control terminal of the multiplexer.
When the series connection of the two unit multiplexers is connected to one input terminal of the multi-input logic gate, two logic functions are connected to one input terminal and the control terminal of the first stage unit multiplexer, respectively. , These two logical functions are passed through the first stage unit multiplexer to the second
It is input to one input terminal of the unit multiplexer of the stage. These two logic functions and another logic function input to the control terminal of the second stage unit multiplexer, that is, a total of three logic functions, are input to the multi-input logic gate via the two unit multiplexers. You. When multiple multiplexers are connected in series within acceptable limits, and each input terminal of a multi-input logic gate is connected to a similar series connection of unit multiplexers, it is possible to map a product term that includes a larger number of logic functions. It becomes possible.

In other words, when the number of logic functions included in the product term is less than the maximum allowable number of input terminals of the multi-input logic gate, all logic functions pass directly, that is, pass through the multiplexer. Instead, it is input to the input terminal of a multi-input logic gate. On the other hand, if the number of logic functions is greater than the maximum allowable number of input terminals of the multi-input logic gate, some of the logic functions are input to the input terminals of the multi-input logic gate through one or more multiplexers.

As shown in JP-A-9-93118,
Alternatively, if an inverter including a pull-up transistor is used to recover the decay of the logic amplitude that occurs when the signal passes through the pass transistor, as in the second prior art already described, one or more After the logic function (more precisely, the product of the logic functions) is inverted by the inverter through the multiplexer, it is input to the corresponding input terminal of the multi-input logic gate.

In the primary mapping process, when the product terms are mapped by the above method, the AND gate is used as a multi-input logic gate. These AND gates are at the logic level match after the primary mapping, and
Replaced by D or NOR gate. On the other hand, if logic level matching is performed during mapping, NOR or NAND gates are employed depending on whether the gate is located on the output or input side of the negative logic region.

A logical function included in a product term may be represented by a plurality of variables, a plurality of lower logical functions, or a product of a variable and a lower logical function. In this case, the logic function is first mapped into the circuit, for example using a multi-input logic gate, and then the product terms are mapped using other multi-input logic gates in the manner described above. In this case, the number of unit multiplexers associated with the multi-input logic gate to which the product term is mapped is determined by the number of logic functions included in the product term. That is, the above logical function is counted as one. Alternatively, each of one or more variables or lower-level logic functions included in such a logic function can be input to an input terminal of a multi-input logic gate to which a product term is mapped. In this case, the number of unit multiplexers associated with the multi-input logic gate to which the product term is mapped is determined by the total number of logic functions included in the product term. That is, all the variables and lower logical functions included in the logical function are counted. In order to reduce the number of stages and the number of multi-input logic gates connected in series, the latter technique is preferable to the former technique.

According to another aspect of the present invention, there is provided a method of mapping a logical expression to a logical circuit, comprising: a multi-input logical gate having a plurality of input terminals and an output terminal; Arranging a multiplexer having one control terminal and an output terminal in a logic circuit; and inputting a plurality of lower-order logic functions and outputting a product of the lower-order logic functions from an output terminal of the multi-input logic gate. Connecting the input terminals of the logic gate, inputting a plurality of logic functions including a product of the lower logic function and at least one upper variable, including the logic function and at least one upper variable shared by the logic function Connecting the input terminal of the multiplexer and at least one control terminal to output the logical group from the output terminal of the multiplexer; Mapping method comprising is provided.

Further, there is provided a CAD system for mapping a logic expression to a logic circuit, comprising a multi-input logic gate having a plurality of input terminals and output terminals, a plurality of input terminals, at least one control terminal and an output terminal. Means for arranging a multiplexer having a logic function in a logic circuit, and inputting a plurality of lower-order logic functions, and inputting the input terminal of the multi-input logic gate so as to output a product of the lower-order logic functions from the output terminal of the multi-input logic gate. Connecting, inputting a plurality of logical functions including a product of the lower logical functions and at least one upper variable,
Means for connecting the input terminal of the multiplexer and at least one control terminal such that the logical function and a logical group including at least one upper variable shared by the logical function are output from the output terminal of the multiplexer. A CAD system is provided.

Further, it is a logic circuit for executing a logical operation, having an input terminal for inputting a plurality of lower logical functions and an output terminal for outputting a product of the lower logical functions. A multi-input logic gate, an input terminal for inputting a plurality of logic functions including a product of the lower logic function, at least one control terminal for inputting at least one upper variable, and A multiplexer having an output terminal for outputting a logic group including at least one upper variable shared by the logic function.

Further, there is provided an electronic system including a logic circuit for executing a logical operation, an input terminal for inputting a plurality of lower logical functions, and an output terminal for outputting a product of the lower logical functions. A multi-input logic gate having an output terminal, an input terminal for inputting a plurality of logic functions including a product of the lower logic function, at least one control terminal for inputting at least one upper variable, and A logical function and at least one shared by the logical function
And a multiplexer having an output terminal for outputting a logic group including two upper variables.

Further, there is provided a method of executing a logical operation, wherein a plurality of lower logical functions are input to an input terminal of a multi-input logical gate such that a product of a plurality of lower logical functions is output from an output terminal of the multi-input logical gate. Inputting a function and including a product of the lower logical functions so as to output a logical group including a plurality of logical functions and at least one upper variable shared by the plurality of logical functions from an output terminal of the multiplexer. Inputting a plurality of logic functions and at least one upper variable to an input terminal and at least one control terminal of the multiplexer.

When a given logical expression is mapped to a logical circuit including a pass transistor and a multi-input logical gate, if the logical expression includes a logical group including a higher-order variable, it is formed by combining pass transistors in the mapping. Multiplexed logic gates are employed if the logic equation includes a product of logic functions. As a result, the logical expression is mapped to the logical circuit using a small number of transistors and the number of stages. Therefore, when the logical expression includes a logical group including the upper variable, the logical function sharing the upper variable is input to the input terminal of the multiplexer, and the upper variable is input to the control terminal of the multiplexer. If the logical group contains multiple upper variables, a multi-stage multiplexer is employed. If some or all of the logic functions sharing the upper variable are each the product of the lower logic functions, such a logic function is first mapped using a multi-input logic gate, and then the input terminals of the multiplexer. Is input to That is, a plurality of lower-order logic functions are input to the input terminals of the multi-input logic gate, and as a result, a logic function including the plurality of lower-order logic functions is output from the output terminal of the multi-input logic gate. Depending on the number of lower logical functions included in the product term,
The required number of unit multiplexers with one input maintained at a constant logic value are added.

According to another aspect of the invention, there is provided a method of mapping a logical expression to a logical circuit, comprising: a multiplexer having a plurality of input terminals, at least one control terminal and an output terminal, and a first input terminal. Terminal, at least one
Arranging a multi-input logic gate having two second input terminals and an output terminal in a logic circuit; inputting a plurality of lower logic functions and at least one upper variable; Connecting an input terminal of the multiplexer and at least one control terminal such that a lower logical group including the at least one upper variable shared by a logical function is output from an output terminal of the multiplexer; A first input terminal of a multi-input logic gate such that one common variable is input and a logic group consisting of a product of the at least one common variable and a lower logic group is output from an output terminal of the multi-input logic gate. And connecting the at least one second input terminal.

Further, there is provided a CAD system for mapping a logical expression to a logical circuit, the multiplexer having a plurality of input terminals, at least one control terminal and an output terminal, a first input terminal, and at least one first terminal. Means for arranging a multi-input logic gate having two input terminals and two output terminals in a logic circuit; and inputting a plurality of lower logic functions and at least one upper variable, the lower logic function and the lower logic function Connecting the input terminal of the multiplexer and the at least one control terminal so that the lower logical group including the at least one upper variable shared by the at least one output terminal is output from the output terminal of the multiplexer; Enter one common variable and calculate the product of this at least one common variable and the lower logical group. Means for connecting a first input terminal of the multi-input logic gate and at least one second input terminal such that the logic group is output from an output terminal of the multi-input logic gate is provided. .

Furthermore, a logic circuit for executing a logical operation, comprising: an input terminal for inputting a plurality of lower logical functions; at least one control terminal for inputting at least one upper variable; A multiplexer having an output terminal for outputting a lower logical group including the lower logical function and at least one upper variable shared by the lower logical function; and a first for inputting the lower logical group. And at least one second input terminal for inputting at least one common variable, and an output for outputting a logical group consisting of a product of the lower logical group and at least one common variable And a multi-input logic gate having a terminal.

Further, there is provided an electronic system including a logic circuit for executing a logical operation, comprising: an input terminal for inputting a plurality of lower logical functions; and at least one control for inputting at least one upper variable. A multiplexer having a terminal and an output terminal for outputting a lower logical group including the lower logical function and the at least one upper variable shared by the lower logical function; A first input terminal for inputting, at least one second input terminal for inputting at least one common variable, and a logical group comprising a product of the lower logical group and at least one common variable And a multi-input logic gate having an output terminal.

Further, there is provided a method of executing a logical operation, wherein a lower logical group including a plurality of lower logical functions and at least one upper variable shared by the lower logical functions is output from an output terminal of the multiplexer. Inputting the lower logical function and the at least one upper variable to the input terminal and the at least one control terminal of the multiplexer, and multi-inputting a logical group consisting of a product of the at least one common variable and the lower logical group The lower logic group and at least one common variable are output from the first input terminal and at least one second input terminal of the multi-input logic gate so as to output from the output terminal of the logic gate.
And inputting to the input terminal of (i).

When the logical expression to be mapped includes a logical group including a common variable, the sum of the common variable and a logical function sharing the common variable is input to the input terminal of the multi-input logical gate. The sum of logical functions sharing a common variable is
If it is a lower logical group that includes an upper variable, the lower logical group is first mapped using a multiplexer and then input to a multi-input logic gate.
That is, a plurality of lower logical functions sharing the upper variable are input to the input terminal of the multiplexer, and the upper variable is input to the control terminal of the multiplexer. As a result, the lower logical group is output from the output terminal of the multiplexer.
The lower logic group and the common variable mapped in this way are input to the input terminals of the multi-input logic gate. According to the number of common variables, the required number of unit multiplexers in which one input terminal is maintained at a constant logical value are added. If the lower logical group is a logical group including multiple higher variables, a multi-stage multiplexer is employed.

When an inverter including a pull-up transistor is used to recover the attenuation of the logic amplitude generated when a signal passes through the pass transistor, the lower logic group output from the output terminal of the multiplexer is controlled by the inverter. After being inverted, it is input to the input terminal of the multi-input logic gate.

If some or all of the lower logical functions that share the upper variable are each the product of the second lower logical function, such lower logical function will first have another multi-input function. Mapped using logic gates, then
It is input to the input terminal of the multiplexer.

According to yet another aspect of the present invention, there is provided a method for mapping a logical expression to a logical circuit, comprising: a first type of multi-input logical gate having a plurality of input terminals and an output terminal; Arranging in a logic circuit a multiplexer having a terminal, at least one control terminal and an output terminal, and a second type of multi-input logic gate having a plurality of input terminals and output terminals, one of the input terminals of the multiplexer Is connected to the output terminal of the first type of multi-input logic gate without inversion, and one of the input terminals of the second type of multi-input logic gate is connected to the output terminal of the multiplexer without inversion. And a mapping method. Here, the first type of multi-input logic gate is one of a NAND and a NOR gate, and the second type of multi-input logic gate is the other of a NAND and a NOR gate.

Preferably, the method further comprises: inputting a plurality of second lower-order logic functions, and outputting a product of the second lower-order logic functions from an output terminal of the first-type multi-input logic gate. To connect the input terminals of a first type of multi-input logic gate, input a plurality of lower logic functions including a product of the second lower logic function and at least one upper variable, Connecting the input terminal of the multiplexer and at least one control terminal to output from the output terminal of the multiplexer a lower logical group including at least one upper variable shared by the lower logical function and the lower logical function. A plurality of logic functions including a lower logic group are input, and a logic group consisting of a product of the logic functions is output from the output terminal of the second-type multi-input logic gate. And connecting the type of the input terminals of the multi-input logic gates, it will be preferable to include.

Furthermore, there is provided a CAD system for mapping a logic circuit to a logic expression, wherein the first type of multi-input logic gate has a plurality of input terminals and an output terminal, a plurality of input terminals, and at least one control terminal. Means for arranging a second type of multi-input logic gate having a plurality of input terminals and output terminals in a logic circuit, and one of the input terminals of the multiplexer being connected to the first type of multi-input. Connected to the output terminal of the logic gate without inversion, and connected to one of the input terminals of the second type of multi-input logic gate.
Means for connecting one to the output terminal of the multiplexer without inversion. Here, the first type of multi-input logic gate is NAND or N
One of the OR gates and the second type of multi-input logic gate is the other of the NAND and NOR gates.

Furthermore, a logic circuit for executing a logical operation, comprising: a first type of multi-input logic gate having a plurality of input terminals and output terminals; A multiplexer having a plurality of input terminals connected to the output terminal of the multi-input logic gate, at least one control terminal and an output terminal, and a plurality of input terminals connected to the output terminal of the multiplexer without one being inverted; A second type of multi-input logic gate having an output terminal. Here, the first type of multi-input logic gate is one of a NAND gate and a NOR gate, and the second type of multi-input logic gate is NAN.
D or the other of NOR gates.

Preferably, the input terminals of the first-type multi-input logic gate are connected to input a plurality of second lower-order logic functions, so that the product of the second lower-order logic functions is It is output from the output terminal of the first type of multi-input logic gate. Also, the input terminal and at least one control terminal of the multiplexer are connected to input a plurality of lower logical functions including a product of the second lower logical function and at least one upper variable, so that: A lower logical group including the lower logical function and at least one upper variable shared by the lower logical function is output from an output terminal of the multiplexer. Further, the input terminals of the second type of multi-input logic gate are connected to input a plurality of logic functions including the lower logic group, so that the logic group including the product of the logic functions is connected to the second logic gate. It is output from the output terminal of each type of multi-input logic gate.

Further, there is provided an electronic system including a logic circuit for executing a logical operation, wherein a first type of multi-input logic gate having a plurality of input terminals and output terminals, and one being a first type of multi-input logic gate. A multiplexer having a plurality of input terminals connected to the output terminal of the input logic gate without inversion, at least one control terminal and an output terminal, and a plurality of ones connected without inversion to the output terminal of the multiplexer. An electronic system is provided having a logic circuit having an input terminal and a second type of multi-input logic gate having an output terminal. Here, the first type of multi-input logic gate is one of NAND and NOR gates, and the second type of multi-input logic gate is NAND or N
The other of the OR gates.

Further, there is provided a method of executing a logical operation, wherein a product of a plurality of second lower-order logic functions is output from an output terminal of a first-type multi-input logic gate. To the input terminal of the first type of multi-input logic gate, and a lower logical group including a plurality of lower logical functions and at least one upper variable shared by the lower logical functions is provided. Including, without inverting the product of said second lower-order logic function as one of said lower-order logic functions, so as to be output from the output terminal of the multiplexer, And at least one higher-level variable to the input terminal and at least one control terminal of the multiplexer.
One of the logical functions includes inputting the lower logical group without inversion so as to be output from the output terminal of the multi-input logical gate of the second type. Inputting to an input terminal of an input logic gate. Here, the first
Type of multi-input logic gate is one of a NAND gate and a NOR gate, and the second type of multi-input logic gate is
The other of the AND and NOR gates.

For example, a logical expression includes a logical group having a product of two or more logical functions, and one of the logical functions is a lower logical group including an upper variable and a lower logical function sharing the upper variable. It is assumed that some or all of the lower logical functions are products of a plurality of second lower logical functions, respectively. When such a logical expression is mapped to a logical circuit by first performing a primary mapping and then performing a logical level matching, or by simultaneously performing the mapping and the logical level matching, the obtained logical circuit is provided on the input side. A first type of multi-input logic gate arranged, a multiplexer having one input terminal connected to an output terminal of the first type of multi-input logic gate,
A second type of multi-input logic gate having one input terminal connected to the output terminal of the multiplexer. One of the first type and the second type of multi-input logic gate is a NAND
A gate, and the other is a NOR gate. Which of the multi-input logic gates is a NAND gate or a NOR gate depends on whether a circuit area between these multi-input logic gates is a positive logic area or a negative logic area. In this logic circuit, a connection between an output terminal of a first-type multi-input logic gate and one input terminal of a multiplexer;
The connection between the output terminal of the multiplexer and one input terminal of the second type of multi-input logic gate is made non-inverting. That is, they are connected so that inversion of the logic does not occur.

The first type of multi-input logic gate inputs a plurality of second lower-order logic functions to its input terminal and outputs a product of the second lower-order logic function from its output terminal. used. On the other hand, the multiplexer inputs the lower logical function to its input terminal, inputs the upper variable to its control terminal, and outputs the lower logical function including the upper variable and the lower logical function sharing this upper variable from its output terminal. Used to output groups. A second type of multi-input logic gate is used to input two or more logic functions to its input terminal and to output from its output terminal a logic group containing the product of these two or more logic functions.

The logic circuit configured as described above has the following advantages. First, in this technique, the logical group containing the upper variable is mapped to the multiplexer,
A product of a plurality of logic functions included in the logic group is mapped to the multi-input logic gate. Thus, a logic circuit having a small number of transistors and a small number of stages can be realized by utilizing the advantages of both the pass transistor and the multi-input logic gate.
Further, the number of transistors can be reduced by using a NAND or NOR gate, which is an inverted logic gate, as a multi-input logic gate.

In some cases, one of the logical functions included in a logical group can be one or more common variables. Depending on the number of common variables, the required number of unit multiplexers, one input terminal of which is maintained at a fixed logic level, can be used in combination with the second-type multi-input logic gate.

When two or more logical functions included in a logical group are lower logical groups each including an upper variable, each lower logical group can be mapped using one multiplexer.

Further, one of the second lower-order logical functions is a lower-order upper variable and a third lower-order logical function sharing the lower-order upper variable, and further, a part of the third lower-order logical function Or all, respectively, constitute the product of the fourth lower-order logic function. In such a case, the second lower-level logic group includes a second second-type multi-input logic gate disposed on the input side and one input terminal having a second second-type multi-input logic. A second multiplexer connected to the output terminal of the gate. A second second type of multi-input logic gate is used to input a fourth lower logic function to its input terminal and output a third lower logic function from its output terminal. The second multiplexer inputs a third lower logical function to its input terminal, inputs a lower higher variable to its control terminal, and outputs a second lower logical group from its output terminal. used. The second lower logic group mapped in this way is then input to the input terminal of the first type of multi-input logic gate as one of the second lower logic functions. Connection between the output terminal of the second second-type multi-input logic gate and one input terminal of the second multiplexer, and between the output terminal of the second multiplexer and the first-type multi-input logic gate; The connection between the input terminals is made without inversion.

[0119]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 8 shows a basic configuration of a composite pass transistor logic circuit described in Japanese Patent Application Laid-Open No. 9-93118. This composite pass transistor logic circuit is configured to individually input a plurality of outputs obtained from a plurality of pass transistor logic circuits (pass transistor logic operation systems) R to a multi-input logic gate S. Here, the pass transistor logic operation system R is defined as a circuit having a plurality of pass transistors connected in series and / or in parallel, and outputs a logic operation result based on input logic signals received from a plurality of input nodes.

When the pass transistors are connected in series, the output terminal of the previous pass transistor is connected to the input terminal of the next pass transistor. When the pass transistors are connected in parallel, the output terminals of the pass transistors are mutually coupled. A control terminal or an input terminal that is not connected to the output terminal of the other pass transistor is used as an input node.

FIG. 9 shows an example of a pass transistor logical operation system. The pass transistor logical operation system R in FIG.
It is configured using a total of three unit multiplexers Q shown in the upper part of FIG. For convenience of drawing, unit multiplexer Q
Are shown using the symbols shown in the lower part of FIG. This unit multiplexer has two pass transistors formed by n-channel MOS transistors whose drains are connected to each other. The sources of the two pass transistors are input terminals X and Y of the unit multiplexer, and the drains connected to each other are output terminals U.

In many cases, a complementary signal is input to the gate of each pass transistor acting as a control terminal. Therefore, in the example shown in FIG.
While the gate of the S transistor is directly connected to the control terminal Z of the unit multiplexer, the gate of the other MOS transistor is connected to the control terminal via an inverter, and the signal applied to the control terminal Z is After being inverted, it is supplied to the gate.

The multiplexer used in the present invention is configured as described above. That is, a structure including two pass transistors whose output terminals are connected to each other is adopted as a unit structure, and a plurality of unit structures are combined as needed. However, the present invention is not limited to the structure as shown in FIGS.

For example, each unit multiplexer does not necessarily need to include an inverter therein. For example, when a pair of complementary signals are generated by another circuit,
This complementary signal can be supplied to each control terminal of the two pass transistors. When a common signal is applied to the control terminals of a plurality of unit multiplexers, the inverter may be shared by the unit multiplexers.

Instead of using an n-channel MOS transistor to form a pass transistor, a p-channel M
An OS transistor may be used. Alternatively, an n-channel MOS transistor and a p-channel MOS transistor may be combined. Further, a switching element other than the MOS transistor may be used.

As disclosed in JP-A-9-162722, the pass transistor may be configured by combining a switching element with an auxiliary switching element having an opposite polarity and a smaller driving capability. In particular,
An n-channel MOS transistor is employed as a switching element, and a p-channel MOS transistor having a smaller size (ratio of gate width to gate length) than this can be employed as an auxiliary switching element. Furthermore,
As disclosed in JP-A-9-93118, a unit multiplexer is composed of two switching elements having opposite polarities,
For example, an n-channel MOS transistor and a p-channel M
The output terminals of the switching elements may be connected to each other using an OS transistor.

As the multi-input logic gate S shown in FIG. 8, AND gate, OR gate, NAND gate, NO
An R gate can be used. The number of input terminals can be two or any other suitable value. Typically, as in some embodiments of the invention described below, a three-input NA
An ND gate or a three-input NOR gate can be used. These multiple-input logic gates typically have multiple-input C
Although it can be a MOS logic gate, other types of multi-input logic gates can be used.

In some embodiments of the present invention,
Multiplexers consisting of a combination of multi-input logic gates and pass transistors as described above are used to construct the logic circuit. However, the method of connecting a multiplexer to a multi-input logic gate is used in a complex pass transistor logic circuit as shown in FIG. 8 in which outputs from a plurality of multiplexers are independently input to input terminals of the multi-input logic gate. It is not limited to the method used.
Further, the logic circuit may be configured using only pass transistors without using a multi-input logic gate.

In the case of a logic circuit including both a pass transistor and one or more multi-input logic gates, it is important to configure the logic circuit so that an effect is obtained as a result of the co-operation of the pass transistor and the multi-input logic gate. . In the present invention,
Given a logical expression to be realized, a part of the expression suitable for being composed of pass transistors and a part suitable for being composed of a multi-input logic gate are extracted from the logical expression. Both transistors and multi-input logic gates are effectively mapped into the used logic circuit. This technique allows the logic circuit to be configured to take advantage of both pass transistors and multi-input logic gates. That is, the present invention is not limited to a particular method of connecting a pass transistor to a multi-input logic gate employed in a composite pass transistor logic circuit, and the advantages of both the pass transistor and the multi-input logic gate result. As obtained by a logic circuit, pass transistors and multi-input logic gates are
They are combined in various ways.

In general, when a signal passes through a pass transistor, the logic amplitude decreases. When a large number of pass transistors are connected in series, the decrease in logic amplitude is large.
As a result, the noise margin decreases, and in the worst case, the logic signal cannot be accurately transmitted to the next stage. Further, when a large number of pass transistors are connected in series, the series connection of the resistors between the input and output terminals of the pass transistors reduces the signal propagation speed. In order to avoid this problem, it is desirable to determine the maximum allowable number of pass transistors connected in series in advance. When the number of pass transistors connected in series reaches the predetermined maximum number, an element such as a buffer for restoring the logic amplitude is inserted. In the case of a logic circuit including both a pass transistor and a multi-input logic gate, the multi-input logic gate can be used as an element for recovering a logic amplitude. The maximum allowable number of pass transistors that can be connected in series without using an element for recovering the logic amplitude, that is, the maximum allowable number of stages of the pass transistor logical operation system is not limited to a specific value, but the complexity of the logic circuit and In consideration of the balance between the operation speeds of the other parts of the logic circuit, it is generally desirable to set the maximum allowable number to 2 or 3.

When a multi-input logic gate is arranged at a stage following the pass transistor logic operation system, a large static through current flows through the multi-input logic gate, and as a result, the power consumption of the logic circuit may increase. There is. The static feed-through current is defined as VDD through a circuit element after the output level reaches a stable state of either "1" or "0" logic level.
It indicates a through current flowing from the power supply to the GND power supply. this is,
This occurs even when a circuit structure having a small static through current, such as a CMOS structure, is employed to form a multi-input logic gate. This is because the decrease in logic amplitude caused by the pass transistor causes one of the complementary switching elements (an n-channel MOS transistor and a p-channel MOS transistor in the case of a CMOS multi-input logic gate) constituting a multi-input logic gate. This is because an incomplete OFF state is set. In order to avoid such a problem, Japanese Patent Application Laid-Open
It is desirable to suppress the static shoot-through current using any of the possible techniques as disclosed in 93118 and 9-162722.

Before describing a specific embodiment according to the present invention, a circuit design technique common to all embodiments will be described first.

In the embodiment described below, a method of designing a logic circuit for executing a specific logical operation is presented. Typically, a logic circuit designed according to the present invention is embodied in a semiconductor integrated circuit including one or more logic circuits designed according to the present invention. An integrated circuit may include one or more logic circuits designed by some other technology. The integrated circuit can be used in combination with other integrated circuits or independent devices to form an electronic system for performing various functions. For example, FIGS. 11 and 12 show block diagrams of a personal handyphone handset and a digital cellular phone subscriber unit, respectively. As shown in these figures,
Various circuits are used in these systems.
Of these circuits, some or all of the circuits indicated by * in the figure are particularly suitable for being designed according to the present invention. This is because these circuits are strongly required to have a small number of transistors, low power consumption, and high operation speed.

The embodiments described below are directed to a method of optimizing a given logical expression and a method of converting a given logical expression to a logic circuit including a pass transistor, in particular, including both a pass transistor and a multi-input logic gate. It deals with how to map to logic circuits. The present invention can be employed to design large-scale logic circuits in the form of integrated circuits used in various practical fields.

Typically, the methods of these embodiments according to the present invention are performed on a CAD (Computer Aided Design) system of a mainframe computer, an engineering workstation or a personal computer. As shown in FIG. 13, the CAD system includes a CPU,
An input device (magnetic tape device or network) for inputting a logical expression to be designed, an output device (magnetic tape device or network) for outputting designed circuit data, a logical expression or a logical circuit in the design process A storage device (semiconductor memory or magnetic disk) for storing is included.
The storage device also stores software for controlling the system. The CAD system further includes a keyboard, display and digitizer used as a man-machine interface. All of the processing shown in FIG. 7 is performed by either a single CAD system or multiple independent CAD systems for each processing. Further, the CAD system is also used to execute a circuit simulation for verifying a designed circuit or to generate a mask layout according to the designed circuit. All such CAD systems are within the scope of the present invention.

Further, the present invention provides a CAD program including the design algorithm or technique according to the present invention, and a medium such as a magnetic disk on which such a program is stored.
Include in that range.

The logic circuit obtained by the design method of the embodiment described below includes various new logic circuits. Such a novel logic circuit and an electronic system including such a novel logic circuit are also included in the scope of the present invention. Further, a method of performing a logical operation using such a novel logic circuit is also included in the scope of the present invention.

The logical operation to be executed by the logic circuit includes variables relating to inputs and outputs from the outside of the integrated circuit and inputs to a sequential circuit and a memory circuit (a flip-flop, a register and a memory) inside the integrated circuit. And variables related to outputs and logical expressions including inputs and outputs of nodes in the integrated circuit. Here, the term “logical expression” means an expression that describes a logical relationship between an output variable and a plurality of input variables. This expression may include the sum, product and / or sum of products of the input variables. This expression can also include various logic functions of the input variables. Typically,
This expression is described by a mathematical expression of the form "output variable" = "sum of products of input variables". However, this expression may be described in various other forms, including HDL (Hardware Description Language), truth tables and state transition diagrams. In a CAD system for designing a logic circuit, this logical expression given in an arbitrary form is converted into a form that can be read by a CPU, recorded in an appropriate place in a storage device of the CAD system, and written by the CPU. It is processed.

In order to obtain an excellent logic circuit which can operate at high speed and has a small number of transistors and low power consumption, it is generally desirable to optimize a given logic expression in consideration of the following points.

A1. Variables that have a strong influence on the output are placed at higher levels in the formula. These variables, located at higher levels in the logic expression, are input near the output of the designed logic circuit.

A2. Variables that are closely related to each other are placed in the same rank.

In designing a logic circuit including pass transistors, it is desirable to consider the following points.

A3. The logic circuit is designed to have a circuit structure that realizes the advantages of the multiplexer including the pass transistor. Thus, the number of transistors used in the circuit can be reduced. In this regard, the present invention provides a combination type method (variable combination method) described below.

In designing a logic circuit including a multi-input logic gate, it is desirable to consider the following points.

A4. Instead of mapping the product terms using independent multi-input logic gates, a plurality of product terms having one or more common variables are collected, and these product terms are input to a common multi-input logic gate. This reduces the number of transistors and the number of stages used. In this regard, the present invention provides a common variable method described below.

Further, when a multi-input logic gate is used in a logic circuit, it is desirable to consider the following points.

A5. As a multi-input logic gate, AND
A NAND gate or a NOR gate is more appropriate than a gate or an OR gate. In the case of a NAND gate or a NOR gate, since the logic is inverted, it is necessary to match the logic levels as described later.

A design method according to the present invention in which all or some of the above conditions A1 to A5 are considered will be described below. Logic circuits having unique aspects achieved by this design method will also be described in connection with each method. As briefly shown in FIG. 7, the basic design procedure according to the present invention comprises the steps of converting a given combinational logical expression into an optimal form suitable for mapping to a logic circuit, and performing a primary mapping. , Matching the logic levels. In other embodiments, mapping and logic level matching are performed simultaneously. In these and other embodiments described below, suitable techniques are presented that relate to various parts of the above procedure. In practice, logic circuits can be designed according to the appropriate combination of these techniques, described below with reference to specific embodiments. Further, these techniques can be combined with other conventional techniques.

Hereinafter, the first to fourth embodiments will be described.
Here, the first embodiment is based on the combination type method, the second embodiment is based on the bottom-up common variable method, and the third embodiment is based on the top-down common variable method. Fourth embodiment is based on the common variable / combination type method. Before describing the first to fourth embodiments separately, common matters will be described first.

In the first to fourth embodiments, the following logical expression (2) is used as an example.

[0152]

(Equation 2) Here, a, b, c, d, e, f, g, h, i, j are input variables, bars above the variables are negative logic,.
D) and + are logical sums (OR).

This logical expression includes a total of eight product terms. For these eight product terms, in the order in equation (2),
Number. In the table of FIG. 14, these eight product terms are described in the second to ninth rows counted from the top. In this table, variables of negative logic are represented by "0", variables of positive logic are represented by "1", and variables not included in each product term are represented by "2"(don't care). I have. In the table of FIG. 14, the variables a to j in the equation (2) are shown in order from left to right in each column of the first row. For example, the second line is the product term in equation (2).

[Outside 9] Is represented. Since this product term includes variables a to i of negative logic, “0” is inserted in a column corresponding to the variables a to i. Since this product term does not include the variable j, "2" is entered in the column corresponding to the variable j. Therefore, the second line in FIG. 14 is given by “0000000000002”.

In order to verify the algorithms of the first, second, and fourth embodiments of the present invention, a program shown in FIGS. 27, 28, 41, and 42, which will be described later, is replaced with a spreadsheet program “Microsoft”. Excel "Visua
1 Basic ". For example, FIG.
, Each variable name is registered in the first row starting from the “A1” cell of the “Excel” sheet, and the product terms are stored in the second and subsequent rows. Next, the program is started.

In the first to fourth embodiments and the fifth to seventh embodiments described below, the maximum allowable number of pass transistors is two, and the maximum allowable number of input terminals of a multi-input logic gate is There are three.

Hereinafter, a method for designing a logic circuit according to the first embodiment of the present invention will be described.

The logical expression shown in the following expression (3) can be mapped to a multiplexer including six pass transistors and three inverters, as shown in FIG. This circuit includes a small number of transistors and a small number of stages as compared to a logic circuit achieved using multiple-input logic gates. In this regard, this circuit is a good example of an ideal circuit configuration. In this circuit, each inverter has n
It can be constituted by a combination of a channel MOS transistor and a p-channel MOS transistor. Therefore,
This circuit includes a total of twelve transistors.
If one inverter is shared by two first-stage multiplexers, the total number of transistors can be reduced to ten.

[0158]

(Equation 3)

Here, C, D, E, and F are arbitrary logical functions.

In the equation (3), variables a and b are upper variables. As in this example, when a higher-level variable is selected from a given logical expression that represents a logical operation to be realized,
The logical expressions are grouped using the selected superior variable. The obtained logical expression is mapped to a logical circuit using a multiplexer.

In the first embodiment, a combination type method is used to specify one or more upper variables and group product terms in an efficient manner. In this combination type method, first, a set of variables is created. At this time, the number of variables in the set is determined according to the maximum allowable number of pass transistors connected in series. For example, if the maximum allowable value of the number of pass transistor stages is v, (v + 1) sets of variables are created. Next, the number of logical combination types of the variables in the set is determined. An example of v = 2 is shown in the variable tables of FIGS. Here, a single variable table is shown in FIG.
17 are divided into four tables shown in FIG.

For example, focusing on the variable c, the variables a, b, and c
Consider the number of logical combinations of the set In the second to ninth rows of the table shown in FIG.
The combination of “00” and the product term are shown as “111”, and the product term is shown as “101.” Therefore, the number of different combinations of variables is 3. Therefore, 11 in FIG. Put "3" in the third column of the row. Since the value of the variable c of the product term is "2"(don't care), the product term does not include the variable c. Not included, not shown in this table, but variable c
Is not "2" and the other two variables are "2", for example, the combination of "221" or "220" is not counted.
On the other hand, a combination in which one of the variables other than c is “2” and the other two variables are values other than “2”, for example, “211” or “120” is counted.

Similarly, the number of logical combinations of variables d, e, f, g, h, i, j and variables b, c is entered in the fourth row to the tenth column of the eleventh row. The number of logical combination types is determined in the same manner in the twelfth line and below.

Alternatively, instead of the (v + 1) variables,
You may combine v variables. In this case, the number of combinations is as shown in FIG. However, (v +
1) It is easier to determine the difference in the number of combinations by combining the variables. In general, if the number of product terms is greater than 2 ^v ,
(V + 1) variables are combined with each other, and the number of product terms is (v +
1) If less, combine v variables with each other.

In this embodiment, v is 2.
v can have different values. (v + 1) with v = 1
When the variables are combined, the combinations “21” and “20” are counted. When v = 1 and v variables are combined, “1” and “0” are regarded as “combination” and counted.

After the number of logical combination types for all possible sets is obtained in this way, the maximum value of the number of logical combination types and the number of occurrences of this maximum value are obtained for each of the variables a to j. For example, the number of logical combination types focusing on the variable a is a numerical value in the first column from the 11th row in FIG. 14 to the 6th row from the bottom in FIG. Therefore, the maximum value is “8”,
The number of occurrences of this maximum value “8” is “6”. Therefore, in the first column of FIG. 17, the maximum value in the fourth row from the bottom is “8”.
And the maximum number of occurrences in the third line from the bottom is “6”
It has become. In the present embodiment, up to v variables are selected in descending order of the “maximum value of the number of combinations” and, in the case of the same number, in descending order of the “number of occurrences of the maximum value”. That is, the variables are selected in the order in which they are included in the set having the largest number of combinations. When the number of combination types is the same, variables are selected in descending order of the number of times included in a set having a large number of combination types.

The selected variables are set as upper variables, and product terms including these higher variables are grouped. The above (2)
In the formulas and the examples of FIGS. 14 to 17, first, the variable b (maximum number of combinations 8 and the number of occurrences 10), and then the variable a (maximum number of combinations 8 and the number of occurrences 6) are selected. Therefore, the product terms in the expression (2) are grouped as in the following expression (4).

[0168]

(Equation 4)

Thus, the first cycle of the optimization according to the first embodiment is completed.

In the equation (4), the variables a and b arranged outside the parentheses are upper variables, and the variables in each parenthesis are:
We have created a logical function that shares the upper variables.

As shown in equation (4), the process of introducing parentheses is merely for easy understanding, and is not essential to the present invention. In the actual process of designing a logic circuit using a CAD system, the logical formula is stored in an appropriate location in a storage device in a form that can be read by the CPU. It is determined which variables are the upper variables and which logical functions share the upper variables, and the results are stored in a storage device in a form that is read by the CPU. In this way, the grouping is performed by the CPU.

In the above example, the selected variables a, b
Are both top variables. That is, two upper variables can be specified by the above processing. However, v upper variables cannot always be specified. For example, v = 2
If the number of combinations of two variables is 4, then the product term is

[Outside 10] Can be grouped into a form having two multiple upper variables. If the number of combinations of two variables is 3, the product term is

[Outside 11] Can be grouped into a form having two partial multiple upper variables. On the other hand, when the number of combinations of two variables is two, only one variable is the upper variable. In this case, the product term is

[Outside 12] Or only one of a or b is an upper variable,
Or

[Outside 13] , The group can be grouped into a form including one upper variable a and one common variable b.

In consideration of these facts, it is possible to specify a variable that is actually a high-order variable and execute grouping on the specified high-order variable. Or v
It is also possible to select a number of variables and perform grouping on the selected variables. According to the former technique, better optimization is possible, whereas according to the latter technique, processing is simple.

Subsequently, similar processing is repeated as the second cycle of the optimization processing. In this cycle,
The lower logical group of each group, ie, the logical function in each parenthesis, is considered a logical expression, and the product terms contained in the logical expression are grouped in a similar manner. In this processing, in order to shorten the processing time, it is desirable to exclude common variables in the group and not perform processing for determining the number of combination types for these. This exclusion is easily performed, for example, by determining the logical product of all the product terms included in each group. This makes it easy to map common variables at the input terminals of the multi-input logic, taking advantage of the multi-input logic gate.

In the above equation (4), c bar of three product terms in parentheses of the first term and c of three product terms in parentheses of the second term are common to each group. Variable. After excluding these common variables, the numbers of logical combination types regarding the product terms in parentheses in the first term are as shown in the tables of FIGS. 19 and 20. Here, FIG. 19 and FIG. 20 show a single table divided into two. In the second to fourth rows of this table,
The three product terms included in this group (the first in equation (2),
2 (from the second and sixth terms) and the common variables are excluded. As shown in the fourth row from the bottom of the table in FIG. 20, the maximum value of the number of combinations is 3, and a set of variables including variables d, f, g, and h has a maximum value of 3.
Among them, as shown in the third line from the bottom, the variable d
Has a maximum number of occurrences of 30. Variables f, g and h
Has the next maximum occurrence 28. Therefore, first, the variable d is selected. Since the variables f, g, and h are equivalent, any of them may be selected next. Here, the variable f is selected. Using the selected variables d and f as upper variables,
The product terms in the group are further grouped.

Similarly, the product term of the second term is further grouped. Then, the original logical expression is converted into the following expression (5).

[0177]

(Equation 5)

In the above processing, an arbitrary lowest group is
The process is repeated until only one or zero product terms including only variables are included. In the expression (5), any logical function included in the lowest group, that is, any logical function in parentheses having the deepest nesting includes only one product term including only variables. In other words, the number of combinations of variables in the lowest group is 1 or 0, and therefore, no more grouping is possible.

A logic circuit obtained by performing a primary mapping process of a fifth embodiment described later and a logic level matching of the sixth embodiment with respect to the logic expression (5) optimized by the present embodiment is shown in FIG. 26 to FIG. here,
For convenience of drawing, a single circuit diagram is divided into a plurality of parts shown in FIGS. In FIG.
11-S22 is used to describe signal connections in the logic circuit. That is, signals represented by the same reference numerals in different drawings are connected to each other. This logic circuit has a total of 133 transistors, and the maximum number of pass stages is nine. Although this logic circuit is not the optimal solution, good results have been obtained. If a process of sharing a similar circuit structure by a plurality of portions of the circuit is performed, the configuration of the logic circuit can be further improved. For example, in the part shown in the upper part of FIG.
One multiplexer is commonly used to generate signals S11 and S17.

The logic circuits shown in FIGS. 21 to 26 include 22 unit multiplexers, 10 multi-input logic gates, and one inverter.

This circuit includes, for example, a two-stage multiplexer in the portion shown in FIG. This two-stage multiplexer is a logical group including two multiplex upper variables d and f.

[Outside 14] Used to map That is, the upper variables d and f are input to the control terminal, and the logical function

[Outside 15] Are input to input terminals as signals S11, S12 and S13. Similarly, the two-stage multiplexer of the part shown in FIG. 24 is a logical group including two multiplex upper variables d and i.

[Outside 16] And the two-stage multiplexer of the part shown in FIG.
Used to map logical groups containing
That is, the whole of the expression (5) is composed of the signals S19, S20 and S21.
, And other parts of the circuit that generate S22. As described above, the logic circuit includes three two-stage multiplexers for mapping a logic group, each containing two multiple upper variables. In other words, there are nine unit multiplexers for mapping logical groups that include multiple higher variables. Therefore, in this circuit, the advantages of the multiplexer are fully utilized. this is,
This is a characteristic aspect of a logic circuit obtained by mapping a logic expression optimized by a combination type method in which product terms are grouped so that the number of combination types is maximized. In particular, the upper variables are specified under the condition that the maximum number of stages of the pass transistor is v = 2, and the logical expression is optimized. Therefore, in order to map a logical group including two multiplex upper variables, a large number of two-stage multiplexers are used. Is used. Since this circuit is designed under the condition that the maximum allowable number of stages of the pass transistor is two, the number of multiplexers used in the circuit is two at the maximum. If a maximum of three or more pass transistor stages is allowed, a three or more stage multiplexer can be used to map a logical group including three or more multiple upper variables.

The logic circuit also includes a multi-input logic gate for mapping a logic group including a common variable.
For example, the two-input NAND gate of the portion shown in FIG.

[Outside 17] And the operation result is output as a signal S19 from its output terminal. That is, the common variable c is input to one input terminal of the two-input NAND gate, and the sum of the logic functions sharing the common variable c is
After being mapped by the two-stage multiplexer, N
The signal is input to the other input terminal of the AND gate. Similarly,
The two-input NAND gate shown in the upper part of FIG.

[Outside 18] Used to map

Multiplexers other than these nine unit multiplexers used for mapping the logical group including the upper variable, and multi-input logic gates other than the multi-input logic gate to which the common variable is input are formed by the product of variables. Used to map

The portion shown in FIG. 25 includes a complex pass transistor logic circuit in which the outputs of a plurality of pass transistor logic operation systems are independently input to the input terminals of a multi-input logic gate. However, this logic circuit is not configured in such a way as to obtain a specific connection between the pass transistor logic operation system and the multi-input logic gate. vice versa,
This circuit configuration performs a primary mapping of the logical expression (5) optimized according to a fifth embodiment described below,
This is obtained as a result of a process of performing logic level matching according to a sixth embodiment described later, and no special limitation is assumed in connection between the pass transistor logic operation system and the multi-input logic gate. As described above, equation (5) is
It has been obtained by optimizing a given logic equation so that pass transistors and multi-input logic gates have advantages. Thus, the resulting logic circuit is composed of a multi-input logic circuit and a pass transistor logic circuit (pass transistor logic operation system) that are connected to each other in various ways so that a given logical expression is efficiently realized. A circuit configuration including a gate is included.

For example, in the case of a two-stage multiplexer arranged at the last stage of the circuit (FIG. 26), the upper variables a and b are input to the control terminals, and the signals S1 and S2 which are logically independent from each other
9, S20, S21 and S22 are input to four input terminals, respectively. Here, "logically independent" signals are neither equivalent nor complementary to one another. These signals S1
9, S20, S21 and S22 are supplied from the output terminals of different multi-input logic gates. That is, the signal S19 is
(5) corresponds to the logical function in parentheses in the first term of the expression, and
The signal S19 is obtained by inputting the common variable c to a multi-input logic gate (NAND gate) and mapping a logic group including upper variables d and f by a two-stage multiplexer. The signals S11, S12 and S13 independent of each other are input to three of the four input terminals of the two-stage multiplexer shown in FIG. 22, and the remaining input terminals are provided with a constant signal having a logic level of "0". Is entered. This signal S11,
S12 and S13 each correspond to a product term containing only variables, mapped using a circuit including a three-input logic gate with one input terminal connected to a multiplexer. The signal S20 corresponds to the logic function in parentheses in the second term of the expression (5). As shown in FIG. 24, the signal S20 inputs the common variable c to a multi-input logic gate (NAND gate). Then, a logical group including the upper signals d and i is input to the control terminal of the two-stage multiplexer. The signals S14, S15 and S16 independent of each other are input to three of the four input terminals of the two-stage multiplexer shown in FIG. 24, and the remaining input terminals are provided with a constant signal having a logic level of "0". Is entered. The signals S14, S15 and S16 each correspond to a product term containing only variables, mapped using a circuit including a three-input zero AND gate having one input terminal connected to the multiplexer. On the other hand, the product term in parentheses of the third term in equation (5)

[Outside 19] Is obtained by using a three-input NAND gate having one input terminal connected to the two-stage multiplexer and the other two input terminals connected to the one-stage multiplexer. This signal S21 is
This signal S21 corresponds to the product term in parentheses of the fourth term of the equation (5), and as shown in FIG. 25, the input terminals of the signal S21 are connected to two one-stage multiplexers and one and two-stage multiplexers, respectively. By using a multi-input logic gate. As described above, a logic circuit designed according to the present invention has a circuit configuration including pass transistors and multi-input logic gates combined in various ways. As a result, the advantages of both circuit elements are exploited therein.

In an actual mapping process using a CAD system, information representing a logic circuit is written at a predetermined position in a storage device in a format readable by a CPU.

FIG. 27 and FIG. 28 show the above processing of this embodiment in a flow chart. Here, a single flowchart is divided into two in FIG. 27 and FIG. 28 for convenience of drawing. The process of this flowchart is
It can be programmed into a computer, and can be incorporated into a CAD system.

Assuming that the number of input variables of the logical expression optimized by the present embodiment is n and the number of product terms is m, the processing of the first cycle can be performed in the calculation time of the following expression (6). it can.

[0189] _{O ((m-1) n} P v + 1 + n n P v) ... (6)

In equation (6), _n P _{v + 1} is the number of permutations for selecting (v + 1) pieces from n sets. In the second and subsequent cycles, the number of input variables is reduced by v per cycle, and calculations can be performed excluding common variables in the group, so that the required calculation time is sharply reduced. Since the content of the calculation processing in the present embodiment is a simple comparison, it can be easily executed by a computer system or a CAD system.

In this embodiment, as described above, only the grouping process by the combination type method is repeatedly performed.
A given logical expression such as Expression (2) is converted into Expression (5) as follows:
The lowest group was converted to an optimal form containing only variables. However, the present invention is not limited to this embodiment. For example, the grouping process by the combination type method can be performed in combination with the grouping process by another method.

Next, a method of designing a logic circuit according to the second and third embodiments of the present invention will be described. Both the second and third embodiments are based on the common variable method. In particular, the second embodiment is based on the bottom-up common variable method, and the third embodiment is based on the top-down common variable method. .

In the pass transistor logic circuit, when the logical OR operation is realized using the multiplexer as described above, the circuit includes a small number of transistors and can operate at high speed. However, in order to implement a logical AND operation or a logical NAND operation in the form of a pass transistor logic circuit, it is necessary to connect a plurality of pass transistors in series. As a result, many transistors are required and the number of pass stages increases. For example, when the logic equation given by the following equation (7) is configured by a pass transistor logic circuit, the circuit is as shown in FIG.

[0194]

(Equation 6)

On the other hand, the above logical expression (7) is
When configured with ND logic gates, the circuit is as shown in FIG. As is clear from FIGS. 29 and 39, the logical NAND operation and the logical AND operation are CMOS-NAN.
The configuration using D gates is more advantageous than the use of pass transistors in terms of the number of transistors and the number of pass stages. Considering the above points, when designing a logic circuit that includes both a pass transistor and a multi-input logic gate,
It is better that the logical AND operation and the logical NAND operation are implemented using a multi-input logical gate. Further, in order to reduce the number of multi-input logic gates required to implement a logical AND operation and a logical NAND operation, instead of distributing AND terms and NAND terms into separate product terms, a logical group including a common variable is used. It is desirable to group. The logic group is mapped by a common multi-input AND gate or NAND gate. In the following second and third embodiments, a common variable method for specifying a common variable from a set of product terms in a given logical expression and efficiently grouping the product terms is presented.

First, a second embodiment based on the bottom-up common variable method will be described in detail.

In this embodiment, first, two product terms are combined with each other to obtain a common variable and the number thereof. The product terms are grouped by the common variables in order from the largest number of common variables to the smallest. Further, the common variable of each group is regarded as a new product term (deemed product term), and the same processing is repeated until there is no more common variable.

FIGS. 31 and 32 show variable tables used in the present embodiment. Here, one table is divided into two as shown in FIGS. 31 and 32 for convenience of drawing. FIG.
1 to 9 are the same as the above-described first to ninth lines in FIG. From the 11th line from the top in FIG. 31 to the 4th line from the bottom in FIG. 32, a set of two product terms that are checked to include a common variable are indicated by two signs on the right side of each line. At the right end of each row, the number of common variables included in the two product terms under consideration is shown.

In this variable table, a column of ten numerical values from the left end of each row to the right indicates whether each of the variables a to j is a common variable. If the numerical value is “0” or “1”, the corresponding variable is a common variable, and if “2”, it is not a common variable. The second line from the bottom of FIG.
The number of types of combinations of “0” of the common variable for each of j is shown. The lowermost row in FIG. 32 shows the number of combinations of “1” of the common variable for each of the variables a to j.

In the tables of FIG. 31 and FIG. 32, the maximum value “6” of the number of common variables shown on the right end of each row is shown in FIG.
It appears in the first line of 2. Therefore, the product terms corresponding to this row are first grouped. The number of the next largest common variable is “5”, and the product term, the product term, and the product term are excluded, except for the product term or the combination including any of which has already been determined to be paired in the preceding grouping. Terms and
A combination with a product term is a candidate with the same value “5”. In addition to the combination of the above, the common variables included in the combination of these four product terms are extracted as new product terms in the next cycle of the optimization process, and the common variables included in each combination of the two product terms are obtained. Is shown in the variable table of FIG. 33 in FIG.
The sixth line shows common variables included in a combination of product terms of,,, and, and these combinations are newly designated as product terms 〜. And 8 to 1
The seventh line shows the common variables included in each combination of these two new product terms.

Looking at the number of common variables shown at the right end of lines 8 to 17 in FIG. 33, the maximum value is 3, and the combination with the product term (with a new number in this table) and the product It can be seen that it can be obtained by a combination with the term.
Therefore, if the combination of the product term (and the product term number in FIG. 31) corresponding to these combinations is selected, the number of common variables in performing the second cycle grouping becomes large. And is preferred.

However, if a combination with a product term is selected, another combination cannot be adopted. Therefore, in this case, a combination of the product term and is selected. Therefore, the product terms in the logical expression given by the expression (2) are grouped into the form shown in the following expression (8) according to the present embodiment.

[0203]

(Equation 7)

In the expression (8), the first to third terms are groups corresponding to the combination of the product term selected by the above processing and. The fourth term is a group formed from the remaining product terms. Each term in the expression (8) is in the form of a product term of a variable (common variable) and a logical function (a part enclosed in parentheses).

In this example, since the even number of product terms are grouped together, all the product terms are grouped into any one set. However, when the above processing is applied to a logical expression having an odd number of product terms, one product term remains without being grouped. Furthermore, in reality, there may be no common variable between two product terms. In such a case, even if the number of product terms included in a given logical expression is even, a product term that remains without being grouped occurs.

Subsequently, similar processing as shown in the variable table of FIG. 34 is repeated in the second cycle of the optimization processing. In this cycle, the common variables of the four groups in the equation (8) are regarded as new product terms (deemed product terms).
As shown in the variable table, when these four new deemed product terms are respectively referred to as in order, the number of common variables is large in the deemed product term and the deemed product term and the combination thereof. . The result of further optimizing equation (8) with this combination is shown in equation (9) below.

[0207]

(Equation 8)

In equation (9), there is no longer a common variable between the first and second terms, which are the lowest product terms in parentheses with the deepest nesting. That is, equation (9) is
No further optimization is possible with the common variable method.

When the primary mapping of the fifth embodiment described later and the logic level matching of the sixth embodiment are performed on the logical expression (9), a logical circuit as shown in FIGS. 35 to 40 is obtained. The logic circuit is divided into FIGS. 35 to 40 for convenience of drawing, and reference numerals S31 to S35 are used to explain signal connections of the logic circuit. The logic circuit has 122 transistors and the maximum number of signal path stages is eight. Although this logic circuit is not the optimal solution, good results have been obtained. This logic circuit obtained by the bottom-up common variable method of the present embodiment has substantially the same number of transistors as the logic circuit obtained by the combination type method of the first embodiment, but has a smaller number of pass stages. ing. In the logic circuit, processing for sharing a similar part of the common circuit is not performed.

This logic circuit includes eleven unit multiplexers, thirteen multi-input logic gates, and one inverter.

In this logic circuit, a multi-input logic gate is used to map a logic group having a common variable, as described below. That is, in FIG. 35, a three-input zero-AND gate is used to receive common variables b and i at its input terminals, and outputs a signal S31 from its output terminal. In FIG. 36, 3-input zero AND
The gate is used to receive the common variables e and f at its input terminal, and outputs a signal S32 from its output terminal. In FIG. 37, a two-input NAND gate is used to receive a common variable c at one of its input terminals, and outputs a signal S33 from its output terminal. In FIG. 38, 3
The input NAND gate is used to receive the common variables b bar, c bar, f and h at its input terminal, and outputs a signal S34 from its output terminal. In FIG. 39, a three-input NAND gate is used to receive a common variable e bar and i bar at its input terminal, and a signal S3 from its output terminal.
5 is output. These multi-input logic gates used to map logic groups containing common variables are:
As a result of the logic level matching described later, the zero AND gate (=
NOR gate) or NAND gate. The logic level of the common variable input to the zero AND gate is inverted as a result of the logic level matching. In FIG. 38, the product of the common variables f and h and the product of the b and c bars are first generated by independent unit multiplexers, respectively. Input to each terminal.

In the above-described mapping process for obtaining a logic circuit, an additional process for specifying a logic group including an upper variable is performed, and as a result, such a logic group is mapped using a multiplexer. For example, the common variables a and c of the first and second terms of the highest level group
And a include the variable a in both positive and negative logic. Therefore, the variable a is an upper variable. For this reason,
At the second stage counted from the last stage of the circuit shown in FIG. 40, a multiplexer whose control terminal is connected so as to input the upper variable a is arranged. Further, common variables of the first and second terms of the second group in the second term

[Outside 20] Includes the variable g in the form of positive logic and negative logic. Therefore,
As shown in FIG. 40, at the third stage counted from the last stage of the circuit, a multiplexer connected so that the control terminal inputs the upper variable g is arranged. Similarly, the first term of the second group and the upper variable of the lower group are specified, and a multiplexer for mapping a logical group including the specified upper variable is arranged in the logic circuit. The upper variable is specified by counting the number of logical combination types in each group, for example.

Accordingly, the variable b shown in FIG. 39 is input to the control terminal, the variable d shown in FIG. 38 is input to the control terminal, and the variable j shown in FIG. 37 is input to the control terminal. Multiplexer
A multiplexer in which the variable b shown in FIG. 36 is input to the control terminal and a multiplexer in which the variable d shown in FIG. 35 is input to the control terminal are arranged. In this logic circuit, as described above, seven unit multiplexers each having one stage are used in order to map a logic group including upper variables.

The two unit multiplexers shown in FIG. 40 are connected in series so as to constitute a partial two-stage multiplexer. This multiplexer is not used to map a logical group containing multiple upper variables, but rather, each of the two unit multiplexers is used to map a logical group containing one upper variable. Since the logic circuit is designed under the condition that the maximum allowable number of stages of the pass transistor is 2, the above-mentioned two multiplexers restore the logic amplitude, such as a buffer, an inverter or a multi-input logic gate. Directly without inserting circuit elements for
They are connected in series. If the maximum allowable number of pass transistors is three or more, three or more unit multiplexers are directly connected in series.

The logic circuit shown in FIGS. 35-40 is a logic circuit optimized by the combination type method (FIG. 21-2).
It contains fewer multiplexers than 6). Especially,
The number of multiplexers used to map the logical group containing the superior variable has been reduced. Furthermore, the multiplexer in the logic circuit according to the present embodiment has one more multiplexer than the logic circuit optimized by the combination type method in which many two-stage multiplexers are used to map a logic group including multiple high-order variables. Used to map a logical group containing two super variables. However, on the other hand, many multi-input logic gates are used. In particular, there are more multi-input logic gates for mapping logic groups that include one or more common variables. For a logic circuit optimized by the combination type method, each multi-input logic gate used to map a logic group that includes one or more common variables receives only one common variable. On the other hand, in the logic circuit according to the present embodiment, up to four common variables are input to the multi-input logic gate. This is a characteristic aspect of a logic circuit configured by mapping a given logical expression optimized by the common variable method.

In the logic circuit of this embodiment, a multiplexer composed of a pass transistor and a multi-input logic gate is connected in various ways so that a given logic equation is efficiently embodied.

FIGS. 41 and 42 show flowcharts of the above processing according to the second embodiment. Here, a single flowchart is divided into two in FIG. 41 and FIG. 42 for convenience of drawing.

Assuming that the number of input variables of the logical expression to be optimized in this embodiment is n and the number of product terms is m, the first cycle can be performed in a calculation time of the following formula (10). it can.

O (2 _nm C ₂ ) (10)

In the expression (10), _m C ₂ is the number of combination types for selecting _{two out} of m sets. In the second and subsequent cycles, m becomes (１ ／) of the previous value, so that the processing can be performed in about (１ ／) of the previous calculation time. In general, this method requires much less computation time than the combination type method. The calculations required in the present embodiment are simple comparisons, are easy for computer processing, and are easy to incorporate into a CAD system. The program shown in the flowcharts of FIGS. 41 and 42 is an example of a program for verifying an algorithm, and therefore, the match is checked for each bit. However, in the actual processing, the AND operation of two rows is performed once. It can be executed by

In the second embodiment, only the grouping process by the common variable method is repeatedly performed, and a given logical expression such as Expression (2) is converted to the lowest product term as Expression (9). Optimized to a state where there is no common variable in between. However, the present invention is not limited to this embodiment. For example, the grouping process using the common variable method can be performed in combination with the grouping process using another method.

Next, a third embodiment will be described. In the third embodiment, optimization is performed by a top-down common variable method.

This embodiment is different from the second embodiment in that
Group from top to bottom, not bottom to top. The basic processing of the present embodiment is as follows. That is, the product terms in a given logical expression are combined into 2 ^v groups corresponding to the maximum number v of pass transistors. For example, if v = 2, the product terms are combined into four groups. In this grouping process, t product terms are grouped. Here, t is (m /
4) It is a minimum integer equal to or greater than 4). In this way, the product terms are grouped in pairs from the larger number of common variables to the smaller number. This grouping process is repeated until the given logical expression is optimized and there is no common variable in each group or until the final form of t = 1. In the present embodiment, as described above, when v = 2, the product terms are combined into four groups. This is for converting a given logical expression into a fully optimized form in consideration of the configuration of the two-stage multiplexer.

Assuming that the number of input variables of the logical expression to be optimized in this embodiment is n and the number of product terms is m, the first cycle can be performed in a calculation time of the following formula.

O (2 _nm C _t ) (11)

From the equation (11), it can be seen that when the number of product terms is too large, the calculation time becomes extremely long. Further, it is necessary to appropriately select the number of combination types according to the number of product terms.
FIGS. 43 to 45 show variable tables in the case where the number of combination types in the group is too large compared to the number of product terms, for example, when m = 8 and t = 3. This table is divided into FIGS. 43 to 45 for convenience of drawing. As is apparent from the table, when m = 8 and t =
The number of combinations of product terms for 3 is greater than that in the bottom-up common variable method (FIGS. 31 and 32). These combinations increase the computation time required to determine the number of common variables. On the other hand, the maximum number of common variables is 3,
It is smaller than 6 in the variable tables shown in FIGS. 31 and 32. As can be seen from this example, if the number of product terms that are grouped together is inappropriate, the computation time required for the top-down It is longer than the time. Further, the number of common variables is rapidly reduced, and the AND term is dispersed, which is not preferable. This point is not a problem if the number of product terms to be grouped is appropriately selected, that is, if t = (8/4) = 2.

Hereinafter, the maximum number of pass transistor stages is 2
The difference between the bottom-up common variable method and the top-down common variable method will now be described, taking the case where the number of product terms is 32 as an example.

In the bottom-up common variable method, grouping is performed by using a common variable between two product terms. Thus, the first grouping process produces 16 groups, which are half the number of product terms. Next, assuming that common variable as a product term,
After the second optimization cycle, the number of groups becomes eight, which is half of the previous value, since further grouping is performed using the common variable between only two product terms. Similarly, the number of groups becomes four after the third cycle, two after the fourth cycle, and one after the fifth cycle.

In the top-down common variable method, the product terms are divided into four groups in each cycle. In the first cycle, the eight product terms are grouped using their common variables to form four groups. Next, the logical functions in each group are regarded as a newly given logical expression, and further grouping is performed. In the second cycle, the eight product terms in each group are divided into four groups, so that four groups are created using the common variables of the two product terms. When the second cycle is completed, there is no common variable in any group, so that all optimization processing is completed.

In this example, in both the first and second grouping processes, logical expressions having product terms that are multiples of 2 ^v are grouped, so that the number of product terms is exactly divided by 2 ^v . There are 2 ^v groups each of which is a set of product terms of the minimum integer greater than the quotient. However, if the number of product terms is 2 ^v
If it is not a multiple of, a group of integers in which the number of product terms is smaller than the minimum integer greater than or equal to the quotient occurs. Furthermore, even if the number of product terms is a multiple of 2 ^v , if there is no common variable common to the product terms of the minimum integer greater than or equal to the quotient, the number of product terms in each group is It is smaller than the minimum integer greater than the quotient. Also, there may be ungrouped product terms.

Next, a method for designing a logic circuit according to the fourth embodiment of the present invention will be described. In the fourth embodiment, the aforementioned common variable / combination type method is adopted.

In the combination type method, a given logical expression is optimized in a form suitable for using a multiplexer. In contrast, the common variable method is logical AND and NAN.
D operations are grouped. Therefore, the combination type method and the common variable method have contradictory parts. In contrast to the common variable method that prevents the variance of common variables, in the combination type method in which variables are grouped so that the number of variable combinations increases, the common variables are dispersed.

By paying attention to the above points, the common variable / combination type method of the present embodiment incorporates the advantages of both the combination type method and the common variable method. That is, first, grouping is performed by the common variable method to prevent variance of common variables, and then the common variable obtained by grouping by the common variable method is regarded as a new product term (deemed product term). Perform grouping with. When the common variable method is performed from the bottom up, the first cycle of the optimization process is performed as shown in FIGS.
This is performed according to the variable table shown in FIG. 33 according to the variable table shown in FIG. The logical expression is n input variables and the number of product terms is m
If the number is included, the calculation time of the first cycle is about the following equation (12).

O (2 _nm C ₂ ) (12)

Optimization processing when the combination type method is applied to the deemed product term obtained in the first processing by the common variable method is performed according to the variable table shown in FIG. Since the variable d does not exist in the deemed product term, the variable d
Has been omitted. In FIG. 46, the maximum allowable number of stages of the pass transistor is two (v = 2). However, since the number of assumed product terms is reduced to (に) of the initial number, the product terms of The number is not (v + 1) but v. In the third row from the bottom, there is a sufficient difference between the variables of the maximum occurrence count. Judging from the maximum number of combinations and the number of occurrences shown in this table, the variable a
The candidate, variable c, becomes the second candidate. However, since the maximum value of the number of combination types is 2, the grouping does not take the form of a logical group including two multiple upper variables mapped to the two-stage multiplexer. Therefore, only the variable a having the maximum number of occurrences is selected as a higher-level variable, and grouping is performed. The calculation time required for this processing is sharply reduced to about the following equation (13).

O ((m / 2-1) _n P _v + n ² ) (13)

When the product terms in each group are further grouped by the combination type method, the logical expression is optimized in the following form.

[0238]

(Equation 9)

With respect to the optimized logical expression (14),
When the primary mapping process according to the fifth embodiment described later and the logical level matching according to the sixth embodiment are performed, FIGS.
A logic circuit as shown in FIG. Here, one logic circuit is divided into FIGS. 47 to 52 for convenience of drawing,
Symbols S41-S50 are used to describe the signal connections of the logic circuit. In the optimization processing of the present embodiment, the original logical expressions are first grouped by the common variable method, and then grouped by the combination type method. Therefore, the upper variable is specified in the equation (14). Thus, equation (14) can be mapped to a logic circuit in a form suitable for using a multiplexer. However, in the equation (14), the upper variable of the group having the logical function sharing the common variable formed in the first processing by the common variable method is not specified. 47 to 52
In obtaining the logic circuit shown in (1), additional processing is performed so that the above-described portion is configured using a multiplexer. In the example of equation (14), the process of modifying the circuit so that similar parts are shared is unnecessary. In this logic circuit, the number of transistors used is 123, and the maximum number of signal path stages is eight. Although this logic circuit is not the optimal solution, good results have been obtained. The number of transistors used is almost the same as that of the circuit obtained by the combination type method, but the number of pass stages is reduced. This logic circuit includes 13 unit multiplexers, 12 multi-input logic gates, and one inverter.

This logic circuit includes seven one-stage multiplexers for mapping a logic group including upper variables. That is, the logic circuit portion shown in FIG. 48 is provided with a one-stage multiplexer in which the upper variable d is input to its control terminal and the product term mapped by different multi-input logic gates is input to each input terminal. I have. FIG.
Is provided with a one-stage multiplexer in which a higher-order variable d is input to its control terminal and signals S41 and S42 are input to respective input terminals. FIG.
Is provided with a one-stage multiplexer in which the upper variable d is input to its control terminal and the signals S43 and S44 are input to each input terminal. FIG.
Is provided with a one-stage multiplexer in which the upper variable b is input to its control terminal and the signals S45 and S46 are input to each input terminal. Furthermore,
In the logic circuit portion shown in FIG. 52, three one-stage multiplexers are provided. In one of the multiplexers, the upper variable g is input to its control terminal and the signal S47
And S48 are input to each input terminal. In another multiplexer, the upper variable j is input to its control terminal, and the signals S49 and S50 are input to each input terminal. In the third multiplexer, the upper variable a is input to its control terminal, and the signals output from the two multiplexers are input to each input terminal.

The three multiplexers shown in FIG.
They are connected in series to form a stage multiplexer. However, different higher-level signals are input to the control terminals of the two multiplexers in the first stage. Therefore, these multiplexers are not used to map logical groups containing multiple high-order variables.

That is, three multiplexers each used to map a logical group including one upper variable are connected in series, forming a two-stage multiplexer. Since this logic circuit is designed under the condition that the maximum allowable number of stages of the pass transistor is 2, the three multiplexers are used to recover logic amplitudes such as buffers, inverters and multi-input logic gates. They are directly connected in series without inserting circuit elements.

The logic circuit also includes four multi-input logic gates for mapping logic groups containing common variables. That is, in FIG.
An ND gate is used to receive the common variables b bar, c bar, f, h at its input terminal and outputs a signal S47 from its output terminal. In FIG. 49, a three-input NAN
A D-gate is used to receive the common variables e and i at its input terminal and outputs a signal S48 from its output terminal. In FIG. 50, a three-input NAND gate is used to receive common variables b, c, and i at its input terminals, and outputs a signal S49 from its output terminal. In FIG. 51, a three-input NAND gate is used to receive common variables c, e, and f at its input terminals,
The signal S50 is output from the output terminal. Further, FIG.
In the logic circuit portion shown in FIG.
There is a gate. In the first three-input zero AND gate, one input terminal is connected to the multiplexer, and a signal S41 is output from the output terminal. In the second three-input zero AND gate, one input terminal is connected to the multiplexer, and a signal S42 is output from the output terminal. The remaining four 3-input zero AND gates output the output signals S43, S44, S45 and S4 from their output terminals.
6 is output. Each of these six three-input zero AND gates is used to map a product term that contains only variables that are logically independent of one another.

The logic circuit shown in FIGS. 47-52 uses fewer multiplexers than the logic circuit obtained by the combination type method (FIGS. 21-26). In particular, fewer multiplexers are used to map logical groups that include higher variables. However, compared with the logic circuit obtained by the common variable method (FIGS. 35-40), it includes many multiplexers. In particular, common variables /
The logic circuit based on the combination type method includes a complete two-stage multiplexer which does not exist in the logic circuit obtained by the common variable method. On the other hand, a logic circuit based on the common variable / combination type method uses fewer multi-input logic gates than a logic circuit obtained by the common variable method. Especially,
Fewer multi-input logic gates for mapping logic groups that include multiple common variables. However, the number of multi-input logic gates is more than that of a logic circuit obtained by the combination type method. As described above, the logic circuit according to the fourth embodiment has a configuration in which the advantages of the combination type method and the common variable method are both achieved. Further, FIG.
In the logic circuit portions 50 and 51, a composite pass transistor logic circuit is used. Therefore, the logic circuit according to the present embodiment has a circuit configuration in which the advantage of the composite pass transistor logic circuit is achieved. In addition to the complex pass transistor logic circuit, the logic circuit includes a circuit configuration in which the pass transistor logic circuit and the multi-input logic gate are combined in various ways. For example, in the case of the two-stage multiplexer shown in FIG.
Signals S47-S output from different multi-input logic gates
50 are respectively input. These signals are logically independent of each other. On the other hand, the input terminals of the multiplexers shown in FIGS. 50 and 51 are respectively provided with signals S43, S44,
And S45 and S46 are input. Here, the signals S43 and S44 are logically independent of each other. Similarly, signals S45 and S46 are logically independent of each other. As described above, a logic circuit designed according to the present invention has a circuit configuration including a pass transistor and a multi-input logic gate combined in various ways, and as a result, the advantages of both circuit elements can be utilized. Have been.

In the above example, there is no significant difference in the number of transistors and the number of pass stages between the logic circuit designed by the common variable / combination type method and the logic circuit designed by the common variable method. However, this is because the given formula is not very complicated. In the case of a more complicated logical expression used in actual design, the common variable / combination type method according to the present embodiment has fewer transistors and lower power consumption than the common variable method. Furthermore, in the method according to the present embodiment, the calculation time required to obtain the logic circuit from the optimized logic formula and the optimized logic formula is short. Thus, a large-scale logic circuit can be designed in a short time.

In this embodiment, as described above, grouping is first performed by the bottom-up common variable method, and then grouping is further performed by the combination type method. However, the invention is not limited to this combination. For example, the first grouping process may be performed by a top-down common variable method, and then the combination type method may be performed. Further, the number of grouping processes performed by the common variable method is not limited to one. That is, the grouping process using the common variable method may be performed a plurality of times before performing the combination type method. However, once or twice is usually sufficient to achieve the benefits of the common variable / combination type method. Conversely, grouping by the combination type method may be performed first, and then grouping by the common variable method. In this case, the processing time required for the first grouping process by the combination type method is O ((m−1) _n P _{v + 1} +
a _n n P _v) degree. In the subsequent processing by the common variable method, the number of product terms to be processed and the number of variables are reduced by the preceding grouping processing by the combination type method.
Processing time is short.

Further, the upper variables and the common variables are specified according to a method other than the combination type method and the common variable method described above with reference to the first to third embodiments, and then the specified upper variables and the common variables are specified. The logical expression may be optimized using variables.

In each of the first to fourth embodiments described above, the given logical expression to be optimized is a sum of product terms each including only variables, as in Expression (2). Was assumed. Either method described is generally very efficient if the given logical expression is in the form of a sum of product terms, each containing only variables. Therefore,
When the given logical expression includes a logical function that is not a simple product of variables, the given logical expression is first expanded to include only the product of variables, and then the first to fourth implementations are performed. It is desirable to perform any optimization processing of the form. However, if a given logical expression includes a logical function that can be efficiently mapped to a particular circuit configuration (eg, a multiplexer), the logical function is not expanded and the other logical expression The optimization may be performed for this.

Next, a method for designing a logic circuit according to the fifth embodiment of the present invention will be described. In the fifth embodiment, a given logical expression is mapped to a logical circuit by a primary mapping process that does not consider inversion of the logic.
Specifically, mapping is performed using a non-inverting logic gate such as an AND gate or an OR gate.

The primary mapping processing according to the present embodiment is as follows.
It is desirable to perform the optimization on the logical expression optimized by any of the methods disclosed in the first to fourth embodiments. However, the optimization can be performed by another method. Depending on the logical expression, the optimization may not be required.

In the present embodiment, first, the product terms of the lowest group are mapped in a form suitable for using an AND gate and a pass transistor. Specifically, the number of variables included in the product term of the lowest group is two or more, and
If the number of input terminals of the D gate is less than the maximum allowable number (for example, three), an AND gate is arranged in the logic circuit, and the variable of the product term is connected to the input terminal of the AND gate. If the number of variables is four or more, a pass transistor whose output terminal is connected to the input terminal of the AND gate is added to the AND gate.
Connect appropriate variables to the input and control terminals of the pass transistor. For example, if pass transistors are added to all input terminals of a three-input AND gate, a product term including up to six variables in total can be mapped. If each pass transistor has two stages, it is possible to map product terms including up to nine variables in total. When the pass transistor combined with the AND gate is configured in the form of a unit multiplexer having a circuit configuration as shown in FIG. 10, the input terminal to which no variable is input is fixed at a logic level "0". The term of the lowest group is
If only one variable is involved, no mapping for that term is needed at this stage. This variable is input directly to the next stage of the logic circuit.

After mapping all the product terms of the lowest group by the above method, mapping is further performed for the second group from the lowest.

For example, if the two product terms in the lowest group share the upper variable, the logical group in the second group from the lowest includes this higher variable. In this case, a multiplexer is arranged in the logic circuit, two product terms are input to an input terminal of the multiplexer, and a higher variable is input to a control terminal. At this time, if three or more terms share multiple high-order variables, a multiplexer having two or more stages (within the range allowed as the number of stages of the pass transistor) is arranged in the logic circuit, and the high-order variables are , And the product term is input to each input terminal. If the next-level logical group includes higher-level variables, a multiplexer is arranged in the next stage until the number of stages becomes equal to or greater than the maximum allowable number. For example, the logical expression given by the following expression (15) is
According to the method of the present embodiment, the data is mapped to the logic circuit shown in FIG.

[0254]

(Equation 10)

In equation (15), the inside of the four parentheses is the lowest group. They are the variable c and the product terms de, fggh, and ijkl, respectively. Of these, the second and third product terms contain two and three variables, respectively, so these two product terms are each mapped using one independent AND gate. . Since the fourth product term contains four variables, this product term is mapped using a combination of an AND gate and a multiplexer. In the next higher level logical group, the above four terms share two multiplex upper variables a and b, so that further mapping is performed using a two-stage multiplexer. Here, a term c containing only one variable
Is directly input to the input terminal of the two-stage multiplexer.

In the logic circuit shown in FIG.
The higher-order variable b is input to the unit multiplexers in the stages. Terms c and de · e that share the upper variable b are input to each input terminal of one unit multiplexer, and product terms f · g that also share the upper variable b are input to each input terminal of the other unit multiplexer.・ H and i · j · k · l are input. Also, a higher-level variable a is input to the control terminal of the unit multiplexer at the last stage, and a logical function sharing the higher-level variable a is input to each input terminal.

[Outside 21] Is entered.

When a set of product terms shares a common variable, A is set so that logical groups sharing the common variable are mapped.
An ND gate is arranged, and a common variable and a sum of product terms sharing the common variable are input to each input terminal of the AND gate. When the number of common variables is large, a pass transistor is combined with the AND gate, and the output terminal of the pass transistor is connected to the input terminal of the AND gate. If the higher group has a common variable, the mapping is performed in a similar manner using an AND gate. Hereinafter, the same mapping is repeatedly performed up to the highest-order group, thereby completing the primary mapping process. For example, when the maximum allowable number of pass transistor stages is two, the following (16)
When the method of this embodiment is applied to a logical expression given by an expression, a logical circuit as shown in FIG. 54 can be obtained.

[0258]

[Equation 11]

In the logic circuit shown in FIG.
Two of the three input terminals of the AND gate at the stage
Common variables b, c, and d are input. That is, the common variable d is input to one input terminal, and bc is input to the other input terminal via the unit multiplexer. Yet another input terminal is used to input a logical function that is the sum of four product terms that share common variables b, c, and d. Product term

[Outside 22] Is mapped to the previous stage using a two-stage multiplexer, taking into account the fact that this sum is a logical group with two multiple upper variables e and f. In this example, the common variables are shared by product terms that contain only variables. In practice, common variables may be shared by more complex logic functions.

In this example, a three-input AND used to map logical groups with common variables
One of the input terminals of the gate is connected to a two-stage multiplexer, and the sum of logic functions sharing a common variable is a three-input AN.
It is input to the input terminal of the D gate. As a result, the number of remaining input terminals that can be used to receive the common variable is two (here, the maximum allowable number of input terminals is assumed to be three). Therefore, a unit multiplexer is connected to one of the remaining input terminals, and three common variables are input to the AND gate. Therefore, the number of unit multiplexers required for combination with an AND gate is determined by the total number of common variables and the sum of logic functions sharing this common variable. In other words, instead of using the number of variables included in the product term as an index, a logical function (in this example, a sum of logical functions sharing a common variable) and a variable included in the product term (in this example, a common variable)
, The number of unit multiplexers needed to map the product terms in the non-least significant group can be determined in a manner similar to mapping the lowest level product term. it can.

More generally, a variable is a logical function of 1
Since it is a seed, mapping of a product term including a plurality of logic functions can be performed using an AND gate and a number of unit multiplexers determined according to the total number of logic functions included in the product term. At this time, regardless of whether all of the logical functions included in the product term are simple variables, or whether some or all of the logical functions are complex logical functions, the unit multiplexer is operated in a similar manner. Can be determined. If some of the logical functions in the product term are products of lower logical functions, the number of such lower logical functions should be included in the count.

In the above example, A is used as a multi-input logic gate.
Only ND gates are used. However, in practice, depending on the particular formula to be mapped, A
Various types of multi-input logic gates can be used, including ND gates. For example, an OR gate can be used to map a logical group having a plurality of independent groups as in the form of Expression (21) described later. On the other hand, a buffer can be inserted to deal with the limitation on the number of pass transistor stages. Further, when the multiplexer is arranged at the last stage of the circuit, a buffer can be added to the output terminal of the multiplexer in order to increase the driving capability or restore the logic amplitude.

Next, a method for designing a logic circuit according to the sixth embodiment of the present invention will be described. This embodiment deals with the above-described logic level matching.

In the CMOS logic gate, the AND gate usually has a configuration in which an inverter is added to a NAND gate. Therefore, the delay time of the AND gate is longer than that of the NAND gate, the number of transistors is increased, and the power consumption is increased. Similarly, the OR gate has N
Compared with the OR gate, the delay time becomes longer, the number of transistors increases, and the power consumption increases. Therefore, NAN
It is desirable to use a D gate or a NOR gate. However, the logic circuit obtained by the primary mapping of the fifth embodiment uses an AND gate or an OR gate as a multi-input logic gate. Therefore, it is desirable to improve the logic circuit obtained in the fifth embodiment by performing the logic level matching according to the sixth embodiment. Improvement is AN
This is achieved by replacing the D gate or the OR gate with a NAND gate or a NOR gate. For the same reason, the buffer is replaced by an inverter. Further, the mismatch of the logic level caused by the inversion of the logic level by the NAND gate, the NOR gate, and the inverter is adjusted.

In the present embodiment, for example, a logic circuit obtained by the mapping according to the fifth embodiment is replaced with a multi-input AN.
A positive logic area and a negative logic area are divided by a D gate, an OR gate or a buffer, and a positive (negative) logic area and a negative (positive) logic area alternate from the output side to the input side of the logic circuit. Arrange so that The polarity of the last stage is determined in consideration of whether a given logical expression is in a positive or negative logical form. In the negative logic area, the logic of the direct input signal is inverted, and the logic of the signal input to the input terminal of the multi-input logic gate on the output side of the negative logic area is further inverted.
The logic of the signal output from the output terminal of the multi-input logic gate on the input side of the negative logic area is inverted. Therefore, the AND gate on the output side of the negative logic area is a zero AND gate, that is, N
Replaced by an OR gate, which is replaced by a zero OR gate or NAND gate. On the other hand, the AND gate on the input side of the negative logic area is replaced with a NAND gate, and
The R gate is replaced by a NOR gate. The buffer is replaced with an inverter.

Here, the "direct input signal" refers to a variable or a constant that is directly input to an input terminal of a multiplexer or a multi-input logic gate, not a signal supplied from a preceding multi-input logic gate or inverter. Here, the “constant” refers to a signal whose logic level is fixed, that is, a signal of “1” or “0” logic level. As a fixed level,
For example, a ground potential (GND) or a power supply potential (VDD) is used.

When the logical expression (17) is linearly mapped according to the fifth embodiment, a logical circuit of the form shown in FIG. 55 is obtained. This logic circuit is converted into the form shown in FIG. 56 by the logic level matching of the present embodiment. In order to make the comparison between the logic circuit and the logic expression easy to understand, the expression (17) is slightly redundant.

[0268]

(Equation 12)

In the equation (17) and the example shown in FIG. 55, since the output W is in the positive logic form, the area between the AND gate G11 and the AND gate G12 is set to the negative logic area. Therefore, A
Replace the ND gate G12 with a zero AND gate, and
The gate G11 is replaced with a NAND gate. Further, the input signals a and c are directly inverted, and a constant “1” input to the input terminal of the multiplexer M11 and the multiplexer M12
Of the constant "0" input to the input terminal of "1" is inverted.
Others remain unchanged. Thus, the logic circuit of FIG. 56 can be obtained.

In equation (17), the group hi · i + h bar in parentheses that is most deeply enclosed can be easily rewritten as i + h bar. This group is a “logical group having a plurality of independent lower logical groups”, which will be described later, and can be mapped using an OR gate. However, in this example, a multiplexer having an OR configuration (a first-stage multiplexer whose control terminal is coupled to input a variable h) is employed. This OR
The configuration multiplexer will be described later in detail with reference to FIG. Similarly, groups

[Outside 23] Are mapped using an OR configuration multiplexer (the second-stage multiplexer counting from the last stage, the control terminal of which is coupled to input the variable d). As in the above example, a logical group represented by the sum of one variable and one logical function is efficiently mapped using an OR configuration multiplexer. Here, a variable is input to its control terminal, a logical function (a part obtained by removing the variable from the product term) is input to one input terminal, and a constant is input to the other input terminal. According to this method, two inputs O
The number of stages can be reduced as compared with the case where an R gate is employed. In the example shown in FIG. 55, a variable (h bar or d bar) expressed in the negative logic form in Expression (17) is input to the control terminal in a positive logic form, and the logical function i or

[Outside 24] Is input to the input terminal X. Further, a constant “1” is input to the input terminal Y. As a result, an inverter for inverting a variable is not required, and the number of transistors can be reduced.

The logic circuit shown in FIGS. 21 to 26, FIG.
The logic circuits shown in FIGS. 40 to 40 and the logic circuits shown in FIGS. 47 to 52 are all subjected to the logic level matching according to the present embodiment. The logic equation corresponding to the logic circuit after the logic level matching can be further improved by using another appropriate algorithm. For example, utilizing the BDD, sharing nodes that have the same logic, replacing multiple nodes with a single node, or converting some variables to obtain an equivalent and simple expression good.

The logic level matching according to the present embodiment corresponds to the fifth
The present invention can be applied to a logic circuit obtained by a primary mapping process using an appropriate method other than the embodiment. For example,
In the fifth embodiment, the mapping is performed from the lowest group to the higher group. Instead, the mapping is performed from the highest group to the lower group, and the resulting logic is calculated. The logic level matching according to the present embodiment can be performed on the circuit.

Hereinafter, a method for designing a logic circuit according to the seventh embodiment of the present invention will be described.

In this embodiment, the primary mapping according to the fifth embodiment and the logic level matching according to the sixth embodiment are performed not simultaneously but as separate steps. In the present embodiment, a fifth bottom-up mapping from the lowest group to the higher group is further performed.
Contrary to the embodiment, a top-down mapping is performed for mapping from the highest group to the lower group. In this embodiment, the highest-order group in a given logical expression is mapped first, and each group is mapped in order toward the lowest-order group.

For the uppermost group, four different types of mappings (hereinafter referred to as first to fourth types) described below are performed according to the configuration of the uppermost group in a given logical expression. Will be

First, the first type is a case where the highest-order group is composed of only logical functions sharing one or more higher-order variables. In this case, a multiplexer having an inverter on the output side is arranged at the last stage. For example, the logical expression (18) of the positive logical output having the upper variable a is mapped to the logical circuit in the form shown in FIG. If there are a plurality of upper variables, a multi-stage multiplexer is used.

[0277]

(Equation 13)

The second type is a case where the highest-order group includes only one logical function having a common variable. In this case, if the output is of a positive logic type, a zero AND gate, that is, a NOR gate is arranged at the last stage, and if the output is of a negative logic type, a NAND gate is arranged. Common variables b and c
Is shown in the equation (19). In the equation (19), the logical function H is represented by the sum of a plurality of lower logical functions sharing the common variables a and b. When the expression (19) is mapped in the present embodiment, a logic circuit having the form shown in FIG. 58 can be obtained. If the number of common variables is equal to or larger than the maximum allowable number of input terminals of the multi-input logic gate, a multiplexer having one input terminal as a constant input is added as in the case of the primary mapping processing according to the fifth embodiment. .

U = b · c · H (19) H is an arbitrary logical function

Next, the third type is a case where the highest-order group includes only one logical function having no common variable. In this case, an inverter is arranged at the last stage. An example of a logical expression whose output is a positive logical format is shown in Expression (20). As a special example in this case, as in the first type, the logical function may have a logical group including a higher-order variable. When the expression (20) is mapped in this embodiment, a logic circuit having the form shown in FIG. 59 is obtained.

U = I (20) I is an arbitrary logical function

Next, the fourth type is a case where the uppermost group includes a plurality of independent lower logical groups. In this case, if the output is in positive logic form, a zero-OR gate, ie, N
An AND gate is arranged at the last stage. On the other hand, if the output is of a negative logic type, the NOR gate is arranged at the last stage. Here, the “independent logical group” includes not only a literally independent logical group but also a group having different upper variables, a group having different common variables, and a mixture of these. An example is shown in equation (21). When this equation (21) is mapped in this embodiment, a logic circuit having the form shown in FIG. 60 is obtained.

U = J + K + L (21) J, K and L are arbitrary logical functions

In the fourth type, the highest-order group is
If there are many independent sub-groups, the above N
An OR configuration multiplexer with one input terminal connected to input a constant signal or a NOR gate is added to the AND or NOR gate. For example, when a multiplexer having an OR configuration is added to the logic circuit of FIG.
It becomes like the logic circuit shown in FIG. On the other hand, when a NOR gate is added, a logic circuit shown in FIG. 62 is obtained.
The logic circuits shown in FIGS. 61 and 62 are of positive logic.

In the multiplexer shown in FIG. 61, when J is in the valid state (H state), the constant input "GND" becomes valid, and the output of the multiplexer becomes valid (L state). When J is in an invalid state, the output of the multiplexer becomes valid (L state) if K bar is valid (L state). That is, if either J or K is valid, the output of the multiplexer is valid. For this reason, this multiplexer is called an "OR configuration multiplexer". In the example of FIG. 61, since the input of the NOR gate is of a negative logic type, a multiplexer configured to have a NOR logic is used. If the input of the NOR gate is of a positive logic type, a multiplexer configured to have an OR logic can be used. Both are OR configuration multiplexers.

In each of the above examples, the attenuation of the logic amplitude caused by the pass transistor logic circuit is restored, and the final stage drives the next stage circuit such as another logic circuit, a sequential circuit, or a storage circuit. In order to have sufficient capacity, an inverter or a multi-input logic gate is arranged at the last stage.

After the mapping processing of the uppermost group is completed, mapping to the lower-level group is further performed as described below.

In this processing, starting from the second highest group, each group is sequentially mapped to the lowest while maintaining the number of stages of the pass transistors within the allowable range. In this mapping process, a positive (negative) logic area and a negative (positive) logic area are alternately formed with the inversion type multi-input logic gate or inverter as a boundary from the output side of the logic circuit toward the input side. Go.

The processing here is basically the same as that of the fifth embodiment except that the logic level matching is performed at the same time.
Specifically, a logical group having an upper variable is mapped by inputting the upper variable to a control terminal of a multiplexer composed of a combination of pass transistors. On the other hand, the group having a common variable is input to the input terminal of the NAND gate when the common variable is input from the positive logic area, and is set to NOR when the common variable is input from the negative logic area.
It is mapped by inputting to the input terminal of the gate. In the above mapping, the lower group represented by the sum of the logical functions sharing the common variable,
Input to one input terminal of the AND or NOR gate, and the common variable is mapped to input to the remaining input terminal of the NAND or NOR gate. The direct input signal is
The signal is input as it is to the positive logic area, and is inverted and input to the negative logic area. If there are many common variables and not all of the common variables can be directly input to the multi-input logic gate, add a multiplexer with one input terminal connected to input a constant. To enter through. In this case, when the multiplexer is arranged in the positive logic area, the variable is directly input and the constant is “G”.
On the other hand, if the multiplexer is arranged in the negative logic area, the variable is input after inversion, and the constant is “VD”.
D "signal. The least significant product term is similarly mapped using all the input terminals of the NAND gate or NOR gate.

When the above-described logical expression (14) optimized by the common variable / combination type method of the fourth embodiment is processed by the top-down mapping of the seventh embodiment, FIGS.
8 is obtained. Here, one logic circuit is divided into FIGS. 63 to 68 for convenience of drawing. In the equation (14), the highest-order group is a logical group having a higher-order variable a. Therefore, the inverter is arranged at the last stage, the multiplexer is arranged at the input side of the inverter, and the upper variable a is input to the control terminal of the multiplexer.

Although this logic circuit has some differences in small points, after the bottom-up primary mapping processing,
This is basically the same as the logic circuit shown in FIGS. 47 to 52 obtained by performing the logic level matching. Sign S
Signals denoted by 41'-S50 'correspond to signals S41-S50 in the logic circuits shown in FIGS. The number of transistors used and the maximum number of signal path stages are the same as those in the circuits shown in FIGS. However, the logic circuit obtained in the present embodiment may be different from the logic circuit obtained by performing the logic level matching after the primary mapping according to the given logic formula.

The logic circuit obtained by performing the logic level matching with the primary mapping according to the fifth and sixth embodiments, or by performing the top-down mapping according to the seventh embodiment, can have various unique circuits. Including configuration.

In the logic circuit shown in FIGS. 21 to 26 obtained by applying the primary mapping to the logic equation (5) optimized by the combination type method and then performing logic level matching, FIG. The portion indicated by reference numeral 22 has a circuit configuration of a NOR gate, a pass transistor logic circuit (multiplexer), and a NAND gate from the input side to the output side. That is, in FIG. 22, the output of the two-stage multiplexer is a two-input N which outputs the signal S19.
Signals S11, S12 and 13 connected to one input terminal of the AND gate and generated by three 3-input NOR gates (zero AND gate) shown in FIG.
Are input to three input terminals of a two-stage multiplexer. This circuit configuration includes, for example, a plurality of lower logical functions sharing a common variable, and the sum of the lower logical functions is a lower logical group having an upper variable shared by a plurality of product terms. Appear inevitably when mapped according to the present invention. That is, the NOR gate in FIG. 21 maps the product term. Further, the multiplexer in FIG. 22 maps a lower logical group. And, in FIG.
The ND gate maps a logical group by inputting a common variable and a lower logical group to its input terminal. In the primary mapping process, AND
Gates are arranged as multi-input logic gates.

In this case, since the multiplexer is arranged in the positive logic area, the multi-input logic gate for mapping the product term is replaced by a NOR gate.
Multi-input logic gates for mapping logic groups are replaced by NAND gates. If the multiplexer is located in the negative logic area, the NAND as a multi-input logic gate for mapping the product term
Gates are employed, and NOR gates are employed as multi-input logic gates for mapping logic groups.
In this case, the circuit comprises NAND gates arranged from the input side to the output side, pass transistor logic circuits, and N
It has an OR gate configuration. Such a circuit configuration appears in the logic circuit shown in FIG. Similarly, when the mapping and the logic level matching are performed simultaneously, one of the circuit configurations is obtained depending on whether the multiplexer is arranged in the positive logic area or the negative logic area.

In the above example, each product term mapped by the NOR gate contains only variables. However, in general, the product terms include logic functions. For example, in the logic circuit shown in FIGS. 35 to 40 obtained by mapping the logic expression (9) optimized by the common variable method, the NAND gates arranged from the input side to the output side , Pass transistor logic circuit, N
A circuit configuration including an OR gate, a pass transistor logic circuit, and a NAND gate has appeared. For example, FIG.
In the example, the output of the one-stage multiplexer is input to one input terminal of a two-input NAND gate that outputs a signal S33. 3-input NOR shown in FIGS. 35 and 36
The signal S generated by the gate (zero AND gate)
31 and S32 are the two-stage multiplexers of FIG.
Input to two input terminals. Further, the output of the other one-stage multiplexer is input to one input terminal of the NOR gate, and the output of the three-input NAND gate is input to two input terminals of these other one-stage multiplexers. .

In this circuit configuration, for example, the mapping method according to the present invention comprises a plurality of lower logical functions sharing a common variable, and the sum of the lower logical functions is the upper variable shared by a plurality of product terms. , Wherein each product term is the product of a lower common variable and a second lower logical group having lower higher variables shared by a plurality of lower product terms. Inevitably appears when applied to logical expressions with groups. That is, the NAND gates in FIGS. 35 and 36 map the lower product terms. The multiplexers of FIGS. 35 and 36 map the second lower logical group, and each NOR gate of FIGS. 35 and 36 maps the product of the lower common variable and the second lower logical group. ing. The multiplexer in FIG. 37 maps a lower logical group, and the NAND gate in FIG. 37 maps a logical group. A similar circuit configuration can be obtained even when mapping and logic level matching are performed simultaneously.

Depending on which part of the circuit becomes the positive logic area or the negative logic area, N
A circuit configuration in which an OR gate, a pass transistor logic circuit, a NAND gate, a pass transistor logic circuit, and a NOR gate are arranged also occurs. When a large-scale logical expression is mapped, a configuration appears in which NAND gates and NOR gates are alternately arranged via pass transistor logical circuits over many stages.

Next, a description will be given of a method of designing a logic circuit not including a multi-input logic gate according to the eighth and ninth embodiments of the present invention. Here, the processing in step S14 (primary mapping processing) and the processing in step S16 (logical level matching processing) shown in FIG. 7 will be described. Processing for simultaneously executing mapping and logical level matching will also be described. The optimization in step S12 can be performed by, for example, any one of the first to fourth embodiments or another technique. The optimization according to the methods disclosed in the first to fourth embodiments is not limited to a logic circuit including both pass transistors and a multi-input logic gate, and may be designed when a logic circuit not including a multi-input logic gate is designed. , Can be implemented.

First, an eighth embodiment will be described. In the present embodiment, as in the fifth embodiment, the primary mapping processing is performed from the lowest group to the higher group. In the present embodiment, mapping is performed so that the circuit includes a circuit configuration including a plurality of pass transistors connected in series via a buffer.

In the primary mapping processing of this embodiment, first, the product terms of the least significant group are mapped using an AND-structured multiplexer. The required number of AND configuration multiplexers are connected in series depending on the number of variables included in the product terms. That is, the output terminal of the preceding multiplexer is connected to the input terminal of the next multiplexer. In order to prevent the logic amplitude from deteriorating, a buffer is inserted every time the number of stages of the pass transistor reaches a predetermined maximum allowable number, for example, two. Terms containing only one variable need not be mapped at this stage. The variable is input directly to the next stage.

After all the product terms in the lowest group are mapped by the above method, the mapping of the higher group is further performed.

For example, when two terms in the lowest group share a higher variable, the logical group in the second group from the lowest includes the higher variable. In this case, a multiplexer is arranged in the logic circuit, two terms are input to the input terminal of the multiplexer, and the upper variable is input to the control terminal of the multiplexer. If three or more terms share multiple high-order variables, two or more multiplexers are arranged in the logic circuit (so that the number of pass transistor stages does not exceed the maximum allowable value), and the high-order variables are used to control each multiplexer. The term is input to the terminal, and the term is input to each input terminal. If the next higher-level logical group includes a higher-level variable, the multiplexer is further arranged at the next stage unless the number of stages exceeds the maximum allowable number. For example, when the above logical expression (15) is mapped by the above-described primary mapping process, a logical circuit having the form shown in FIG. 69 is obtained.

In equation (15), the inside of the four parentheses is the lowest group. They have terms containing only the variable c, and product terms de, fgh, and ijkl, respectively. Of these, the second and third product terms are
Includes two or three variables, respectively. Therefore, each is mapped by one AND configuration multiplexer and two AND configuration multiplexers. Since the fourth product term contains four variables, this product term is mapped using a combination of three AND configuration multiplexers connected in series. The maximum allowable number of pass transistors is 2
Being a stage, a buffer is inserted between the second and third stage AND configuration multiplexers. The above four terms are logical functions that share two upper variables a and b. Therefore,
Further mapping is performed using a two-stage multiplexer. The last stage and the previous stage are basically the same as the circuit in FIG. However, the first of the multiplexers used to map a logical group with two upper variables
A buffer is inserted between the stage and the second stage so that the number of pass transistor stages does not exceed the allowable maximum value.

An example of the AND configuration multiplexer described in the primary mapping process is the multiplexer M21 shown in FIG. In the multiplexer M21, the output of the multiplexer M21 becomes valid (H state) only when the variables d and e are valid (H state). In this example, since the multiplexer M21 is configured in a positive logic format, an AND logic is adopted. However, if the constants and variables input to the input terminal are inverted,
NAND logic can also be employed. Such an multiplexer is also referred to as an “AND configuration multiplexer”.

On the other hand, a logical group having a common variable is
It is mapped using an AND logic multiplexer.
In this case, a buffer is inserted every time the number of pass transistor stages becomes, for example, two. If the logical group has one common variable, the sum of the logical functions sharing this common variable is input to the input terminal of the AND configuration multiplexer;
Input common variables to control terminals. If the logical group includes a plurality of common variables, use another AND configuration multiplexer to map the product of the common variables, and then use the AND configuration multiplexer to map the group having the common variable. Is input to Then, of the product of the common variables and the sum of the logical functions sharing this common variable, the one with the larger number of path stages is input to the input terminal of the AND configuration multiplexer, and the one with the smaller number of path stages is input to the control terminal. .

If the signal to the control terminal is supplied without passing through the buffer, a buffer is inserted. This buffer helps to recover the logic amplitude. That is, H
The signal is restored to the power supply voltage, and the L signal is restored to the ground voltage. If the number of paths of the product of the common variables is the same as the number of paths of the logic function sharing the common variable, either of them may be input to the control terminal. The above logical expression (16) is an example where the number of path stages related to the product of the common variables is equal to the number of path stages related to the sum of the logical functions. This logical expression (1
If 6) is mapped by the primary mapping process described here, a logic circuit as shown in FIG. 70 can be obtained.

In the logic circuit of FIG. 70, common variables b,
c and d are mapped using two AND configuration multiplexers, and the outputs are input to the control terminals of the second-stage multiplexer from the last stage. This common variable b,
Sum of four logic functions sharing c and d

[Outside 25] Is input to the input terminal of the AND configuration multiplexer. Then, taking into account the fact that variables e and f act as multiple higher-order variables,

[Outside 26] Are mapped using a two-stage multiplexer.

After the primary mapping process, a logic level matching corresponding to step S16 in the flowchart of FIG. 7 is performed.

The buffer used in the primary mapping is C
In a MOS logic circuit, since two inverters are used in series, a delay time is increased, the number of transistors is increased, and power consumption is increased. Therefore, in this logic level matching, the buffer used in the primary mapping is stored in the inverter 1
To reduce the number of transistors. At the same time, the logic inversion is adjusted.

In the logic level matching of this embodiment, the logic level is adjusted so that positive (negative) logic areas and negative (positive) logic areas are alternately arranged from the output side to the input side. The polarity of the last stage is determined in consideration of whether a given logical expression is expressed by positive or negative logic. Specifically, each buffer is first replaced with one inverter, and the logic circuit is divided into a positive logic area and a negative logic area with each inverter as a boundary. Then, the logic of the signal directly input to the negative logic area is inverted.

When the primary mapping processing according to the present embodiment is performed on the logical expression (17), a logical circuit shown in FIG. 71 can be obtained. FIG. 72 shows the result of performing the logic level matching on this logic circuit.

In the example of FIG. 71, since the logical expression (17) is expressed by positive logic, the output W is in the positive logic area. Therefore, the circuit portion between the buffers B1 and B2, the buffer B
The part preceding the buffer 3 and the part preceding the buffer B4 are in the negative logic area. The control signal input to the control terminal of the multiplexer may be a positive logic or a negative logic, but here is a positive logic. The portion preceding the buffer B5 is also in the negative logic area. Specifically, the variables c, g, and i which are direct input signals are inverted. Similarly, the L constant signal input to the multiplexers M31 to M35 and the H constant signal input to the multiplexer M36 are inverted. No other changes are made. When the above logic level matching is performed on the logic circuit of FIG. 71, the logic circuit is converted into a circuit as shown in FIG.

Next, a ninth embodiment will be described.

In the ninth embodiment, after the optimization of a given logical expression is completed, first, the mapping process for the highest-order group is performed, and then the mapping process for the lower-order group is adjusted simultaneously with the logical level. While doing.

The mapping processing for the highest-order group and the lower-order group can be performed in substantially the same manner. However, when the highest-order group includes a plurality of independent lower-order groups, as in the case of equation (21), the input order of the plurality of groups may be selected so that the maximum number of stages is minimized. desirable.

For this purpose, an OR configuration multiplexer is used in which one input terminal is connected to receive a constant signal. An inverter is inserted at an appropriate position so that the number of pass transistor stages falls within an allowable range. Mapping is performed in order from the group having the largest number of path stages to the group having the smallest number of path stages from the output side to the input side. For example, when the number of path stages of the logical groups J, K, and L decreases in this order in the equation (21), a logical circuit as shown in FIG. 73 can be obtained.

[0317] The number of path stages can be approximately estimated as follows. Of the product terms of the lowest group belonging to the group under consideration, compare the product term with the largest number of variables with the number of common variables shared by the product terms of the lowest group, 1 "is added, and the number of upper variables is added to this. This process is repeated for the upper logical group, and the obtained value is added to the value. By repeating the same processing, the top-level group ((2
In the case of the expression 1), when reaching the logical group J, K, L), the finally obtained value is used as the estimated path stage number.

The mapping process is also performed on the highest-order group and the lower-order group having a configuration other than the expression (21). In the mapping process for each group,
Mapping is performed from the highest order to the lowest order so that the number of pass transistor stages does not exceed the maximum allowable number. In this mapping process, a positive (negative) logic area and a negative (positive) logic area are alternately formed from the output side toward the input side, and the adjacent positive logic area and negative logic area are mutually inverted. Is bounded.

The processing here is basically the same as that of the eighth embodiment except that the logic level matching is performed at the same time.

More specifically, a logical group having upper variables is mapped by a multiplexer, and a logical group having common variables is mapped by using an AND configuration multiplexer. An estimated value of the number of pass stages is determined for the product of the common variables and the sum of the logic functions sharing the common variables. The larger one is input to the input terminal of the AND configuration multiplexer, and the smaller one is input to the control terminal of the corresponding multiplexer. input. When the signal input to the control terminal of the multiplexer is supplied without passing through the inverter, the inverter is inserted. A signal input directly to the negative logic area inverts the logic.

As described above, in the eighth and ninth embodiments, the logical expression given to be formed in the logic circuit is mapped using the pass transistor logic circuit. A logical expression (5) optimized by the combination type method, a logical expression (9) optimized by the bottom-up common variable method, and a logical expression (14) optimized by the common variable / combination type method FIGS. 74 to 77, FIGS. 78 to 82, and FIGS. 83 to 87, respectively, using a pass transistor logic circuit according to the method of the eighth embodiment.
Can be mapped to the logic circuit shown in FIG. Here, FIG. 74 to FIG. 77, FIG. 78 to FIG.
Are one logical circuit divided for convenience of drawing, and are denoted by S81 to S84, S91 to S94, S
101 to S104 are used to indicate connection of signals in a logic circuit.

The logic circuit shown in FIGS. 74 to 77 uses 166 transistors, and the maximum value of the number of signal paths is 1.
There are four stages. The number of transistors used in the logic circuits shown in FIGS. 78 to 82 is 141, and the maximum value of the number of signal path stages is 1.
Two stages. The number of transistors used in the logic circuits shown in FIGS. 83 to 87 is 142, and the maximum number of signal path stages is 1.
2.

[0323]

According to the technology disclosed in various embodiments of the present invention, at least one of the following advantages is achieved.

According to the logic circuit designing method of the present invention, a logic group having a higher variable is mapped to a logic circuit having a smaller total number of transistors and a smaller number of stages by using a multiplexer composed of a combination of pass transistors. In one embodiment of the present invention, further, logic groups having common variables are mapped using multi-input logic gates, resulting in a logic circuit including a smaller number of transistors and stages. The CAD system according to the invention is used to perform such a mapping process in a desired manner.

According to the logic circuit designing method of the present invention, optimization processing including processing for grouping product terms by higher variables is performed on a given logical expression. As a result, the optimized logical expression is easily mapped to a logical circuit including a small number of transistors and the number of stages using the multiplexer. In one embodiment of the invention, a given logical expression is optimized by grouping product terms by common variables. This optimized logic expression is easily mapped to a logic circuit including a small number of transistors and the number of pass transistor stages using a multi-input logic gate. According to an embodiment of the present invention, a given logical expression is optimized by an optimization process including a process of grouping product terms by common variables in addition to a process of grouping product terms by upper variables. Be transformed into As a result, the optimized logic expression is easily mapped using a multiplexer and a multi-input logic gate to a logic circuit including a smaller number of transistor and pass transistor stages.
The CAD system according to the invention is used to perform such a mapping process in a desired way.

According to the mapping method of the present invention, a combinational logic expression is mapped to a small number of transistors and a logic circuit having a number of stages using a circuit configuration including a multiplexer and an inversion type logic gate. The CAD system according to the invention is used to perform such a mapping process in a desired manner.

According to the mapping method of the present invention, a product term including various numbers of logic functions is mapped to a logic circuit including a small number of transistors and stages using a combination of a multi-input logic gate and a required number of multiplexers. Is done. The CAD system according to the invention is used to implement such a mapping process in a desired way.

According to the present invention, a logic circuit for executing a logical operation represented by a logical expression having a product term including various numbers of logical functions is provided by using a combination of a multi-input logical gate and a required number of multiplexers. Thus, it can be configured with a small number of transistors and the number of stages. An electronic system according to the present invention is implemented using such a logic circuit. In a method for performing a logical operation according to the present invention, a logical operation represented by a logical expression having a product term including various numbers of logical functions is efficiently performed by using a logical circuit of the above-described form. You.

According to the mapping method of the present invention, a logical expression including a logical group having one or more upper variables shared by a plurality of logical functions, some or all of which are products of a plurality of lower logical functions. Are mapped to a logic circuit that includes a small number of transistors and stages using a combination of one or more multi-input logic gates and multiplexers. The CAD system according to the invention is used to implement such a mapping process in a desired way. According to the present invention, performing a logical operation represented by a logical expression that includes a logical group having one or more upper variables shared by a plurality of logical functions, one or all of which is the product of a plurality of lower logical functions. A logic circuit suitable for using a combination of one or more multi-input logic gates and a multiplexer,
It can be composed of a small number of transistors and the number of stages.
An electronic system according to the present invention is configured using such a logic circuit.

According to the logical operation execution method of the present invention, a logical group having one or more upper variables shared by a plurality of logical functions, some or all of which are products of a plurality of lower logical functions, is created. The logical operation represented by the logical expression including, using a logical circuit including a combination of one or more multi-input logical gates and multiplexers of the above-described type,
It can be executed efficiently.

According to the mapping method of the present invention, the mapping method includes one or more common variables shared by a plurality of logical functions,
A logical expression that includes a logical group whose logical function sum is a lower logical group including one or more upper variables shared by a plurality of lower logical functions is expressed by using a combination of a multi-input logical gate and a multiplexer. It is mapped to a logic circuit including a small number of transistors and the number of stages. The CAD system according to the present invention performs such a mapping process,
Used to implement in the desired manner.

According to the present invention, one or more common variables shared by a plurality of logical functions are included, and the sum of the logical functions is determined by a lower order including one or more upper variables shared by a plurality of lower logical functions. A logic circuit suitable for performing a logical operation represented by a logical expression including a logical group that is a logical group of the above is configured with a small number of transistors and the number of stages using a combination of a multi-input logical gate and a multiplexer. Can be. An electronic system according to the present invention is configured using such a logic circuit.

According to the method of executing a logical operation according to the present invention, the method includes one or more common variables shared by a plurality of logical functions, and the sum of the logical functions is one or more common variables shared by a plurality of lower logical functions. The logical operation represented by the logical function including the logical group that is the lower logical group including the upper variable of the above is efficiently executed using the logical circuit including the combination of the multi-input logical gate and the multiplexer of the above-described form. can do.

According to the logic expression mapping method of the present invention, a logic expression is mapped using a combination of two types of multi-input logic gates and a multiplexer. The method includes, for example, a product of a plurality of logical functions, at least one of the logical functions being a lower logical group including one or more upper variables shared by the plurality of lower logical functions, and At least one of the logical functions has a plurality of second functions.
A logical expression including a logical group, which is a product of lower logical functions, can be mapped to a logical circuit including a small number of transistors and the number of stages. The CAD system according to the invention is used to implement such a mapping process in a desired way.

A logic circuit according to the present invention includes first and second types of multi-input logic gates and multiplexers,
Is connected to one of the input terminals of the multiplexer without inversion, and the output terminal of the multiplexer is connected to the input of the second type of multi-input logic gate without inversion. Connected to one of the terminals. The circuit includes, for example, a product of a plurality of logical functions, and at least one of the logical functions is a lower logical group including one or more upper variables shared by the plurality of lower logical functions. Is suitable for executing a logical operation represented by a logical expression including a logical group such that at least one of the logical functions is a product of a plurality of second lower-order logical functions with a small number of transistors and the number of stages. An electronic system according to the present invention is configured using such a logic circuit.

According to the logical operation execution method of the present invention, for example, the logical operation is formed by a product of a plurality of logical functions, and at least one of the logical functions includes one or more upper variables shared by the lower logical functions. A logical operation represented by a logical expression such that at least one of the lower logical groups includes a logical group that is a product of a plurality of second lower logical functions is performed in the above-described manner.
It can be implemented efficiently using a logic circuit that includes a combination of different types of multi-input logic gates and multiplexers.

[Brief description of the drawings]

FIG. 1 is a diagram of an example of a BDD expressing a logical expression.

FIG. 2 is a circuit diagram of a logic circuit obtained by mapping the logic expression of FIG. 1;

FIG. 3 is a circuit diagram of a logic circuit in which input variables of a logical expression are input in a certain order;

FIG. 4 is a diagram showing a BDD expressing a logical expression mapped to the logical circuit of FIG. 3;

5 is a circuit diagram of a logic circuit in which a logical expression equivalent to that mapped to the logic circuit in FIG. 3 is mapped so that input variables are input in different orders;

FIG. 6 is a diagram showing a BDD expressing a logical expression mapped to the logical circuit in FIG. 5;

FIG. 7 is a flowchart illustrating a procedure for designing a logic circuit according to one embodiment of the present invention.

FIG. 8 is a circuit diagram of a logic circuit showing a basic configuration of a composite pass transistor logic circuit.

FIG. 9 is a circuit diagram showing an example of a pass transistor logic operation system used in a composite pass transistor logic circuit;

FIG. 10 is a circuit diagram showing an example of a unit multiplexer used in one embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a handset of a personal handyphone.

FIG. 12 is a block diagram showing a configuration of a cellular phone subscriber unit.

FIG. 13 is a schematic configuration diagram of a CAD system.

FIG. 14 is a diagram of a head part of a first variable table used for designing a logic circuit according to the first embodiment of the present invention;

FIG. 15 is a diagram of a part following FIG. 14 of the first variable table.

FIG. 16 is a diagram of a portion following FIG. 15 of the first variable table;

FIG. 17 is a diagram of a portion following FIG. 16 of the first variable table;

FIG. 18 is a diagram of a second variable table used in the first embodiment.

FIG. 19 is a chart of a head portion of a third variable table used in the first embodiment.

FIG. 20 is a diagram of a portion following FIG. 19 of the third variable table.

FIG. 21 obtained by the first embodiment;
26 is a circuit diagram showing a part of a logic circuit shown in whole in FIG.

FIG. 22 is a circuit diagram showing another part of the logic circuit obtained by the first embodiment.

FIG. 23 is a circuit diagram showing still another part of the logic circuit obtained by the first embodiment.

FIG. 24 is a circuit diagram showing still another part of the logic circuit obtained by the first embodiment.

FIG. 25 is a circuit diagram showing still another part of the logic circuit obtained by the first embodiment.

FIG. 26 is a circuit diagram showing still another part of the logic circuit obtained by the first embodiment.

FIG. 27 is a flowchart showing the first half of the process according to the first embodiment;

FIG. 28 is a flowchart showing the second half following FIG. 27;

FIG. 29 is a circuit diagram showing a pass transistor logic circuit of NAND logic.

FIG. 30 is a circuit diagram showing a CMOS-NAND gate;

FIG. 31 is a diagram of a first half of a first variable table used for designing a logic circuit according to the second embodiment of the present invention;

FIG. 32 is a second half chart of the first variable table following FIG. 31;

FIG. 33 is a diagram of a second variable table used in the second embodiment.

FIG. 34 is a diagram of a third variable table used in the second embodiment.

FIG. 35 obtained by the second embodiment;
To 40 is a circuit diagram showing a part of a logic circuit entirely shown in FIG.

FIG. 36 is a circuit diagram showing another part of the logic circuit obtained by the second embodiment.

FIG. 37 is a circuit diagram showing still another part of the logic circuit obtained by the second embodiment.

FIG. 38 is a circuit diagram showing still another part of the logic circuit obtained by the second embodiment.

FIG. 39 is a circuit diagram showing still another part of the logic circuit obtained by the second embodiment.

FIG. 40 is a circuit diagram showing still another portion of the logic circuit obtained by the second embodiment.

FIG. 41 is a flowchart showing the first half of processing according to the second embodiment;

FIG. 42 is a flowchart showing the second half following FIG. 41;

FIG. 43 is a diagram of a head portion of a variable table used for designing a logic circuit according to the third embodiment of the present invention;

FIG. 44 is a diagram of the portion of the variable table following FIG. 43;

FIG. 45 is a diagram of the part of the variable table following FIG. 44;

FIG. 46 is a diagram of a variable table used for designing a logic circuit according to the fourth embodiment of the present invention;

FIG. 47 FIG. 47 obtained by the fourth embodiment.
To 52 are circuit diagrams showing a part of a logic circuit entirely shown in FIG.

FIG. 48 is a circuit diagram showing another part of the logic circuit similarly obtained by the fourth embodiment;

FIG. 49 is a circuit diagram showing still another part of the logic circuit obtained by the fourth embodiment.

FIG. 50 is a circuit diagram showing still another part of the logic circuit obtained by the fourth embodiment.

FIG. 51 is a circuit diagram showing still another part of the logic circuit obtained by the fourth embodiment.

FIG. 52 is a circuit diagram showing still another part of the logic circuit obtained by the fourth embodiment.

FIG. 53 is a circuit diagram showing a logic circuit designed by the first method of the fifth embodiment of the present invention.

FIG. 54 is a circuit diagram showing a logic circuit designed by the second method of the fifth embodiment.

FIG. 55 is a circuit diagram showing an example of a logic circuit targeted by the design method according to the sixth embodiment of the present invention;

FIG. 56 is a circuit diagram showing a logic circuit converted from the logic circuit of FIG. 55 by the processing according to the sixth embodiment;

FIG. 57 is a circuit diagram showing an example of a first-type logic circuit of the highest-level group mapping by the logic circuit design method according to the seventh embodiment of the present invention;

FIG. 58 is also the second of the top-level group mapping.
Circuit diagram showing an example of various kinds of logic circuits

FIG. 59 is also a diagram showing a third example of the top-level group mapping.
Circuit diagram showing an example of various kinds of logic circuits

FIG. 60 is a diagram showing a fourth group mapping of the highest-order group;
Circuit diagram showing an example of various kinds of logic circuits

FIG. 61 is a circuit diagram showing a logic circuit obtained by adding a multiplexer to the fourth type of logic circuit;

FIG. 62 is a circuit diagram showing a logic circuit in which a NOR gate is added to the fourth type of logic circuit;

FIG. 63 obtained by the seventh embodiment;
To FIG. 68 are circuit diagrams showing a part of the whole logic circuit.

FIG. 64 is a circuit diagram showing another portion of the logic circuit similarly obtained by the seventh embodiment;

FIG. 65 is a circuit diagram showing still another part of the logic circuit obtained by the seventh embodiment.

FIG. 66 is a circuit diagram showing still another part of the logic circuit obtained by the seventh embodiment.

FIG. 67 is a circuit diagram showing still another part of the logic circuit obtained by the seventh embodiment.

FIG. 68 is a circuit diagram showing still another part of the logic circuit obtained by the seventh embodiment.

FIG. 69 is a circuit diagram showing a first example of a logic circuit obtained by primary mapping according to the eighth embodiment of the present invention;

FIG. 70 is a circuit diagram showing a second example of the logic circuit obtained by the primary mapping

FIG. 71 is a circuit diagram showing a logic circuit targeted for logic level matching according to the eighth embodiment;

FIG. 72 is a circuit diagram showing a logic circuit after the logic circuit of FIG. 71 is processed according to the eighth embodiment;

FIG. 73 is a circuit diagram showing an example of a logic circuit having an OR logic configuration in which a highest-order group is mapped by the logic circuit design method according to the ninth embodiment of the present invention;

74 to FIG. 77, in which the logical expressions optimized by the combination type method are mapped according to the eighth embodiment.
Circuit diagram showing a part of a logic circuit indicated in whole by

FIG. 75 is a circuit diagram showing another part of the logic circuit according to the combination type method.

FIG. 76 is a circuit diagram showing still another part of the logic circuit according to the combination type method.

FIG. 77 is a circuit diagram showing still another part of the logic circuit according to the combination type method.

FIG. 78 is a circuit diagram showing a part of a logic circuit shown in FIGS. 78 to 82 in which logic expressions optimized by the common variable method are mapped according to the eighth embodiment.

FIG. 79 is a circuit diagram showing another part of the logic circuit according to the common variable method.

FIG. 80 is a circuit diagram showing still another part of the logic circuit according to the common variable method.

FIG. 81 is a circuit diagram showing still another part of the logic circuit according to the common variable method.

FIG. 82 is a circuit diagram showing still another part of the logic circuit according to the common variable method.

FIG. 83 is a view showing a case where a logical expression optimized by the common variable / combination type method is mapped according to the eighth embodiment;
FIG. 3 is a circuit diagram showing a part of a logic circuit entirely shown in FIG.

FIG. 84 is a circuit diagram showing another portion of the logic circuit according to the common variable / combination type method.

FIG. 85 is a circuit diagram showing still another part of the logic circuit according to the common variable / combination type method.

FIG. 86 is a circuit diagram showing still another part of the logic circuit according to the common variable / combination type method.

FIG. 87 is a circuit diagram showing still another part of the logic circuit according to the common variable / combination type method.

[Explanation of symbols]

 Q: Unit multiplexer R: Pass transistor logical operation system S: Multi-input logic gate U: Output terminal X, Y: Input terminal Z: Control terminal a to j: Input (or variable) GND: Ground voltage VDD: Power supply voltage

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[Procedure amendment]

[Submission date] June 9, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 25

[Correction method] Change

[Correction contents]

FIG. 25

Claims (18)

[Claims] 1. A method for designing a logic circuit for mapping a logic expression, comprising: disposing a multiplexer having a plurality of input terminals, at least one control terminal, and an output terminal in the logic circuit; A first logical group of logical expressions, comprising a plurality of logical functions and at least one upper variable, and including a first plurality of logical functions and at least one upper variable shared by the first plurality of logical functions. Connecting the input terminal of the multiplexer and at least one control terminal such that is output from the output terminal of the multiplexer. 2. The design method according to claim 1, further comprising: arranging a multi-input logic gate having a plurality of input terminals and an output terminal in the logic circuit; a common variable and a second plurality of logic functions. Enter the sum of
Multi-input logic gate such that a second logical group of logical expressions, including a plurality of logical functions and a common variable shared by the second plurality of logical functions, is output from an output terminal of the multi-input logical gate Connecting the input terminals of the logic circuit. 3. The design method according to claim 1, further comprising a step of specifying a first logic group before the step of making said connection. 4. A CAD system for designing a logic circuit for mapping a logic expression, comprising: a multiplexer having a plurality of input terminals, at least one control terminal, and an output terminal arranged in the logic circuit; A first logical group of logical expressions, comprising a plurality of logical functions and at least one upper variable, and including a first plurality of logical functions and at least one upper variable shared by the first plurality of logical functions. Means for connecting the input terminal of the multiplexer and at least one control terminal such that the output terminal is output from the output terminal of the multiplexer. 5. A method of designing a logic circuit for mapping a logical expression, comprising: (a) selecting at least a part of a logical expression including a plurality of product terms each including a plurality of variables; Identifying at least one upper variable complementary to at least two of the plurality of product terms; and (c) identifying the at least two product terms with the at least one
Creating a logical group including at least one upper variable and at least two logical functions sharing the at least one upper variable by at least one cycle. A method for designing a logic circuit, comprising: optimizing an expression; and mapping the optimized logic expression to a logic circuit. 6. The design method according to claim 5, wherein said specific step includes a step of determining a number of logical combination types of a set of variables in said plurality of product terms, and a maximum number of logical combination types. Selecting at least one variable from among at least one set of variables as a candidate for a higher-order variable. 7. The design method according to claim 5, wherein said specific step is a step of determining the number of logical combination types of a set of variables in said plurality of product terms; Selecting at least two variables included in at least one of the set of variables having a number; and determining a number of times each of the at least two variables is included in the set of variables having the largest number of logical combination types. And selecting at least one variable having the largest number of times included in the set of variables having the maximum number of logical combination types from the at least two variables as a candidate for a higher-level variable. A logic circuit design method characterized by the following. 8. The design method according to claim 5, wherein the optimizing step includes at least a first cycle and a second cycle of a first process, and the selecting step in a second cycle includes: A logic circuit design method, wherein a logic function created by a first cycle grouping is selected as a product term of at least a part of a logic expression. 9. The design method according to claim 5, wherein the step of optimizing further comprises: (a) selecting at least a part of a logical expression including a plurality of product terms each including a plurality of variables. (B) identifying at least one set of common variables commonly included in at least two of the plurality of product terms; and (c) grouping the at least two product terms to form the at least one product variable. A second variable including a common variable and a plurality of second logical functions sharing the at least one common variable;
Creating a logical group of the following: and a second process including at least one cycle, the method comprising: 10. The design method according to claim 9, wherein the optimizing step includes a first processing cycle following a second processing cycle, and wherein the specific step in the second processing is performed. Identifying at least two sets of at least two common variables, wherein said step of selecting during the first processing comprises: multiplying at least two sets of at least two common variables of the at least two sets specified during the second processing; A method for designing a logic circuit, comprising selecting as a product term of at least a part of a logic expression. 11. A CAD system for designing a logic circuit for mapping a logical expression, comprising: (a) selecting at least a part of a logical expression including a plurality of product terms each including a plurality of variables; (b) A) identifying at least one upper variable that is complementary to at least two of said plurality of product terms;
And (c) replacing the at least two product terms with the at least one
Grouped by two top variables and the at least one
Creating a logical group including at least one upper variable and at least two logical functions sharing the at least one upper variable, wherein the first processing includes at least one cycle. And a means for mapping the optimized logical expression to a logical circuit. 12. A method for designing a logic circuit for mapping a logic expression, comprising: (a) selecting at least a part of a logic expression including a plurality of product terms each including a plurality of variables; Identifying at least one set of common variables commonly included in at least two of the plurality of product terms;
And (c) grouping the at least two product terms to create a logical group including the at least one common variable and a plurality of logical functions sharing the at least one common variable. A method for designing a logic circuit, comprising: optimizing a logic expression including one cycle; and mapping the optimized logic expression to a logic circuit including a multiplexer. 13. The design method according to claim 12, wherein the step of optimizing includes at least a first cycle and a second cycle of the processing, and the specific step in the first cycle is at least two cycles. Identifying at least two sets of two common variables, wherein said selecting step during a second cycle comprises calculating a product of at least two common variables in at least two sets identified during a first cycle by a logical expression A logic circuit design method, wherein the product term is selected as at least a part of the product term. 14. The design method according to claim 12, wherein the step of optimizing includes at least a first cycle and a second cycle of the processing, and the specific step in the first cycle is grouping. Identifying at least one set of common variables that are commonly included in at least four product terms such that the logical group created by includes at least four logical functions, wherein said selecting step during a second cycle comprises: At least four logic functions selected during the second cycle
A method for designing a logic circuit, comprising selecting as a product term of at least a part of a logic expression. 15. The design method according to claim 12, wherein
The method of designing a logic circuit, wherein the specific step specifies a plurality of sets of at least one common variable commonly included in a predetermined number of product terms. 16. The design method according to claim 12, wherein:
The design method of a logic circuit, wherein the specific step specifies a predetermined number of sets of at least one common variable. 17. The design method according to claim 12, wherein:
The mapping step comprises: at least one upper variable in the optimized logical expression;
And identifying a second logical group having a plurality of second logical functions that share the at least one upper variable; and inputting the second logical function and at least one upper variable; Connecting the input terminal and the control terminal of the multiplexer so that the logical group is output from the output terminal of the multiplexer. 18. A CAD system for designing a logic circuit for mapping a logical expression, wherein at least a part of the logical expression including a plurality of product terms each including a plurality of variables is selected, and a plurality of product terms of the plurality of product terms are selected. At least 2
A set of at least one common variable included in common with each other, and grouping the at least two product terms to include the at least one common variable and a plurality of logic functions sharing the at least one common variable Means for optimizing a logical expression including at least one cycle of creating a logical group, and means for mapping the optimized logical expression to a logical circuit including a multiplexer. Characterized CAD system.