JPH1165974A - Communication network system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily process communication data between a communication controller and a central controller by fixing a buffer circuit to access next time by the combination of a buffer circuit under access this time and a free buffer by means of a transition condition judging part. SOLUTION: A free buffer detecting part 40 detects a free buffer which is not accessed to by neither the communication controller 10 nor the central controller 20 from among three buffer circuits. The transition condition judging part 50 fixes the buffer circuit to access next time from the combination of the buffer circuit under access this time and the free buffer detected by the part 40. Three buffers are provided for the buffer circuits 30 to allow the controllers 10 and 20 to access to two of the buffer circuits and to make the other one a free buffer in this case, but the number of buffers to provide for the circuits 30 can be equal to or more than four.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication network system in which a plurality of control devices each including a central control device and a communication control device are interconnected by a plurality of networks. Communication control.

[0002]

2. Description of the Related Art A communication network system including a central control unit and a communication control unit is disclosed, for example, in Japanese Patent Laid-Open No. 1-24123.
No. 8 discloses this. In such a communication network system, simultaneous broadcast communication is performed at a fixed period in order to share data between each control device with another control device. Each control device outputs its own data,
Data from other stations will be input. That is, each station broadcasts its own station data simultaneously.

FIG. 3 is a block diagram showing the configuration of a conventional communication network system. FIGS. 3A to 3C show various states of use of a buffer circuit. In the figure, for example, in a process control or the like, a central control unit 20 calculates a set value for an individual operation terminal, reads a measured value of an individual detection terminal, and further provides an operator with a process operation state. Or display. Communication control device 10
Transmits and receives data to and from another communication control device 10 using a communication line such as a local network (LAN), and a communication protocol and the like are predetermined. Here, three buffer circuits 30 are provided in parallel to synchronize the central control device 20 and the communication control device 10 that are operating asynchronously. The management flag 32 indicates the buffer circuit 3 used by the central control device 20 and the communication control device 10.
Flags are managed so that 0 does not conflict.

[0004]

However, if the central control unit 20 and the communication control unit 10 are prohibited from accessing the same buffer circuit at the same time, if a speed difference occurs between the two, the speed will be reduced. The access to the buffer circuit on the device side repeats the access to the same buffer circuit until the processing in the buffer circuit of the slower device is completed. For example, initially, the central control device 20 stores the buffer #
1 and the communication control apparatus 10 accesses the buffer # 3 (FIG. 3A). Since the processing of the central controller 20 is fast, the central controller 20 sets the next buffer # 2.
, But access to the buffer # 3 of the communication control device 10 is continued (FIG. 3B). Communication control device 1
FIG. 3B until the processing for buffer # 3 of 0 is completed.
State is continued, and after the end, the central controller 20 accesses the buffer # 3, and the communication controller 10
(FIG. 3C).

By the way, in the state of FIG.
0 accesses the buffer # 1, but the data stored in the buffer # 1 is transmitted to the buffer # 2 by the central controller 20.
Just before accessing. That is, the latest data of the central control unit 20 is the one that accessed the previous buffer # 2, and there was a problem that the data stored in the buffer # 1 became old data. In addition, although the control of the buffer circuit 30 is performed by the management flag 32, there is a problem that the processing speed is further reduced because the access state of the partner device needs to be monitored.

A first object of the present invention is to provide a communication network system capable of transmitting and receiving the latest data between the central control device 20 and the communication control device 10 via a buffer circuit. It is in. A second object is to provide a communication network system capable of high-speed processing by managing the use state of a buffer circuit without using a management flag.

[0007]

To achieve the above object, a communication network system according to the first aspect of the present invention is a communication control apparatus for exchanging data with another communication control apparatus using a communication line. And a central control device 20 provided one-to-one with the communication control device, and three or more buffer circuits 30 provided in parallel between the communication control device and the central control device. A means 40 for detecting an empty buffer which is not accessed by any of the communication control device and the central control device in the buffer circuit; and, for the communication control device and the central control device, A transition condition determining unit 50 for determining a buffer circuit to be accessed next from a combination of buffers is provided.

According to the first aspect of the present invention, the transition condition judging section 50 determines the buffer circuit to be accessed next time from the combination of the buffer circuit currently accessed and the empty buffer for the communication control device and the central control device. Therefore, even if the processing speeds of the communication control device and the central control device are unbalanced, communication data can be quickly exchanged between the communication control device and the central control device via the buffer circuit.

Here, if the buffer circuit is configured so that the communication control device and the central control device are prevented from simultaneously accessing one buffer, the buffer circuit can access the buffer circuit. A stable access can be made without the contents of the communication data being changed or being undefined during the operation. When the access to the buffer circuit currently accessed is completed, the communication control device or the central control device accesses the transition condition determination unit to determine a buffer circuit to be accessed next time. It may be configured as follows. By setting the timing of accessing the transition condition determining unit immediately before determining the buffer circuit to be accessed next time, promptness of transmission and reception of communication data is always ensured.

According to a fifth aspect of the present invention, when the transition condition determining unit sets the buffer circuit to be accessed next time to the empty buffer obtained by the empty buffer detecting means, the transmission delay of communication data between the communication control device and the central control device is reduced. Each processing speed is equivalent to one access, and speeding up can be reliably achieved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a configuration block diagram showing one embodiment of the present invention. In FIG. 1, components having the same functions as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. In the figure,
The communication control device 10 includes a buffer access end determination unit 12 that detects a timing when access to one of the buffer circuits 30 ends. The central control device 20 is also provided with a buffer access end determination unit 22 that detects the timing when access to one of the buffer circuits 30 ends.

The empty buffer detecting section 40 detects an empty buffer which is not accessed by any of the communication control device 10 and the central control device 20 among the three buffer circuits # 1 to # 3. The transition condition determination unit 50 determines a buffer circuit to be accessed next time from the combination of the buffer circuit currently accessed and the empty buffer detected by the empty buffer detection unit 40 for the communication control device 10 and the central control device 20.

FIG. 2 is a state transition diagram used by the transition condition determination section 50. In the figure, the transition condition of the central control device 20 is represented by i, and the transition condition of the communication control device 10 is represented by j. In an initial state of access to the buffer circuit, the buffer # 1 is accessed by the central control device 20, the buffer # 3 is accessed by the communication control device 10, and the buffer # 2 is an empty buffer. This state is represented by an arrangement of “123”. Assuming that the access of the central control device 20 in the initial state has now been completed, the next time access is to the empty buffer # 2, and the state transits to the state of arrangement of "213". Next, assuming that the access of the communication control device 10 has been completed, the next time the access is to the empty buffer # 1, and the state transits to the state of “231”. In this way, the transition condition determination unit 50 recommends the empty buffer detected by the current empty buffer detection unit 40 as the buffer circuit to be accessed next time.

In the above embodiment, three buffers # 1 to # 3 are provided in the buffer circuit 30, and the two buffer circuits are accessed by the communication control device 10 and the central control device 20, and the other one is Has been described as an empty buffer, but the present invention is not limited to this, and the number of buffers provided in the buffer circuit 30 may be four or more. It goes without saying that the present invention can be implemented with various changes within a range not departing from the gist.

[0015]

As described above, according to the first aspect of the present invention, the transition condition judging section 50 determines the communication control device and the central control device from the combination of the buffer circuit and the empty buffer currently accessed. Since the buffer circuit to be accessed next time is determined, even if the processing speeds of the communication control device and the central control device are unbalanced, transmission and reception of communication data between the communication control device and the central control device via the buffer circuit are not possible. Can be done quickly. Also, the conventional management flag 3
Compared to the case where the buffer circuit 2 is provided, the empty buffer detection unit 40 can be easily configured using a logic element, so that the processing speed can be increased by hardware, and the use state of the buffer circuit 30 is determined by the empty buffer detection. Since the determination can be made based on the signal from the unit 40, management software such as a central control device can be easily configured.

Here, if the buffer circuit is configured so as to prevent the communication control device and the central control device from simultaneously accessing one buffer, the buffer circuit can access the buffer circuit. A stable access can be made without the contents of the communication data being changed or being undefined during the operation. When the access to the buffer circuit currently accessed is completed, the communication control device or the central control device accesses the transition condition determination unit to determine a buffer circuit to be accessed next time. It may be configured as follows. By setting the timing of accessing the transition condition determining unit immediately before determining the buffer circuit to be accessed next time, promptness of transmission and reception of communication data is always ensured.

According to a fifth aspect of the present invention, the number of buffers connected in parallel to the buffer circuit is set to three, and the transition condition judging section sets a buffer circuit to be accessed next time as an empty buffer determined by the empty buffer detecting means. Then, the transmission delay of the communication data between the communication control device and the central control device is equivalent to one access of each processing speed, and the speed-up can be reliably realized.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention.

FIG. 2 is a state transition diagram used by a transition condition determination unit 50.

FIG. 3 is a configuration block diagram of a conventional communication network system.

[Explanation of symbols]

 Reference Signs List 10 communication control device 20 central control device 30 buffer circuit 40 empty buffer detection unit 50 transition condition determination unit

Claims (5)

[Claims] 1. A communication control device (10) for exchanging data with another communication control device using a communication line, a central control device (20) provided one-to-one with the communication control device, In a communication network system having three or more buffer circuits (30) provided in parallel between a control device and a central control device, access is made from any of the communication control device and the central control device among the buffer circuits. Means (40) for detecting an unoccupied empty buffer; and for the communication control device and the central control device, a combination of a buffer circuit and an empty buffer currently accessed.
And a transition condition determining unit (50) for determining a buffer circuit to be accessed next time. 2. The communication network system according to claim 1, wherein said buffer circuit prevents a communication control device and a central control device from simultaneously accessing one buffer. 3. The communication control device according to claim 2, wherein when the access to the buffer circuit currently accessed is completed, the communication control device accesses the transition condition determination unit to determine a buffer circuit to be accessed next time. The communication network system as described. 4. When the access to the buffer circuit currently accessed is completed, the central control unit accesses the transition condition determination unit to determine a buffer circuit to be accessed next time. The communication network system as described. 5. The communication network system according to claim 1, wherein said transition condition determination unit sets a buffer circuit to be accessed next time to a free buffer obtained by said free buffer detecting means.