JPH1160395A - Compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compd. semiconductor device having a lattice relaxation layer capable of relieving the strain by the lattice mismatching between a substrate and an element forming layer and preventing the generation of cross hatch-like ruggedness on the surface. SOLUTION: Plural intermediate layers 13 constituting the relaxation layer 12 are formed of two-layered structures consisting of InGaAs layers 14 and GaAs layers 15. The In content in the InGaAs layers 14 arranged on the upper side is made larger, by which the inclination angle distribution of the crystal axes at the respective boundaries is confined to <=0.05 deg. or the lattice relaxation quantity is confined to <=0.1%, more preferably <=0.07%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compound semiconductor device provided with a lattice relaxation layer provided between a compound semiconductor substrate and an element formation layer to reduce distortion due to a difference in lattice constant between the two.

[0002]

2. Description of the Related Art In recent years, compound semiconductors have been used for highly efficient light emitting diodes and laser devices. In these devices, it has become increasingly necessary to form an element formation layer made of a group III-V mixed crystal compound semiconductor having a different lattice constant from the substrate on a substrate made of a compound semiconductor such as InP or GaAs.

However, when an element formation layer made of a group III-V mixed crystal compound is directly formed on a compound semiconductor substrate such as InP or GaAs, distortion due to lattice mismatch between the substrate and the element formation layer is large, Defects (transitions) occur in the element formation layer, and irregularities occur on the surface of the element formation layer or a layer formed thereon, which causes deterioration of element characteristics. For this reason,
III-V on compound semiconductor substrate such as InP or GaAs
In the case of forming an element formation layer made of a group mixed crystal compound, a strain caused by lattice mismatch is reduced by interposing a lattice relaxation layer between the two.

The lattice relaxation layer has a step-like structure and a continuous composition gradient structure. FIG. 6 shows that the horizontal axis represents In.
Taking the content, the vertical axis takes the thickness direction of the lattice relaxation layer,
It is a schematic diagram which shows the change of the In content in the thickness direction in the lattice relaxation layer of the conventional step-like structure. For example, the semiconductor substrate is made of GaAs, and the lattice relaxation layer is made of a plurality of InGaAs.
As shown in FIG. 6, the InGaAs layer constituting the lattice-relaxing layer has a lower IGaAs
n is formed to have a high n content, and the uppermost InG
The aAs layer has substantially the same composition as the element forming layer formed thereon.

As described above, by providing a plurality of InGaAs layers whose In content gradually changes between the semiconductor substrate and the element formation layer and gradually changing the horizontal lattice spacing at each interface, the semiconductor substrate is formed. Distortion due to a difference in lattice constant between the element and the element formation layer can be reduced. Also, in the lattice relaxation layer having the continuous composition gradient structure, the lattice relaxation layer is formed so that the In content continuously changes from the substrate side to the element formation layer side. As a result, a relaxation layer having a low threading dislocation density can be obtained, and distortion due to lattice mismatch can be reduced.

[0006]

However, in a conventional lattice relaxation layer having a step-like structure or a continuous composition gradient structure,
In each case, the surface of the lattice relaxation layer is cross-hatched (lattice)
There is a problem that unevenness occurs. The unevenness causes undulation in the element formation layer deposited on the lattice relaxation layer, and the effect of improving the element characteristics is not sufficient.

SUMMARY OF THE INVENTION An object of the present invention is to provide a compound semiconductor having a lattice relaxation layer capable of alleviating distortion due to lattice mismatch between a substrate and an element formation layer and preventing cross-hatched irregularities from being generated on the surface. It is to provide a device.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a compound semiconductor device having a lattice relaxation layer interposed between a compound semiconductor substrate and an element forming layer, which alleviates strain caused by a difference in lattice constant between the two. In the above, the lattice relaxation layer is composed of a plurality of intermediate layers having different lattice spacings in a horizontal direction, an interface between a lowermost intermediate layer of the plurality of intermediate layers and the semiconductor substrate, and an interface between the intermediate layers. Wherein the inclination angle distribution of the crystal axes is 0.05 ° or less.

[0009] The above-mentioned problem is also solved by a compound semiconductor device having a lattice relaxation layer interposed between a compound semiconductor substrate and an element forming layer, which alleviates strain caused by a difference in lattice constant between the two. The relaxation layer is composed of a plurality of intermediate layers having different lattice spacings in the horizontal direction, and the lattice relaxation amount at the interface between the lowermost intermediate layer of the plurality of intermediate layers and the semiconductor substrate and at the interface between the intermediate layers. Are all 0.1% or less.

In the present application, the tilt angle distribution refers to the distribution of the tilt angle of the crystal axis at the interface by a reciprocal lattice mapping method using an X-ray apparatus, and the standard deviation of the tilt angle of the crystal axis obtained from the result. Say. Hereinafter, the operation of the present invention will be described. FIG. 1 shows that GaAs substrate 1 has In
Misfit transition and In when GaAs layer 2 is formed
FIG. 3 is a schematic diagram showing a relationship with unevenness on the surface of a GaAs layer 2. In FIG. 1, the arrow indicates the direction of the crystal axis. As shown in FIG. 1, InGaAs is formed on a GaAs substrate 1.
When the layer 2 is formed, a misfit transition 3 occurs between the two, and the crystal axis is inclined in the vicinity of the location where the misfit transition 3 has occurred. When the InGaAs layer 2 is formed, the InGaAs layer 2 grows in the crystal axis direction. Therefore, if the inclination angle of the crystal axis is large, cross-hatched irregularities may be generated on the surface of the InGaAs layer 2.

The inventors of the present application have examined the relationship between the inclination angle distribution of the crystal axis and the cross-hatch irregularities by reciprocal lattice mapping using an X-ray apparatus. By reciprocal lattice mapping, the spread of reciprocal lattice points can be examined. The spread of reciprocal lattice points corresponds to the tilt angle distribution of the crystal axis. Therefore, reciprocal lattice mapping is performed under the (004) reflection condition,
The tilt angle of the crystal axis was calculated from the half width, and the tilt angle distribution was determined based on the calculated result. As a result, it has been found that when the inclination angle distribution of the crystal axes is 0.05 ° or less, almost no cross-hatch irregularities are observed.

The inventors of the present application have examined the relationship between the distribution of the tilt angle of the crystal axis and the amount of lattice relaxation. The result is shown in FIG. However, the lattice relaxation amount f is defined as a _{sub where} the horizontal lattice spacing of the GaAs substrate is a _sub , and In is formed on the GaAs substrate.
Assuming that the average lattice spacing in the horizontal direction of the GaAs layer is a _epi , it is defined by the following equation (1). f = (a _epi− a _sub ) / a _sub (1) As is apparent from FIG. 2, the inclination angle distribution of the crystal axis increases as the lattice relaxation amount f increases. If the lattice relaxation amount f is 0.1% or less, the inclination angle distribution is set to 0.0%.
5 ° or less, and the lattice relaxation amount f is 0.07%
Below, the inclination angle distribution becomes extremely small.

FIG. 3 is a schematic diagram showing the horizontal lattice spacing at each interface of the compound semiconductor device of the present invention and the intermediate layer constituting the lattice relaxation layer of the compound semiconductor device.
As shown in FIG. 3, the compound semiconductor device of the present invention
Lattice relaxation layer 8 formed by laminating a plurality of intermediate layers 9 on substrate 1
have. For example, the lattice relaxation amount f1 of the (k + 1) th intermediate layer 9 with respect to the (k) th intermediate layer 9 is obtained by setting the horizontal average lattice spacings of the kth intermediate layer 9 and the (k + 1) th intermediate layer 9 to a _k and a _k , respectively. _{If +1} is set, it is approximately obtained by the following equation (2).

F ₁ = ( _{ak + 1− ak} ) / _asub (2) In the present invention, the lattice relaxation amount at the interface between the substrate 1 and the lowermost intermediate layer 9 and at the interface between the intermediate layers 9 To 0.1
% Or less, more preferably 0.07% or less. Thereby, the inclination angle distribution of the crystal axis at each interface is 0.05
° or less, which prevents the formation of cross-hatch-like irregularities on the surface of the lattice relaxation layer 8, and provides a compound semiconductor device having good characteristics.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 4 is a schematic diagram showing the compound semiconductor device according to the embodiment of the present invention and the amount of lattice relaxation at each interface of a plurality of intermediate layers constituting the lattice relaxation layer of the semiconductor device. In FIG. 5, the horizontal axis indicates the In content, and the vertical axis indicates the thickness direction of the lattice relaxation layer.
It is a figure which shows the change of the thickness direction of content.

On the GaAs substrate 11, a lattice relaxation layer 12 is formed. The lattice relaxation layer 12 is formed by laminating a plurality of intermediate layers 13, and each intermediate layer 13 is formed of a lower InGaAs.
It is composed of two layers, a layer 14 and an upper GaAs layer 15. Further, the InGaAs layer 14 of each intermediate layer 13
The higher the number is, the higher the In content is. That, InGaAs layer 14 of the lowermost intermediate layer 13 is made of In _0.06 Ga _{0. 94} As, the next intermediate layer 13
The InGaAs layer 14 is composed of In _0.07 Ga _0.93 As, and the In / Ga content ratio of each InGaAs layer 14 is slightly different, as shown in FIG.
The compound semiconductor device of the present embodiment has an InGaAs layer 1
4 and a plurality of intermediate layers 13 each composed of a GaAs layer 15. In the horizontal direction, the In content in the InGaAs layer 14 of each intermediate layer 13 is increased as the upper layer is disposed. Since the lattice spacing is changed little by little, the lattice relaxation amount at the interface between the substrate 11 and the lowermost intermediate layer 13 and at the interface between the intermediate layers 13 is 0.1 mm.
07% or less. Thereby, the inclination angle distribution of the crystal axis at each interface becomes 0.05 ° or less, cross-hatched irregularities are prevented from being generated on the surface of the lattice relaxation layer 12, and the characteristic deterioration of the semiconductor element is avoided. The effect is obtained.

Hereinafter, a method for manufacturing the compound semiconductor layer of the present embodiment will be described. First, for example, metal organic chemical vapor deposition (MOCVD) is formed on a substrate 11 made of GaAs.
InGaAs layer (In _0.06 G)
a _0.94 As) 14 is formed to a thickness of about 0.2 μm. Thereafter, a sufficient thermal annealing treatment is performed. As a result, the amount of lattice relaxation at the interface between the substrate 11 and the InGaAs layer 14 becomes about 0.07%, and the distribution of the tilt angles of the crystal axes becomes sufficiently small.

At this point, the InGaAs layer 14 has a residual strain. This residual strain is a compressive strain, and its magnitude is equal to or larger than the critical strain amount at which a misfit transition occurs. Therefore, the I.I.
When an InGaAs layer having a different n content is deposited, the critical strain is exceeded, so that a new misfit transition occurs at the interface between the InGaAs 14 and the substrate 11 and the lattice relaxation amount cannot be maintained at 0.1% or less. .

Therefore, it is necessary to form a layer made of a material having a tensile strain on the InGaAs layer 14 so as to cancel the compressive strain. In this embodiment, a GaAs layer 15 is formed as this layer. The first (lowermost) intermediate layer 13 is constituted by the two layers of the InGaAs layer 14 and the GaAs layer 15. The material having a tensile strain may be any material as long as the lattice spacing in an unstrained state is smaller than the lattice spacing in the horizontal direction of the InGaAs layer 14, and may be formed of InGaAs having a small In content.

Next, InGaAs is formed on the first intermediate layer 13.
An s (In _0.07 Ga _0.93 As) layer 14 is formed, and this In
The GaAs layer 15 is formed on the GaAs layer 14 to form the second intermediate layer 13. In this way, In
Intermediate layer 13 composed of GaAs layer 14 and GaAs layer 15
Are laminated to form the lattice relaxation layer 12. The lattice-relaxed layer 12 formed in this manner is made of InGa of each intermediate layer 13.
Since the higher the In content in the As layer 14 is, the higher the upper layer, the lattice spacing in the horizontal direction of the uppermost intermediate layer 13 is increased by an amount corresponding to the total relaxation amount of each intermediate layer 13.

Thus, the lattice spacing of the uppermost layer of the lattice relaxation layer can be matched with the lattice spacing of the element formation layer, and there is no possibility that the characteristics of the element formed in the element formation layer will be impaired. Further, it is possible to avoid the occurrence of cross-hatched irregularities on the surface of the lattice relaxation layer.

[0022]

As described above, according to the present invention,
The interface between the lowermost intermediate layer of the plurality of intermediate layers constituting the lattice relaxation layer and the semiconductor substrate, and the inclination angle distribution of the crystal axis at the interface of each intermediate layer are all set to 0.05 ° or less. Or the lattice relaxation amount at the interface between the lowermost intermediate layer and the semiconductor substrate and at the interface between the intermediate layers is set to 0.1% or less. Distortion due to a difference in lattice constant can be alleviated, and cross-hatched irregularities can be prevented from being generated on the surface of the relaxation layer, thereby avoiding deterioration of device characteristics. Therefore, the present invention makes a great contribution to improving the characteristics of the compound semiconductor device.

[Brief description of the drawings]

FIG. 1 is a diagram (part 1) illustrating the principle of the present invention;
This shows a state when an InGaAs layer is formed on an As substrate.

FIG. 2 is a diagram (part 2) illustrating the principle of the present invention, and is a diagram illustrating a relationship between a lattice relaxation amount and a tilt angle distribution.

FIG. 3 is a diagram (part 3) illustrating the principle of the present invention, and is a diagram illustrating a horizontal lattice spacing at each interface between a compound semiconductor device and an intermediate layer constituting a lattice relaxation layer of the compound semiconductor device. .

FIG. 4 is a schematic diagram showing a compound semiconductor device according to an embodiment of the present invention and the amount of lattice relaxation at each interface of a plurality of intermediate layers constituting a lattice relaxation layer of the semiconductor device.

FIG. 5 shows I in the relaxation layer of the compound semiconductor device of the embodiment.
It is a figure showing distribution of n content.

FIG. 6 is a schematic diagram showing a change in the In content in the thickness direction of a conventional lattice-relaxed layer having a step-like structure.

[Explanation of symbols]

 1,11 GaAs substrate 2,14 InGaAs layer 8,12 lattice relaxation layer 9,13 intermediate layer 15 GaAs layer

Claims (6)

[Claims] 1. A compound semiconductor device having a lattice relaxation layer interposed between a compound semiconductor substrate and an element formation layer and configured to relax strain caused by a difference in lattice constant between the two. And a plurality of intermediate layers having different lattice spacings in the directions, and an interface between the lowermost intermediate layer of the plurality of intermediate layers and the semiconductor substrate, and an inclination angle distribution of a crystal axis at an interface of each intermediate layer. Also 0.05
° or less. 2. The compound semiconductor device according to claim 1, wherein each of the plurality of intermediate layers includes a first layer having a compressive strain and a second layer having a tensile strain. 3. The first layer is made of InGaAs having a higher In content as it is disposed on the upper side, and the first layer is made of InGaAs.
3. The compound semiconductor device according to claim 2, wherein said layer is made of a material having the same composition as said substrate. 4. A compound semiconductor device having a lattice relaxation layer interposed between a compound semiconductor substrate and an element formation layer and configured to relax strain caused by a difference in lattice constant between the two. A plurality of intermediate layers having different lattice spacings in the directions, and an interface between the lowermost intermediate layer of the plurality of intermediate layers and the semiconductor substrate and an interface between the respective intermediate layers have a lattice relaxation amount of 0. A compound semiconductor device having a content of 1% or less. 5. The compound semiconductor device according to claim 4, wherein each of the plurality of intermediate layers includes a first layer having a compressive strain and a second layer having a tensile strain. 6. The first layer is made of InGaAs having a higher In content as it is disposed on the upper side, and the first layer is made of InGaAs.
6. The compound semiconductor device according to claim 5, wherein said layer is made of a material having the same composition as said substrate.