JPH1155570A - Solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an image data quantity received by an image processing unit by minimizing increase in a scanning frequency while processing a high definition image in the image pickup element. SOLUTION: The solid-state image pickup element is provided with pixels 11 being pluralities of photoelectric conversion means, a scanning circuit 12 that scans the pixel, a signal evaluation circuit 14 that specifies a significant photoelectric conversion area from a photoelectric conversion signal outputted from the pixel 11, and a timing generating circuit 15 that controls the pixel 11 in the photoelectric conversion area specified significant by a scanning clock CL changed in response to the photoelectric conversion area specified significant by the signal evaluation circuit 14 by scanning a required scanning among scanning lines H1-H4 at the scanning circuit 12 to read a photoelectric conversion signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image input device, and more particularly to a solid-state image sensor suitable for inputting image information to a computer or the like.

[0002]

2. Description of the Related Art A solid-state image pickup device as one of image input devices has a MOS type image pickup device provided with a photodiode and a signal readout transistor for sequentially reading out electric signals photoelectrically converted by the photodiode, a photodiode, and the like. There is a CCD type image pickup device including a CCD for transferring signal charges. In the former case, most of the pixels can be used as photodiodes, which are effective light-receiving parts.On the other hand, there is a problem in that image quality is impaired due to switching noise generated when selecting pixels. I was

In recent years, as the performance of an imaging system has become higher, the solid-state imaging device also needs to have higher definition, and the number of pixels in a CCD type imaging device has also increased. However, since the CCD type image pickup device has pixels composed of a photodiode and a CCD, the effect of a reduction in the area per pixel increases due to the increase in the number of pixels, and the amount of signal charges that can be handled is reduced. Thus, it is difficult to increase the number of pixels.

For this reason, taking advantage of the characteristics of the MOS type image pickup device, which requires a small area for signal reading inside the pixel,
Based on the progress of semiconductor processing technology, an amplification type image sensor incorporating a simple amplifier for each pixel is being studied.
(Amplified MOS Intelligent Imager), BASIS (B
ase Stored Image Sensor), CMD (Charge Modulati)
on Device). For example, AMI is reported in pp. 51-52 (Ando et al., "Random noise of amplifying solid-state imaging device") at the 1986 National Convention of the Institute of Television Engineers of Japan.

Hereinafter, a conventional AMI will be described with reference to FIG. FIG. 8A shows a configuration of an AMI solid-state imaging device, and FIG. 8B shows a configuration of each unit pixel. As shown in the figure, the two-dimensionally arranged pixels 81 are provided with a vertical scanning circuit 8.
2, a power supply voltage Vdd is supplied, and signal lines V1 to V4 for opening and closing the vertical switch transistor TVL are connected to reset signal lines R1 to R4 for opening and closing the reset transistor TR. Here, the signal line V and the reset signal line R are shared, and are connected so that the reset is performed when the signal line V is selected. The signal lines H1 to H4 from the horizontal scanning circuit 83 open and close the horizontal switch transistor THL.

A specific signal reading operation is as follows. First, the signal line V1 is selected by the vertical scanning circuit 82, then the signal lines H1 to H4 are sequentially scanned by the horizontal scanning circuit 83, and the signal as the image information of the pixel 81 along the signal line V1 from the signal lines S1 to S4. The current is sequentially read out, and voltage-converted and taken out by an output circuit 84 including a load resistor and a source follower. Similarly, after the signal line V2 is selected (the reset signal line R1 is selected at the same time), the signal lines H1 to H4 are sequentially scanned, and the signal lines S1 to S4 are scanned.
, A signal current is sequentially read out from the memory cell, and this operation is repeated for the signal line V3 and thereafter to read out signals for all pixels.

A specific signal reading operation for each pixel is as follows.
It looks like this: The photodiode PD, which is a photoelectric conversion unit in the pixel, has a reset transistor TR in an initial state.
Is set to the initial voltage. Electrons generated by photoelectric conversion during the light accumulation time of one frame are accumulated in the photodiode PD, and as a result, the potential of the photodiode PD decreases. The potential of the transistor T
When the voltage is applied to the gate of A and amplified and the vertical switch transistor TVL is selected, a current modulated by a change in the potential of the photodiode PD is read out to the signal line S. After the signal reading, the reset transistor TR is opened and closed for the selected vertical pixel column to reset the potential of the photodiode PD.

As described above, in the amplification type image pickup device, the signal charge is amplified by the amplifying transistor TA, so that the switching noise component which is a disadvantage of the conventional MOS type image pickup device is relatively reduced, thereby improving the performance. Is being planned.

[0009]

Although this amplification type imaging device is suitable for increasing the number of pixels, the following problem arises when the number of pixels further increases.

Assuming that the number of read frames per second of the solid-state image sensor is constant, the scanning speed becomes higher in proportion to the increase in the number of pixels of the solid-state image sensor. Further, it is necessary to widen the signal line between the output circuit of the solid-state imaging device and the image processing device connected to the next stage. Further, in the case of an image processing system using such a solid-state imaging device, the processing time required for image processing and recognition is significantly increased due to an increase in the amount of image data to be handled.

For example, the solid-state imaging device most frequently used at present has an effective pixel number of 380,000 pixels, and the data rate of pixel information, ie, the scanning frequency of the solid-state imaging device is 1
4.32 MHz. As a solid-state imaging device used for high-definition images such as high-definition images, those having an effective pixel number of 2 million pixels have been put to practical use. In that case, the scanning frequency becomes 74.25 MHz, and the scanning frequency of the scanning circuit is further increased Get higher.

An object of the present invention is to provide a solid-state imaging device capable of suppressing an increase in scanning frequency even when the number of pixels has increased in view of the above problems.

[0013]

According to a first aspect of the present invention, there is provided a solid-state imaging device comprising: a plurality of photoelectric conversion units; a scanning unit that scans the photoelectric conversion units; and a photoelectric conversion signal output from the photoelectric conversion units. A signal evaluation unit for specifying a significant photoelectric conversion region, and the scanning unit for converting the photoelectric conversion unit of the photoelectric conversion region specified as significant by a scanning clock changed according to the photoelectric conversion region specified as significant by the signal evaluation unit. And control means for controlling so as to read out the photoelectric conversion signal by scanning at the same time.

According to a second aspect of the present invention, in the solid-state imaging device according to the first aspect, the scanning clock is:
The frequency is lower than a scanning clock for scanning all of the plurality of photoelectric conversion units in a predetermined direction within the same period.

According to a third aspect of the present invention, there is provided the solid-state imaging device according to the first aspect, wherein the photoelectric conversion means is a two-dimensional imaging device.
The signal evaluation means is arranged in a dimension, and the signal evaluation means specifies a significant photoelectric conversion area based on a result of integrating the photoelectric conversion signal output from the photoelectric conversion means in the vertical direction and the horizontal direction. .

According to a fourth aspect of the present invention, in the solid-state image sensing device according to the first or third aspect, the signal evaluation means determines a comparison result between each output from the photoelectric conversion means and a reference signal. It is characterized in that a significant photoelectric conversion area is specified based on the area.

According to a fifth aspect of the present invention, in the solid-state imaging device according to the first or third aspect, the signal evaluation means includes a difference value between adjacent outputs from the photoelectric conversion means and a reference signal. A significant photoelectric conversion region is specified based on the comparison result with the above.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Even when a high-definition image is handled, the whole area of the image is rarely needed, and in many cases, a meaningful image area is sufficient. Therefore, the solid-state imaging device of the present invention pays attention to this, and before actually reading out image information, a necessary image area of the input image,
That is, a significant photoelectric conversion area is determined based on the properties of the image,
The determination result is fed back to a scanning circuit that scans each pixel, and a scanning clock of the scanning circuit is changed according to a required image area to scan and capture an actual image, thereby handling a high-definition image. In addition, an increase in the scanning frequency of the solid-state imaging device is suppressed, and the amount of image data input to the image processing apparatus is reduced.

Hereinafter, an embodiment in which the present invention is applied to a one-dimensional solid-state image sensor will be described with reference to FIG. FIG. 1A shows the configuration of the solid-state imaging device according to the present embodiment.
(B) shows the configuration of each unit pixel. The transistor used in this embodiment is a MOS transistor. As shown, Vdd is supplied to the pixels 11 arranged one-dimensionally, and a read signal line V for opening and closing the gate of the read transistor TV from the scanning circuit 12 and a reset for opening and closing the gate of the reset transistor TR. The signal line R is connected. From the scanning circuit 12, signal lines H1 to H1 for opening and closing the gate of the switch transistor TH are provided.
H4 is connected.

The signal lines S1 to S4 are connected to the signal evaluation circuit 1
4 and all the pixels 11
The photoelectrically converted signal is detected in the above, a significant photoelectric conversion region is determined from the signal, and the selection signal S indicating the region is determined.
E is generated. The timing generation circuit 15 outputs the selection signal S
A scanning clock CL for driving the signal line H according to E and scanning circuit data P indicating the starting position of the signal line H are supplied to the scanning circuit 1.
2, the scanning circuit 12 drives the necessary signal lines H to perform actual reading. That is, after the photoelectrically converted signal in the pixel 11 is evaluated and a significant photoelectric conversion region is specified, only that region is driven and read.

A specific signal reading operation is as follows. First, the scanning circuit 12 opens the readout signal line V, sequentially scans only the signal line H corresponding to the significant photoelectric conversion region, reads out a signal current as image information from the signal line S, and reads the load resistance and the source follower. The voltage is converted by an output circuit 13 consisting of After that, the reset signal line R is opened, each pixel is reset, and the reading of one frame is completed.

A specific signal reading operation for each pixel is as follows.
It looks like this: Initially reset transistor T
Through R, the photodiode PD is set to the initial voltage. Electrons generated by photoelectric conversion during the light accumulation time of one frame are accumulated in the photodiode PD, and the potential of the photodiode PD decreases. When the read transistor TV is selected, the potential is input to the gate of the amplification transistor TA and amplified. The current modulated by the potential change of the photodiode PD is read out to the signal line S. After this signal is read, the gate is reset by opening and closing the gate of the reset transistor TR.

Next, the operation of evaluating the photoelectrically converted signal performed before the actual read operation will be described. A signal for each pixel 11 is input to the signal evaluation circuit 14, and a significant photoelectric conversion region is specified from all the photoelectric conversion regions by a signal detection operation described below. Select

FIG. 2 shows the details of the signal evaluation circuit 14.
This circuit includes a detection circuit 21 that receives a signal current from each pixel and performs signal detection for each pixel, and a determination circuit 2 that receives a signal from each detection circuit 21 and determines whether the signal is significant or not.
2 and a signal readout circuit 23 including a selection switch for serially inputting the determination result from the determination circuit 22 and serially outputting the determination result as a selection signal SE.

Next, a specific example of the detection circuit 21 of FIG. 2 is shown in FIG.
(A). The signal current of each pixel is converted into a voltage by the load resistor 31, impedance-converted by the transistor 32 and the load resistor 33, and output.

Next, a specific example of the judgment circuit 22 shown in FIG.
(A). FIG. 4A is a circuit for determining an area based on the brightness of an image. The output from the detection circuit 21 is input to the comparator 41, the input signal is compared with the reference voltage Vref, and the operation is performed so as to output when the result is large. For this reason, the comparator 41 outputs only a pixel that has output a signal larger than the reference signal corresponding to a certain reference brightness, and uses it as the selection signal SE. By selecting a pixel corresponding to the signal output from the determination circuit 22 in this manner, a photoelectric conversion region having a certain brightness or higher can be specified. When a plurality of regions are obtained at this time, it is also effective to make the entire inside of the selected region at both ends significant.

FIG. 4B shows another specific example of the judgment circuit 22 shown in FIG. FIG. 4B shows a circuit for determining an area based on the magnitude of a signal change in an image. An absolute value difference unit is provided so as to obtain an absolute value difference between outputs of the detection circuits 22 of adjacent pixels, and the output is input to a comparator 43. The comparator 43 outputs the selection signal SE only between pixels that output a signal change greater than the reference voltage Vref corresponding to the magnitude of the predetermined absolute value difference. In this manner, a photoelectric conversion region having a change equal to or more than a predetermined value can be specified. In this case, it is also effective to make the entirety of the inside of the selection area at both ends of the plurality of selection areas significant.

FIG. 5 shows the details of the timing generation circuit 15. The selection signal SE from the signal evaluation circuit 14 is input to the duty ratio detection circuit 51, where the ratio of significant pixels is calculated from all the pixels, and the calculation result is input to the voltage controlled oscillator (VCO) 52. The oscillation frequency is controlled in accordance with the ratio and used as the scan clock CL. That is, the lower the ratio of significant pixels among all the pixels, the lower the scanning clock CL is. Alternatively, a plurality of frequency-divided oscillator outputs may be prepared and selected from among them according to the ratio of significant pixels among all pixels. Furthermore, a low-pass filter may be used for the duty ratio detection circuit 51, and the oscillation frequency may be controlled by the DC component obtained therefrom.

On the other hand, the selection signal S from the signal evaluation circuit 14
E is input to the significant pixel determination circuit 53, and the selection signal SE
Is taken as scanning circuit data P indicating the scanning circuit start position. In this way, if the scanning frequency for scanning the scanning circuit is controlled according to the ratio of the selected pixel area to the entire pixel area, the solid-state imaging device can be scanned according to the amount of information.

Next, the generation of the scan clock CL in the above-described embodiment will be described with reference to FIG. Although the solid-state imaging device in FIG. 1 has four pixels, it is actually a solid-state imaging device having a large number of pixels in one dimension, and FIG. 6A is a schematic diagram of a pixel row. When incident light is incident on these pixels as shown in FIG. 6B, a selection signal SE having a higher level than the reference voltage Vref is generated by the signal evaluation circuit as shown in FIG. 6C. With respect to such incident light, FIG. 6D shows scanning circuit data P 'indicating the scanning start position of the conventional scanning circuit, and FIG.
FIG. 6F shows the read signal in FIG. 6E. On the other hand, in the present invention, the scanning circuit data P indicating the scanning start position of the scanning circuit for such incident light is shown in FIG.
FIG. 6 (g) shows the scanning clock CL in FIG. 6 (h), and FIG. 6 (i) shows the readout signal on the same time axis as the conventional one. For this reason, in the related art, the reading was performed for all the pixels without changing the scanning clock even if the significant area was part, but in the present invention, the scanning was performed for all the pixels in the same frame. The reading of a significant area is performed by controlling the scanning clock at a frequency lower than that of the scanning clock.

Next, an embodiment in which the present invention is applied to a two-dimensional solid-state image sensor will be described with reference to FIG. FIG. 7A shows the configuration of the solid-state imaging device according to the present embodiment.
(B) shows the configuration of each unit pixel. Basically, the signal evaluation performed by the above-described one-dimensional solid-state imaging device is developed two-dimensionally. However, as shown in the figure, pixels 71 arranged two-dimensionally and line-sequentially selected by actual signal reading. The vertical scanning circuit 72 to which the connected signal lines V1 to V4 and the reset signal lines R1 to R4 for opening and closing the gate of the reset transistor TR are connected, and the signal lines H1 to H4 for sequentially opening and closing the gate of the horizontal switch transistor THL. Are connected, an output circuit 74 composed of a load resistor and a source follower for converting a signal current as image information from each pixel 71 into a voltage, and a vertical signal for evaluating signals in signal lines V1 to V4. An evaluation circuit 75; a horizontal signal evaluation circuit 76 for evaluating signals in the signal lines S1 to S4; a selection signal VSE output from the vertical signal evaluation circuit 75; Scan clock VCL for scanning signal line V corresponding to a photoelectric conversion region determined to be significant among signal lines V1 to V4 of vertical scanning circuit 72 in response to selection signal HSE output from value circuit 76. And scanning circuit data VP indicating the scanning start position, and a scanning clock HCL for scanning the signal line H corresponding to the photoelectric conversion region determined to be significant among the signal lines H1 to H4 of the horizontal scanning circuit 73. And a timing generation circuit 77 which outputs scanning circuit data HP indicating the scanning start position.

The details of the vertical signal evaluation circuit 75 and the horizontal signal evaluation circuit 76 are shown in FIG. 2, and are connected to the detection circuit 21 for each signal line V and signal line S.
2, the selection signals VSE, H from the signal readout circuit 23.
SE is output. Here, the detection circuit 21 of each signal evaluation circuit has the configuration shown in FIG. 3B, and the terminals a, b,
c, a switch 34 for switching to c, and in signal evaluation, a signal current from each pixel is converted into a voltage by a load resistor 35,
Impedance conversion is performed by the transistor 36 and the load resistor 37. The determination circuit 22 of each signal evaluation circuit has the configuration shown in FIG.

Next, the operation of signal evaluation performed before the actual signal read operation will be described. This operation is performed in two stages of horizontal signal detection and vertical signal detection.

First, when a horizontal signal is detected, the switch 34 of the detection circuit 21 in the vertical signal evaluation circuit 75 is set to the power supply Vdd.
(Terminal a), and the switch 34 of the detection circuit 21 in the horizontal signal evaluation circuit 76 is connected to the gate (terminal c) of the transistor 36. As a result, all the signal lines V in the vertical direction become power supply lines, and the signal current generated in the amplifying transistor TA according to the potential of the photodiode PD for each pixel passes through the signal lines S1 to S4, and the horizontal signal evaluation circuit. At 76, the signals are integrated and detected for each signal line S.

Next, when a vertical signal is detected, the switch 34 of the detection circuit 21 in the horizontal signal evaluation circuit 76 is connected to the power supply Vdd (terminal a).
The switch 34 of the detection circuit 21 is connected to the gate (terminal c) of the transistor 36. As a result, all the signal lines S in the horizontal direction become power supply lines, and the signal current generated by the amplifying transistor TA according to the potential of the photodiode PD for each pixel passes through the signal lines V1 to V4, and the vertical signal evaluation circuit At 75, it is integrated and detected for each signal line V.

Thus, the selection signal VS indicating the significant photoelectric conversion area for the horizontal and vertical pixel columns, respectively.
E, HSE, and the timing generation circuit 77 is lower than the scan clock for scanning all pixels in each direction in the same frame according to the significant photoelectric conversion area for the horizontal and vertical pixel columns. The significant scan of the photoelectric conversion region is performed by controlling the scan clocks VCL and HCL of the frequency.

The specific signal reading operation is as follows. The power supply voltage Vd is applied to one signal line V selected corresponding to the significant photoelectric conversion region by the vertical scanning circuit 72 by the switch 34 of the detection circuit 21 of the vertical signal evaluation circuit 75.
d (terminal a) is connected, the other unselected signal lines V are connected to high impedance (terminal b) by the switch 34, and the signal currents of only significant pixel columns along the selected signal line V are connected. Is read out to the signal line S, and the horizontal scanning circuit 73 sequentially scans the selected signal line H corresponding to the significant photoelectric conversion area to perform reading. Hereinafter, similarly, the signal lines V selected sequentially corresponding to the significant photoelectric conversion regions are sequentially scanned, and the image information is read from the pixels corresponding to the significant photoelectric conversion regions. In this embodiment, the scanning of the signal line V is controlled by switching the switch 34 in accordance with an instruction from the vertical scanning circuit 72. However, a similar switch is provided in the vertical scanning circuit 72 so that Vdd is directly supplied. Is also good.

A specific signal reading operation for each pixel is as follows.
It looks like this: The photodiode PD is set to the initial voltage through the reset transistor TR. 1
Electrons generated by photoelectric conversion during the light accumulation time of the frame lower the potential of the photodiode PD. The modulated potential is input to the gate of the amplifying transistor TA, amplified, and the current modulated by the potential change of the photodiode PD is selected by the selected signal line V to the signal line S.
Is read out. After this signal is read, the reset is performed by opening and closing the gate of the reset transistor TR.

The two-dimensional solid-state imaging device described above has 16
Although the case of pixels has been described, it goes without saying that the present invention can be similarly applied to a two-dimensional solid-state imaging device having more pixels.

[0040]

According to the present invention, a necessary area of an image input to a solid-state image sensor is specified based on the properties of the image, and the result is fed back to scanning means and only the required area is output to the outside. Accordingly, it is possible to suppress an increase in the scanning frequency of the solid-state imaging device and to reduce the amount of image data input to the image processing device while handling a high-definition image.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a one-dimensional solid-state imaging device according to an embodiment;

FIG. 2 is a diagram illustrating details of a signal evaluation circuit according to the present embodiment;

FIG. 3 is a diagram showing a detection circuit of the signal evaluation circuit according to the present embodiment.

FIG. 4 is a diagram showing a determination circuit of the signal evaluation circuit according to the present embodiment.

FIG. 5 is a diagram illustrating details of a timing generation circuit according to the present embodiment;

FIG. 6 is a diagram for explaining a state of scanning according to the present embodiment.

FIG. 7 is a diagram showing a two-dimensional solid-state imaging device according to the present embodiment.

FIG. 8 is a diagram showing a conventional two-dimensional solid-state imaging device.

[Explanation of symbols]

 11, 71 pixels 12 scanning circuit 13, 74 output circuit 14 signal evaluation circuit 15, 77 timing generation circuit 72 vertical scanning circuit 73 horizontal scanning circuit 75 vertical signal evaluation circuit 76 horizontal signal evaluation circuit

Claims (5)

[Claims] A plurality of photoelectric conversion means; a scanning means for scanning the photoelectric conversion means; a signal evaluation means for specifying a significant photoelectric conversion area from a photoelectric conversion signal output from the photoelectric conversion means; Control means for controlling the scanning means to scan the photoelectric conversion means of the photoelectric conversion area specified as significant by the scanning means and to read out the photoelectric conversion signal with the scanning clock changed according to the photoelectric conversion area specified as significant by the evaluation means. And a solid-state image sensor. 2. The solid-state imaging device according to claim 1, wherein the scan clock has a lower frequency than a scan clock that scans all of the plurality of photoelectric conversion units in a predetermined direction within the same period. 3. The photoelectric conversion means is arranged in a two-dimensional manner, and the signal evaluation means has a significant value based on a result of integrating a photoelectric conversion signal output from the photoelectric conversion means in a vertical direction and a horizontal direction. The solid-state imaging device according to claim 1, wherein a photoelectric conversion region is specified. 4. The signal evaluation device according to claim 1, wherein said signal evaluation means specifies a significant photoelectric conversion area based on a comparison result between each output from said photoelectric conversion means and a reference signal. Solid-state imaging device. 5. The method according to claim 1, wherein the signal evaluation unit specifies a significant photoelectric conversion area based on a comparison result between a difference value between adjacent outputs from the photoelectric conversion unit and a reference signal. The solid-state imaging device according to claim 3.