JPH1154742A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be made uniform in device characteristics and easily integrated. SOLUTION: This device is equipped with a gate insulating film 12 formed on a semiconductor substrate 11, a gate electrode 13 used for inducing a conductive region 18 on the surface of the semiconductor substrate 11, a gate electrode 14 used for inducing a conductive region 19 adjacent to the conductive region 18, and impurity regions 16 and 17 formed adjacent to the induced conductive regions 18 and 19 respectively. An Esaki diode is formed of the induced conductive regions 18 and 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device that exhibits a negative differential resistance by a tunnel effect.

[0002]

2. Description of the Related Art The performance of a silicon LSI has been improved by miniaturizing a CMOS device. Now, a 0.1 μm class ULSI is also being developed. However, CMOS operation becomes very difficult at a boundary of 0.1 μm. The cause is
This is a short channel effect typified by punch-through.

In order to overcome the limitations of the CMOS device, a device based on a new operation principle has been proposed (Japanese Patent Application No. 8-67628). FIG. 10 is a diagram showing a cross-sectional configuration of such an element. Here, it is called a surface junction tunnel element. The structure is similar to a normal MOSFET, and has an advantage that it can be easily manufactured by a CMOS process. The difference is that the impurity types of the source and the drain are opposite to each other.

The operation of the surface junction tunnel device will be described below. If a voltage is not applied to the gate, normal pn junction characteristics appear between the source and the drain, and a current flows when a constant drain voltage is applied. On the other hand, when a voltage is applied to the gate, an n ⁺ -p ⁺⁺ junction, a so-called Esaki diode, is formed near the drain. The Esaki diode exhibits a negative differential resistance characteristic by a tunnel effect, and the surface junction tunnel element also has a negative differential resistance function. FIG. 11 shows the current-voltage characteristics of the surface junction tunnel element. The surface junction tunnel element has both a current modulation function (switching function) by a gate and an Esaki diode function.
Overcoming the disadvantages of Esaki diode circuits (Japanese Patent Application No. 8
-246697).

Since the surface junction tunnel element has only one depletion layer region, the problem of punch-through does not occur in principle. In addition, since a micro phenomenon called a tunnel effect is used, the device operates normally even in an ultrafine region. Furthermore, since the element has functionality, there is an advantage that a functional circuit can be easily configured (Japanese Patent Application No. Hei 8-24669).
7).

However, when a surface junction tunnel device was actually manufactured, it became clear that the characteristics of each device varied greatly. The cause lies in the method of forming the p ⁺⁺ region. Although ion implantation is used to form the p ⁺⁺ region, the impurity profile varies in processing.
Since the tunnel characteristic is very sensitive to the impurity profile, the processing variation appears as the characteristic variation as it is. Therefore, it is very difficult to use it for an LSI that integrates elements.

[0007]

As described above, the surface junction tunnel element is very promising as a next-generation ultra-fine electronic device. There was a problem that the conversion was difficult. SUMMARY OF THE INVENTION It is an object of the present invention to provide an element that can achieve uniform element characteristics and can easily achieve integration.

[0008]

According to the present invention, there is provided a semiconductor device comprising: an insulating film formed on a semiconductor substrate; and at least one first conductive type of first conductive type formed on the insulating film on the surface of the semiconductor substrate. At least one first electrode for inducing a conductive region, and at least one second conductive type formed on the insulating film and adjacent to the at least one first conductive region on a surface of the semiconductor substrate. At least one second electrode for inducing a second conductive region, and a first impurity region of a first conductivity type formed adjacent to at least one region where the first conductive region is induced. When,
A second conductivity type second impurity region formed adjacent to at least one region where the second conductive region is induced.

In the above invention, a predetermined potential is applied to the first electrode and the second electrode, so that the surfaces of the semiconductor substrate under the first electrode and the second electrode have the first conductivity type opposite to each other. And the second conductive region are induced. As a result, an Esaki diode having a negative differential resistance characteristic is formed at the boundary between the first conductive region and the second conductive region. As described above, the first electrically formed semiconductor surface is formed.
In addition, since the surface junction tunnel element is realized by using the second conductive region, the processing variation does not affect the tunnel characteristic as in the related art. Therefore, it is possible to realize a semiconductor device having uniform device characteristics without variation in characteristics and suitable for ultraminiaturization and integration.

The semiconductor device according to the present invention comprises a first insulating film formed on a semiconductor substrate and at least one of a first conductivity type formed on the first insulating film on a surface of the semiconductor substrate. At least one first electrode for inducing a first conductive region, a second insulating film formed on the first electrode, and on the first insulating film and the second insulating film A semiconductor layer formed on the surface of the semiconductor substrate to induce at least one second conductive region of a second conductivity type adjacent to at least one first conductive region on the surface of the semiconductor substrate and through the first insulating film; At least one second electrode for injecting and releasing charge between a substrate and at least one first electrode, and adjacent to a region where at least one first conductive region is induced Of the first conductivity type formed A first impurity region, and having at least one second impurity region of said second conductivity type second conductive region is formed adjacent to the region to be induced.

In the above invention, the first electrode is a floating electrode, and a predetermined voltage is applied to the second electrode to inject and discharge charges between the semiconductor substrate and the first electrode. Therefore, a predetermined potential is applied to the first electrode in advance by the injected charge, and the first conductive region can be formed in advance on the surface of the semiconductor substrate below the first electrode.
Therefore, a memory function can be provided depending on whether or not charge is injected into the first electrode, that is, whether or not the first conductive region is formed in advance. As a result, it is possible to realize a semiconductor device having a non-volatile memory function suitable for ultra-miniaturization and integration with uniform device characteristics without characteristic variations.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a first embodiment of a semiconductor device according to the present invention. A first gate electrode 13 and a second gate electrode 14 are formed on a p-type silicon substrate 11 with a gate oxide film 12 interposed therebetween. For example, polysilicon is used as a material for forming the gate electrodes 13 and 14.
Gate electrode 13 and gate electrode 14 are insulated by oxide film 15, and p ⁺⁺ drain 16 and n ⁺⁺ source 17 are formed on both sides of gate electrodes 13 and 14.

When a negative bias is applied to the gate electrode 13 and a positive bias is applied to the gate electrode 14, a hole accumulation layer 18 and an electron inversion layer 19 are formed on the surface of the silicon substrate 11, respectively. As a result, an Esaki diode is generated at the boundary between the hole accumulation layer 18 and the electron inversion layer 19, and a negative differential resistance appears in the electrical characteristics. On the other hand, when no voltage is applied to either of the gates, no Esaki diode is formed and the pn junction characteristics are normal. The current-voltage characteristics are the same as those of the surface junction tunnel element described in the section of the prior art, and have characteristics as shown in FIG.

A major feature is that the two regions constituting the Esaki diode are both electrically controlled by the gate electrode 13 and the gate electrode 14. Therefore, even if the impurity profile of the source / drain varies, it does not affect the tunnel characteristics at all. Therefore, a surface junction tunnel element having uniform element characteristics can be realized. Further, since the distribution of electrons and holes is very steep, advantages such as an increase in tunnel current and a reduction in parasitic capacitance can be obtained. It is very difficult to control such a steep profile by ion implantation.

As described above, different voltages may be applied to the gate electrode 13 and the gate electrode 14, but the gate electrode 13 may be a floating electrode. In this case, by applying a high positive voltage to the gate electrode 14 and injecting electrons from the silicon substrate 11 to the gate electrode 13, the hole accumulation layer 18 is formed on the surface of the silicon substrate 11. When a high negative voltage is applied to the gate electrode 14, electrons in the gate electrode 13 are emitted to the silicon substrate 11,
The hole accumulation layer 18 disappears. That is, depending on whether electrons are injected into the gate electrode 13 or not.
Even if a positive voltage is applied to the gate electrode 14, a negative differential resistance may or may not appear. By adding such a kind of memory function to the surface junction tunnel element, it is also possible to constitute a nonvolatile memory.

FIG. 2 shows a second embodiment of the semiconductor device according to the present invention. In the present embodiment, as shown in FIG.
The gate electrode 13 and the gate electrode 14 are processed two-dimensionally without overlapping. The specific element operation is the same as that of the first embodiment shown in FIG.

FIG. 3 shows a third embodiment of the semiconductor device according to the present invention. In the present embodiment, the shape of the gate electrode is different from the structure shown in FIG. 1, and the electric field concentration is reduced by processing the gate electrode 13 into a tapered shape. This structure is particularly effective when the electrical breakdown voltage of the oxide film 15 that insulates the gate electrode 13 and the gate electrode 14 is poor.

FIG. 4 shows a fourth embodiment of the semiconductor device according to the present invention. In the present embodiment, the planar shape of the gate electrodes 13 and 14 is comb-shaped. As a result, the effective tunnel area increases, and the tunnel current can be increased. The present embodiment is also characterized in that the tunnel region has no contact with the element isolation end 20. As a result, a leak current at the element isolation end 20 is eliminated, and good negative differential characteristics can be realized. Here, a comb shape is described as an example, but other shapes such as a spiral shape are also possible.

FIG. 5 is a cross-sectional view showing a manufacturing process for manufacturing the semiconductor device according to the first embodiment shown in FIG. First, an oxide film for element isolation (not shown) is formed on the surface of the p-type silicon substrate 11 using, for example, the LOCOS method. Subsequently, after forming the gate oxide film 12, for example, a polysilicon film 13 is formed in order to form a first gate electrode, and this is processed into a predetermined shape (FIG. 5).
(A)).

Next, after the surface of the polysilicon film 13 is oxidized to form an oxide film 15, a polysilicon film 14, for example, is formed to form a second gate electrode. Process. Subsequently, arsenic ions are implanted using the resist used for processing the polysilicon film 14 as a mask to form the source region 17 (FIG. 5B).

Next, the gate electrode 14 and the gate electrode 13 are continuously patterned using the resist 21 as a mask. Further, boron ions are implanted with the resist 21 left to form the drain region 16 (FIG. 5).
(C)). Finally, the resist 21 is removed, and a structure as shown in FIG. 1 is completed.

Normally, processing of the first gate electrode 13
Processing of the second gate electrode 14, formation of the source region 17, and formation of the drain region 16 require a total of four times of patterning. However, if the above-described manufacturing process is adopted, three times of patterning are required. Leads to reduced costs and costs.

The same concept as in the above manufacturing method can be applied to the conventional structure shown in FIG. In order to realize the structure of FIG. 10, usually, processing of a gate electrode, formation of a source region and formation of a drain region, and a total of three times of patterning are required. A manufacturing process in which this is simplified twice will be described with reference to FIG.

First, an oxide film for element isolation (not shown) is formed on the surface of the p-type silicon substrate 31 by using, for example, the LOCOS method. Subsequently, after forming the gate oxide film 32, for example, a polysilicon film 33 is formed to form a gate electrode, and this is processed into a predetermined shape. continue,
Arsenic ions are implanted using the resist 35 used for processing the polysilicon film 33 as a mask to form a source region 34 (FIG. 6A).

Next, after removing the resist 35, a resist 37 is formed, and the gate electrode 33 is processed and the drain region 36 is formed using the resist 37 as a mask (FIG. 6).
(B)). Finally, if the resist 37 is removed, an element as shown in FIG. 10 is completed by two patterning operations.

FIG. 7 is a cross-sectional view showing a manufacturing process for manufacturing the semiconductor device according to the second embodiment shown in FIG. First, an oxide film for element isolation (not shown) is formed on the surface of the p-type silicon substrate 11 using, for example, the LOCOS method. Subsequently, after forming the gate oxide film 12, for example, a polysilicon film 13 is formed to form a first gate electrode, and this is processed into a predetermined shape (FIG. 7).
(A)).

Next, after the surface of the polysilicon film 13 is oxidized to form an oxide film 15, for example, a polysilicon film 14 is formed to form a second gate electrode. Subsequently, anisotropic etching is performed to leave the gate electrode 14 only on the side wall of the polysilicon film 13. Thereafter, the source region 17 is formed by arsenic ion implantation using the gate electrode as a mask (FIG. 7B).

Next, the gate electrode 13 is patterned using the resist 21 as a mask. Further, the resist 21
Is implanted in a state where is left, thereby forming a drain region 16 (FIG. 7C). Finally, resist 2
1 is removed, and the structure as shown in FIG. 2 is completed.

FIG. 8 shows a fifth embodiment of the semiconductor device according to the present invention. FIG. 8A is an equivalent circuit diagram of FIG.
8B is a plan view, and FIG. 8C is a cross-sectional view. In the present embodiment, the structure is such that a plurality of surface junction tunnel elements are connected in series. As shown in FIG. 8, the bistable circuit is constituted by arranging the high power and V _dd to a low power supply V _ss. That is, when two surface junction tunnel elements are connected in series, a bistable circuit can be formed because two stable points a and b exist as shown in FIG. Hei 8-246697). In the negative differential resistance element, a functional circuit is assembled based on such a bistable circuit.

In this embodiment, as shown in FIG. 8C, an SOI substrate 54 in which a silicon element region 53 is formed on a silicon base substrate 51 via an oxide film 52 is used. In the example of FIG. 8, three Esaki diodes D1,
D2 and D3 are formed, but the forward bias
Only 1 and D3 form a bistable circuit. D
Since 2 is in reverse bias, it can be regarded as simply a resistor.

Looking at the single element alone, the structure of the present invention represented by FIG. 1 is larger than the conventional structure of FIG. 10, and there is a concern that the chip area may be increased. However, when a plurality of elements are arranged as in an LSI, as shown in FIG.
By using the device of the present invention, the source / drain regions can be omitted, and as a result, a compact layout can be realized. Therefore, there is no increase in the chip area as a concern, and the area can be reduced.

Although the embodiments have been described above, the present invention is not limited to these embodiments, and can be variously modified and implemented without departing from the gist of the invention.

[0033]

According to the present invention, since an Esaki diode is formed using a conductive region electrically induced on a semiconductor surface, processing variations do not affect tunnel characteristics. Therefore, a semiconductor device having uniform device characteristics and suitable for ultra-miniaturization and integration can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

FIG. 4 is a plan view showing a fourth embodiment of the present invention.

FIG. 5 is a view showing a manufacturing process according to the first embodiment of the present invention.

FIG. 6 is a view showing a manufacturing process when the same concept as the manufacturing method according to the first embodiment is applied to the conventional configuration shown in FIG. 10;

FIG. 7 is a view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a fifth embodiment of the present invention.

FIG. 9 is a diagram illustrating an operation principle when a bistable circuit is realized by a fifth embodiment.

FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a conventional technique.

FIG. 11 is a diagram showing current-voltage characteristics of a semiconductor device according to the present invention and a conventional technique.

[Explanation of symbols]

 Reference Signs List 11 silicon substrate (semiconductor substrate) 12 gate insulating film (first insulating film) 13 gate electrode (first electrode) 14 gate electrode (second electrode) 15 oxide film (second insulating film) 16: drain region (first impurity region) 17: source region (second impurity region) 18: storage layer (first conductive region) 19: inversion layer (second conductive region) 54: SOI substrate ( Semiconductor substrate)

Claims (2)

[Claims] 1. An insulating film formed on a semiconductor substrate, and at least one insulating film formed on the insulating film for inducing at least one first conductive region of a first conductivity type on a surface of the semiconductor substrate. A first electrode and at least one second conductive type second conductive type formed on the insulating film and adjacent to the at least one first conductive region on the surface of the semiconductor substrate;
At least one second electrode for inducing a conductive region of the first conductivity type, and a first impurity region of a first conductivity type formed adjacent to a region where at least one of the first conductive regions is induced; A semiconductor device comprising: a second impurity region of a second conductivity type formed adjacent to at least one region where the second conductive region is induced. 2. A first insulating film formed on a semiconductor substrate, and at least one first conductive region of a first conductivity type is induced on a surface of the semiconductor substrate formed on the first insulating film. At least one first electrode for performing
A second insulating film formed on the first electrode, a second insulating film formed on the first insulating film and the second insulating film, and adjacent to at least one first conductive region on a surface of the semiconductor substrate; To induce at least one second conductive region of the second conductivity type and to inject and discharge charges between the semiconductor substrate and at least one first electrode through the first insulating film. At least one second electrode, a first impurity region of a first conductivity type formed adjacent to a region where at least one first conductive region is induced, and at least one second impurity region. And a second impurity region of a second conductivity type formed adjacent to the region where the conductive region is induced.