JPH1153272A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To add a data error detection function about data to be transferred without deviating from a standard in a data transfer system that is configured, conforming a data transfer standard which does not define a data error detection function. SOLUTION: When a peripheral device 12 sends data to a host 11, the device 12 sends data in a 1st phase in which transfer is performed from the device 12 to the host 11. When the data is sent, a parity generating means 123 that is provided on the device 12 generates a horizontal parity code and holds it. The host 11 generates a horizontal parity code from received data and sends an error code that is generated to the device 12 after data receiving in the 1st phase is finished and shifted to a 2nd phase in which transfer is performed from the host 11 to the device 12. The device 12 which receives it compares the horizontal parity signal that is generated before sending the data with a horizontal parity code of data after sending which is received from the host 11 with a comparing means and performs code error detection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a host device (host) based on a specific standard (for example, IEEE 1284 standard).
Adds a code error detection function without making any changes to the data transfer method for transferring data between the device and peripheral devices, especially if the code error detection function is not defined in that particular standard Data transfer method.

[0002]

2. Description of the Related Art In a data transfer system between a host computer and a peripheral device, a system equipped with a system conforming to the IEEE1284 standard is widely used at the time of realizing bidirectional communication. However, IEEE 1284
The standard does not define an error detection method typified by parity check and CRC (cyclic coding), and has no function of detecting a code error. In general, an error detection method such as a parity check generates an error code for data to be transmitted on a transmission side, transmits data of a specific data format to which the code is added, receives the data on a reception side, and generates a parity check. The error is detected by an error detection circuit such as a check circuit. Further, as an example of a conventional data transfer method employing such an error detection method, there is a system described in JP-A-6-282501 for increasing the speed of data transfer from a host to a peripheral device. In this method, clock parity and the like are simultaneously burst-transferred together with data, and an error detection function is realized by a clock detection circuit and a parity error check circuit in a peripheral device.

[0003]

However, in the prior art, a data format corresponding to the error detection method and a data transfer path are required, but a data transfer method conforming to a standard having no error detection function is required. Since it does not correspond to such a data format and does not have a data transfer path therefor, an error detection function cannot be added. If an attempt is made to change the data format or expand the data transfer path in order to provide an error detection function, for example, the standard will be deviated from the standard to be adopted as in the prior art described in the above-mentioned publication. .

Accordingly, the present invention provides a data transfer system configured in accordance with a data transfer standard in which a data error detection function is not defined, without changing the data error detection function for transferred data without deviating from the standard. The task is to add it.

[0005]

According to the present invention (claim 1), the first device (12 in FIG. 1, 52 in FIG. 5, FIG. 8)
81, 82 in FIG. 11) to the second device (11, FIG. 1).
5, 51 of FIG. 5, 82 of FIG. 8, 81 of FIG. 11) (for example, a data transfer phase in the nibble mode, a data transfer phase in the byte mode,
ECP forward phase, ECP reverse phase)
And a second phase (for example, a termination phase, a compatible mode, an ECP reverse phase, and an ECP forward phase) in which data can be transmitted from the second device to the first device. Then, the first device includes first generation means (123 in FIG. 1, 523 in FIG. 5, and 812 in FIG. 8) for generating an error code (for example, a horizontal parity code) relating to data transmitted in the first phase. 824 in FIG. 11) and a comparing means (1 in FIG. 1) for comparing the error code generated by the first generating means with the error code received from the second device in the second phase.
24, 524 in FIG. 5, 813 in FIG. 8, and 825 in FIG. 11)
Are provided. Further, the second device includes second generating means (113 in FIG. 1, 513 in FIG. 5, 822 in FIG. 8, and 815 in FIG. 11) for generating an error code related to the data received in the first phase. The error code transmitting means (112 in FIG. 1, 512 in FIG. 5, 8 in FIG. 8) for transmitting the error code generated by the second generating means to the first device in the second phase.
23, 811) in FIG.

In the data transfer method including the above configuration, when data is transmitted from the first device to the second device, the first device transmits data in the first phase. When transmitting the data, an error code is generated and held by the first generation unit. The second device generates an error code, for example, a horizontal parity code, from the received data by the second generation means. After the reception of the data in the first phase is completed, and the state transitions to the second phase, the second device generates the error code. Transmits the error code generated by the second generation means to the first device by the error code transmission means. In the first device that has received the error code, the comparing unit compares the error code held in the first generating unit with the received error code. As a result of the comparison, if there is a mismatch, a code error has occurred in the data received by the second device, so that appropriate processing is performed. In one aspect of the present invention (claim 2), when the comparison result by the comparing means does not match, the first device notifies the second device that an error has been detected and responds to the error. Resend the data. This enables error correction.

Conventionally, when data is transmitted from a first device to a second device, an error check is performed by adding an error code to the transmission data and transmitting the data together with the data. The error detection is performed based on the error code by the check circuit provided in the device, but in the case of the device conforming to the data transfer standard without the error detection function, the error code is transmitted to the second device together with the data. It does not have a data format, a data path, and a time slot, and thus cannot add a function of performing error checking.
In contrast, according to the present invention, only data is transmitted from the first device to the second device in the first phase,
The error code is generated on the second device side, and is transmitted to the first device using a second phase that can be transferred from the second device to the first device. Since the configuration is such that the error check is performed on the side, the error detection function can be added while conforming to a specific communication standard for which the error detection function is not defined. Therefore, errors in transmission from the first device to the second device can be reduced,
Reliable data transfer can be performed.

[0008] In a specific aspect (claim 3) of the present invention, in the above invention (claims 1 and 2), the first device is a peripheral device and the second device is a host computer (hereinafter referred to as a host). ), Wherein the first phase is an operation state of transmitting data of the peripheral device to the host using the control line,
The second phase is characterized by an operation state in which host data can be transmitted to a peripheral device using a data line to which a transition is made after the first phase is completed. For example, IEEE1
For example, data transfer in the nibble mode of the H.284 standard corresponds to this mode, and the data transfer phase in the nibble mode corresponds to the first phase, and the forward transfer phase in the termination phase or the compatible mode corresponds to the second phase. . In this example, the data of the peripheral device is transferred to the host in the data transfer phase of the nibble mode, and after the completion of the data transfer phase, the mode returns to the compatible mode via the termination phase. Since the operation state is such that data can be transmitted to the device, the error code generated by the host can be transmitted to the peripheral device by using this. Therefore,
Even if the error code cannot be sent to the host in the data transfer phase in the nibble mode, the error code necessary for checking the code error in the termination phase or the forward transfer phase in the compatible mode can be input to the comparing means on the peripheral device side. As it becomes possible, IEEE1
An error detection function can be added without changing the transfer function conforming to the 284 standard.

According to the present invention (claim 3), the error code cannot be transferred together with the data in the first phase in which the data is transferred from the peripheral device to the host using the control line. Since the generated error code can be sent to the peripheral device, the error code of the data before transmission and the error code after transmission can be compared by the comparison circuit prepared in the peripheral device, and the error can be detected.
Therefore, errors in transmission from the peripheral device to the host can be reduced, and reliable data transfer can be performed.

According to the present invention (claim 4), in the invention (claims 1 and 2), the first device is a peripheral device and the second device is
Is a host computer, a first phase is an operation state of transmitting data of a peripheral device to the host computer using a bidirectional data line, and a second phase is a state in which the first phase transits after the completion of the first phase. The operation state is such that data of the host computer can be transmitted to the peripheral device using the data line. For example, IEEE
Data transfer in the byte mode or ECP mode of the 1284 standard corresponds to a specific example of this mode, and the data transfer phase or the ECP reverse transfer phase in the byte mode corresponds to the first phase, and the termination phase,
The compatible mode forward transfer phase or ECP forward transfer phase corresponds to the second phase. In this example, in the byte mode data transfer phase or the ECP reverse phase, the data of the peripheral device is transferred to the host, and after the byte mode data transfer phase is completed, the mode returns to the compatible mode via the termination phase. Transitions to the ECP forward transfer phase. Since the termination phase, compatible mode, and ECP forward transfer phase are operating states in which data can be transmitted from the host to the peripheral device via the bidirectional data line, use this to send an error code generated by the host to the peripheral device. Can be. Further, even if the error code cannot be sent to the host in the byte mode data transfer phase or the ECP reverse transfer phase, the exchange of the error code necessary for checking the code error in the termination phase, the compatible mode or the ECP forward transfer phase is performed. It is possible between the host and the peripheral device.

According to the present invention (claim 4), the error code cannot be transferred together with the data in the first phase in which the data is transferred from the peripheral device to the host using the data line. Since the generated error code can be sent to the peripheral device, the error code of the data before transmission and the error code after transmission can be compared by the comparison circuit prepared in the peripheral device, and the error can be detected. Accordingly, an error in transmission from the peripheral device to the host can be detected, and reliable data transfer can be performed.

According to the present invention (claim 5), in the above invention (claims 1 and 2), the first device is a host computer, the second device is a peripheral device, and the first phase is bidirectional. An operation state in which data of the host computer is transmitted to the peripheral device using the data line. In the second phase, data of the peripheral device is transmitted to the host computer using a bidirectional data line to which a transition is made after completion of the first phase. It is characterized by a possible operating state. For example, IEEE
The data transfer in the ECP mode of the 1284 standard corresponds to a specific example of this mode, the ECP forward transfer phase corresponds to a first phase, and the ECP reverse transfer phase corresponds to a second phase. In this example, the data of the host is transferred to the peripheral device in the ECP forward transfer phase, and after the completion of the data transfer phase, the host returns to the compatible mode via the termination phase or transits to the ECP reverse transfer phase. Since the termination phase and the ECP reverse transfer phase are operating states in which data can be transmitted from the peripheral device to the host via the bidirectional data line, the error code generated by the peripheral device can be transmitted to the host using this. Even if the error code cannot be sent to the host in the ECP forward transfer phase, the exchange of the error code necessary for checking the code error in the termination phase or the ECP reverse transfer phase becomes possible between the host and the peripheral device. According to the present invention (claim 5), the error code cannot be transferred together with the data in the first phase in which the data is transferred from the host to the peripheral device using the data line, but the error code is generated by the peripheral device in the second phase. Since the error code can be sent to the host, the error code of the data before transmission and the error code after transmission can be compared by the comparison circuit prepared in the host on the transmission side, and the error can be detected. Therefore, errors in transmission from the host to the peripheral device can be reduced, and reliable data transfer can be performed.

The present invention (Claim 6) is the invention according to the invention (Claims 1 and 2 and Claims 4 and 5), wherein the first device includes a second error code for data transmitted in the first phase. (For example, a vertical parity code) (525 in FIG. 5) and a control line (for example, IEEE 1) in which the generated second error code is not used in the first phase.
Xfla in 284 byte mode and ECP mode
g signal line 541), a means (522 in FIG. 5) for simultaneously transmitting data to the second device is added, and the second device is provided with a second error code from the data received from the first device. And a second error code generated by the fourth generation means and a second error code received via the control line to compare the error with the second error code generated by the fourth generation means. And a second comparing means (515 in FIG. 5) for detecting. According to the present invention (claim 6), the check using the first error code (for example, the horizontal parity check) and the check using the second error code (for example, the vertical parity check) can be used in combination, so that more data can be obtained. Transfer reliability can be improved.

[0014]

Embodiments of the present invention will be described below. FIG. 2 is for explaining an outline of transition of a communication mode for communication between a host and a peripheral device in the IEEE1284 standard. As shown in the figure, the communication mode includes a compatible mode (Compatibility mode).
y Mode), Nibble Mode (Nibble Mode)
e), byte mode (Byte Mode), ECP mode (Extended Capabilities)
Port Mode). The interface between the host and peripheral devices is initially in compatible mode. When performing a data transfer, when the host issues a request to a peripheral device in the compatible mode, a transfer mode that is possible for the peripheral device is selected in a negotiation phase, and a transition is made to the selected transfer mode. When the data transfer is completed in the transitioned transfer mode, the mode returns to the compatible mode via the termination phase. Data transfer from the host to the peripheral device is called forward data transfer, and data transfer from the peripheral device to the host is called reverse data transfer. The first embodiment is an example in which the error detection function according to the present invention is added to the reverse data transfer in the nibble mode.
Is an example in which the error detection function according to the present invention is added to the reverse transfer in the byte mode, and Embodiment 3 shows an example in which the error detection function according to the present invention is added to the reverse data transfer and the forward data transfer in the ECP mode. . Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0015]

First Embodiment In a first embodiment, the present invention is applied to a data transfer system conforming to a nibble mode, which is one of the transfer modes of IEEE1284. The nibble mode is an asynchronous reverse channel performed under the control of the host, that is, an operation state in which its own ID and status signal are transferred from the peripheral device to the host. In this mode, data bytes are transmitted as two sequences of four parallel bits each using four data lines (status lines) from the peripheral device to the host. The nibble mode standard does not provide a function for detecting a code error in the transmission.

FIG. 1 is a diagram schematically showing a data transfer system between the host 11 and the peripheral device 12. The host 11 and the peripheral device 12 are connected via a half-duplex bidirectional data bus or the host 11.
To the peripheral device 12 and to the unidirectional bus 13 via control lines 141 to 144 used for data transfer in the nibble mode. The host 11 includes a receiving unit 111 and a transmitting unit 11
2 and a parity generation circuit 113. The parity generation circuit 113 generates a time-series parity code (horizontal parity code) for each bit of the 8-bit data received by the reception unit 111 of the host 11 from the time of negotiation to the nibble mode to the time of termination to the compatible mode. It is. Transmission unit 112
Drives the time-series parity code generated by the parity generation circuit 113 to the data bus 13 not used at the termination phase, and
2 has a function of transmitting data.

The peripheral device 12 includes a transmitting unit 122 and a receiving unit 12
1, a parity generation circuit 123 and a parity comparison circuit 124. The parity generation circuit 123 has a function of generating and holding a time-series parity code of all data transmitted to the host in the nibble mode. Parity comparison circuit 1
A function 24 compares the time-sequence parity code received from the host 11 in the termination phase with the time-sequence parity code held in the parity generation circuit 123, and determines that a code error has occurred when they do not match. Have.

The transmission unit 122 converts the 8-bit data to IEEE
NData according to the definition of the nibble mode of the 1284 standard
Data bit 0 on the signal line of the signal named Avail
And 4, data bits 1 and 5 on a signal line of a signal named Xflag, data bits 2 and 6 on a signal line of a signal named AckDataReq, PtrBu.
The data bits 3 and 7 are transferred to the host machine 11 through a signal line of a signal named sy.

FIG. 3 shows the peripheral device 12 in the nibble mode.
FIG. 4 is a diagram showing a flow of an operation when data is transferred from a host to a host 11. FIG. 4 is a schematic flow chart showing a process of generating a parity code in a host 11, a parity check in a peripheral device 12, and a request for retransmission. Here, an example of the parity is an even parity, but it is not necessary to stick to the parity if the format is a predetermined format.

FIG. 4 is a detailed timing chart in which the host transmits a time series parity code of each bit to the peripheral device 2 when terminating from the nibble mode. Note that the event numbers and signal names in FIG.
It is the same as the standard of E1284. In the figure, TL is the response time (peripheral resp) of the peripheral device.
once time), TH is the response time of the host (Ho
st response time), T∞ is indefinite response time (infinite response time)
It is.

The operation of the first embodiment of the present invention will be described below in accordance with the IEEE1284 standard. The host 11 makes a transition from the compatible mode to the nibble mode through the negotiation phase in order to receive data (data relating to IDs and functions and status data) from the peripheral device 12. In response, the peripheral device 12 transmits data in the nibble mode. In the data transfer phase of the nibble mode, as shown in FIG. 4, each 8-bit data is transmitted through a control line (AckDataReq, Pt in the IEEE1284 standard).
rBusy, nDataAvail, lines of signals named XFlag) 141 to 144
It is transferred as two sequences of bits. When the data reception ends, the host returns to the convertible mode after the termination phase.

As shown in FIG. 3, the host 11 converts the data received in the nibble mode into a parity code of a time series parity code in real time for each bit.
(S31 in FIG. 3). The parity generation circuit 113 can be easily realized by an exclusive-OR circuit EXOR and a flip-flop circuit. The host 11 uses the generated parity code in the data line 13 not used in the termination phase of the nibble mode, that is, Data (8...) Shown in the third waveform from the top in FIG.
Drive to the data line of 1). The peripheral device 12 takes in the time-series parity code of the data line 13 at a predetermined timing of one of the event numbers 22, 25, and 28 in FIG. Comparison circuit 124
(S32 in FIG. 3). At that time, the peripheral device 12
When there is a difference in the comparison result, that is, when a time-series parity error occurs, the error is notified to the host 11 via a control line or the like such as immediately generating a busy signal (S33 in FIG. 3). Then, since the host 11 cannot transmit data when, for example, the busy signal is asserted, the host 11 transitions to one of the transmission modes to check the reason why the peripheral device 12 is asserting busy (S in FIG. 3).
34). Here, it is possible to retransmit the data transferred in the nibble mode.

In the nibble mode of the IEEE 1248 standard, when data is transmitted from the peripheral device to the host, a parity code for the transmitted data is transmitted together with the data in a format attached to the data from the peripheral device to the host,
There is no function that enables parity check on the host. Further, even if an attempt is made to extend the function of transferring a parity code to data for parity checking, the nibble mode standard has no available channels or control lines. On the other hand, when data transmission in nibble mode is completed and transition to compatible mode is performed after the termination phase, there is a free data channel in both the termination phase and the compatible mode that can transfer data from the host to the peripheral device. I do. In the first embodiment, in order to add a code error check function without changing the IEEE 1248 standard, a parity code of transmission data is generated on the host side, and a termination phase and a usable data channel in a compatible mode are determined in advance. At the same time, it is sent to the peripheral device, and the parity check is performed in the peripheral device.

As described above, in the first embodiment, the IEEE
Without changing the 1284 standard, a parity code of data after transmission necessary for parity check is sent to a peripheral device which is a transmission source, so that a peripheral device side can check a code error of transfer data in a nibble mode. Therefore, the reliability of data transferred from the peripheral device to the host in the nibble mode can be improved.

[0025]

Embodiment 2 In Embodiment 2, the present invention is applied to a data transfer system conforming to a byte mode, which is one of the transfer modes of IEEE1284. Byte mode is
This is an operation mode in which communication is performed asynchronously from a peripheral device to a host in a byte width using eight data lines for data and control / status lines.

FIG. 5 is a diagram schematically showing a data transfer system between the host 51 and the peripheral device 52. The host 51 and the peripheral device 52 are connected by a bidirectional data path 53 or unidirectional control signal lines 541 to 543. The host 51 includes a horizontal parity generation circuit 513 that generates a horizontal parity code of received data, that is, a time-sequence parity code for each bit of the received data, in addition to the reception unit 511 and the transmission unit 512. A vertical parity generation circuit 514 that generates a vertical parity code of the data obtained, that is, a parity code for each byte, and a vertical parity generation circuit 525 of the peripheral device and a vertical parity code generated by the vertical parity generation circuit 514 and transmitted. A vertical parity comparison circuit 515 that compares the vertical parity codes received by the reception unit 511 of the host 51 is provided.

The peripheral device 52 includes a reception unit 521 having a reception buffer for holding a horizontal parity code transmitted from the host 51, a transmission unit 522 for transmitting transmission data and a vertical parity code, and a horizontal parity code for transmission data. And a horizontal parity comparison circuit 524 that compares and generates a horizontal parity code.
And a vertical parity generation circuit 525 for generating a vertical parity code for 8-bit data.

FIG. 6 shows the transfer of the data and the vertical parity code generated by the peripheral device 52 from the peripheral device 52 to the host 51 in the byte mode, and the vertical parity comparison circuit 515 of the host 51 checks and compares the vertical parity code. FIG. 7 is a schematic flow chart until a retransmission request is made when the result does not match. Here, an example of the vertical parity check is an even parity check, but an odd parity check may be used.

FIG. 7 shows a case where data is transferred from the peripheral device 52 to the host 51 in the byte mode, a horizontal parity code is generated by the horizontal parity generation circuit 513 of the host 51, and the horizontal parity code is generated by the parity comparison circuit 524 of the peripheral device 52. FIG. 7 is a schematic flow chart showing a process up to checking for a retransmission request.
Here, an example of the horizontal parity check is an even parity check, but an odd parity check may be used.

The operation of the second embodiment will be described below in accordance with the IEEE 1284 standard. The host 51 transitions from the compatible mode to the byte mode through the negotiation phase in order to receive data (data, status, etc.) from the peripheral device 52. The peripheral device 52 transmits data in the byte mode in response. Here, the peripheral device 52
Generates a vertical parity of data transmitted in the byte mode by the vertical parity generation circuit 525 (S61 in FIG. 6).
The vertical parity generation circuit 525 can be easily realized by an exclusive-OR circuit (EXOR) and a flip-flop. The vertical parity code generated by the peripheral device 52 is transmitted to the host 51 via a signal line 541 named Xflag. The vertical parity generation circuit 514 generates a vertical parity of the received data. Vertical parity and parity generation circuit 5 received from peripheral device 52
The vertical parity generated in 14 is compared by the vertical parity comparison circuit 515 in the host 51 (S62 in FIG. 6). When there is a difference in the comparison result, that is, when a parity error in the vertical direction occurs, the host 51 immediately generates a signal and requests the peripheral device 52 to retransmit data via the signal line 542 named nini. Peripheral device 52
Receives the data transfer request and retransmits the data via the data bus 53 (S63 in FIG. 6). Then, when the data reception is completed, the host 51 returns to the compatible mode via the termination phase.

In the second embodiment, a horizontal parity check is also performed in addition to a vertical parity tick. FIG. 7 shows a processing flow when a horizontal parity check is performed.
The host 51 converts the horizontal parity code for each bit of the data received in the byte mode into a horizontal parity generation circuit 513.
(S71 in FIG. 7). Note that the horizontal parity generation circuit 513 can be easily realized by an EXOR and a flip-flop.

The host 51 drives (holds) this horizontal parity code to the data bus 53 which is not used in the termination phase. The peripheral device 52 compares the data transmitted by itself with the horizontal parity code in the horizontal parity comparison circuit 524 (S72 in FIG. 7). At this time, when there is a difference in the comparison result, that is, when a horizontal parity error occurs, the peripheral device 52 notifies the host 51 of the error through the control line 543 or the like such as immediately generating a busy signal (S73 in FIG. 7). ). And the host 51
For example, if the Vichy signal is asserted, data cannot be transmitted, so that the device transitions to one of the transmission modes to check the reason why the peripheral device is asserting Vichy (S74 in FIG. 7). Here, the data transferred in the byte mode can be retransmitted.

In the byte mode of the IEEE 1248 standard, when data is transmitted from the peripheral device to the host, a parity code for the transmitted data is attached to the data and transferred together from the peripheral device to the host. Function to enable parity check is not provided. Also, even if an attempt is made to extend the function of transferring a horizontal parity code to data for parity checking, the byte mode standard does not support data that adds a parity code to data. There are no available free channels or control lines. On the other hand, when data transmission in the byte mode is completed and transition to the compatible mode is performed after the termination phase, there is an empty data channel in both the termination phase and the compatible mode that can transfer data from the host to the peripheral device. I do. In the second embodiment, in order to add a code error checking function without changing the IEEE 1248 standard, a horizontal parity code of transmission data is generated on the host side, and an available data channel in the termination phase and the compatible mode is used. By transmitting to a peripheral device at a predetermined timing position, the peripheral device can perform a horizontal parity check. As for the vertical parity, the control line Xflag in the byte mode can be used. Therefore,
In the second embodiment, in the byte mode, the function can be extended so that a vertical parity code is generated by a peripheral device and sent to the host, and the host performs a vertical parity check. As described above, according to the second embodiment, 1EE128
The reliability of data transfer from the peripheral device to the host in the byte mode can be improved without departing from the 4 standards. Further, by using the vertical parity check and the horizontal parity check together, the reliability of data transfer can be further improved.

[0034]

Third Embodiment In the first embodiment, the present invention is applied to data transfer in the ECP mode, which is one of the transfer modes of IEEE1284. In the ECP mode, as schematically shown in a part of FIG. 2, a transition is made from the negotiation phase to the forward phase, and data transfer from the host to the peripheral device is performed. Transition from the forward phase to the reverse transfer is performed, and data transfer from the peripheral device to the host is performed.
After the transfer of each of these data is completed, the mode transits to the forward phase, and then returns to the compatible mode via the termination phase.

FIG. 8 is a schematic diagram of a data transfer system from the host 81 to the peripheral device 82 during the ECP mode forward phase. The host 81 and the peripheral device 82 are half-duplex bidirectional data. Connected by a tabus 83 and a control line 84. The host 81 includes a transmission unit 811 having a transmission buffer.
And peripheral devices 82 in the ECP mode forward phase.
Generates a time-series parity code for all data transmitted to
A parity generation circuit 812 to be held, a time-series parity code transmitted from the peripheral device 82 in a reverse phase or a termination phase, and the parity generation circuit 81
2, a parity comparison circuit 813 for comparing the time-series parity codes held in the peripheral device 8 and a peripheral device 8 having a reception buffer.
Receiving section 8 having a function of receiving a signal sent from
14 is provided. If the comparison result of the time-sequence parity code by the parity comparison circuit 813 differs even by one bit, the host 81 transits to the ECP mode forward phase again, notifies the peripheral device of retransmission, and notifies the corresponding device of the error. Has a function of retransmitting data, whereby data having a code error can be corrected.

The peripheral device 82 receives a signal transmitted from the host 81 via the data bus 83.
21 and the 8-bit data received by the receiving unit 821 from the negotiation to the ECP mode and the transition to the forward phase to the termination to the reverse phase or the compatible mode. Parity generating circuit 822 for generating a time-series parity code for each bit of the data
And a transmission unit 823 that transmits a signal to the host 81.

FIGS. 9 and 10 show data from the host 81 to the peripheral device 82 in the ECP mode forward phase.
FIG. 7 is a schematic flow chart showing a process of transferring data, generating a parity code in a peripheral device 82, a parity check in a host 81, a retransmission notification, and retransmission. Here, an example of the parity check is an even parity, but it is not necessary to stick to the parity if the format is a predetermined format.

FIG. 11 shows an ECP mode of IEEE1284.
Peripheral device 82 to host 81 during de-river phase
FIG. 2 is a schematic diagram of a data transfer system to the system. The same elements as those in FIG. 8 are denoted by the same reference numerals. The host 81 and the peripheral device 82 are connected to a half-duplex bidirectional data bus 83 and a control line 8.
4 are connected. The host 81 has a receiving unit 814 having a receiving buffer, and the receiving unit 814 of the host 81 which has negotiated the ECP mode and transits to the reverse phase until transits to the forward phase.
A parity generation circuit 815 that generates a time-series parity code for each bit of the bit data, and data that is not used when the time-series parity code generated by the parity generation circuit 815 transits to the forward phase. And a transmitting unit 811 having a function of driving to the peripheral line and transmitting to the peripheral device 82.

The peripheral device 82 has a transmission unit 823 having a transmission buffer, and a parity generation circuit 824 for generating and holding a time-series parity code of all data transmitted to the host 81 in the ECP mode reverse phase. A parity comparison circuit 825 for comparing a time-sequence parity code received from the host 81 in the forward phase with the time-sequence parity code held in the parity generation circuit 824; and a reception for receiving a parity code from the host 81. 821. If the comparison result of the time-sequence parity code is different even by one bit, the peripheral device 82 asserts an unused signal to the host 81 and notifies the host 81 that the error detection result has an error. And has a function of retransmitting the error. As a result, data errors can be corrected.

FIG. 12 shows that data is transferred from the peripheral device 82 to the host 81 in the ECP mode reverse phase.
FIG. 7 is a schematic flow chart showing parity generation in a host 81, parity check in a peripheral device 82, retransmission notification, and retransmission. Here, an example of the parity check is an even parity, but it is not necessary to stick to the parity if the format is a predetermined format.

FIGS. 13 and 14 are detailed timing charts in which the host or the peripheral device transmits the time series parity of each bit to the peripheral device or the host when terminating from the ECP mode. It is. Note that FIG.
The event number and signal name in FIG.
It is the same as the standard. Also, in FIG.
Is a response period of the peripheral device, and TH is a response period of the host.

Hereinafter, the IEEE 12 standard will be described with reference to the drawings described above.
The operation flow of the third embodiment will be described according to the 84 standard.

(Detection and Correction of Code Error in ECP Mode Forward Phase)
In order to transmit information (data and status) to the EPC mode, a transition is made from the compatible mode to the ECP mode forward phase through the negotiation phase. Host 8
No. 1 responds to this and transmits data in the ECP mode forward phase. When the data transmission is completed, the host 81
When information (data, status) is to be received from the peripheral device 82, the ECP mode is switched from the ECP mode forward phase to the ECP mode via the forward-to-reverse phase. The state transits to the reverse phase, and otherwise returns to the compatible mode through the termination phase. E
An error in the CP mode forward phase is made when the state transits to the ECP mode reverse phase or the termination phase. Here, the peripheral device 82 is EC
The data received in the P mode forward phase is generated by a parity generation circuit 822 in real time for each bit and a time series parity code is generated and held (S9 in FIG. 9).
1). Note that this parity generation circuit 822 can be easily realized by an EXOR and a flip-flop.

First, as shown in FIG. 9, the ECP mode
At the time of transition from the forward phase to the ECP mode reverse phase, the peripheral device 82 uses the parity code generated and held by the parity generation circuit 822 in the forward-to-reverse phase. Data not done
Drive to taline 83. The host 81 fetches the time-series parity code of the data line 83 at the timing of the event 40 (FIG. 14), and the time-series parity code and the parity comparison circuit 81 for the data transmitted by itself.
3 (S92 in FIG. 9). At that time, the host 81
When there is a difference in the comparison result, that is, when a time-series parity error occurs, the peripheral device 82 is notified of retransmission by an unused line (HostClk: L) (S9 in FIG. 9).
At the same time as 3), the state transits again to the ECP mode forward phase (nReverseRequest: H) (S94 to 95 in FIG. 9) and the data is retransmitted (S9 in FIG. 9).
6).

Next, at the time of transition from the ECP mode forward phase to the termination phase, the peripheral device 82 (holds) the parity code which is not used in the termination phase. -Drive to taline 83. The host 81 receives this at the receiving unit 814, and fetches a time-sequence parity code of the data line 83 at a predetermined timing, for example, any of the events 23, 24, and 27. The parity code of the stream is compared with the parity code of the stream (FIG. 1).
0 of S102). At this time, when there is a difference in the comparison result, that is, when a time-series parity error occurs, the host 81 transitions from the compatible mode to the ECP mode forward phase again (S104 in FIG. 10).
105), the peripheral device 82 is notified of retransmission by an unused line (nCmd) (S106 in FIG. 10), and retransmits the data corresponding to the error bit in byte units (S106 in FIG. 10).

(Detection and Correction of Code Error in ECP Mode Reverse Phase) In the data transfer system in the ECP mode reverse phase in FIG. 10, the host 81 sends information (data, status) from the peripheral device 82. From the compatible mode to the ECP mode reverse phase through the negotiation phase in order to receive.
In response to this, the peripheral device 82 transmits data in the ECP mode reverse phase. When the data transmission is completed, the host 81 sends information (data status) to the peripheral device 82.
If it is desired to transmit an ECP mode, a transition is made from the ECP mode reverse phase to the ECP mode forward phase via the reverse to forward phase, and otherwise, it is compatible via the termination phase. Return to mode.
Error detection in ECP mode reverse phase is ECP
This is performed when the state transitions to the mode forward phase.

Here, the host 81 generates a time-series parity code in real time by the parity generation circuit 815 (S121 in FIG. 12). The parity generation circuit 8
15 can be easily realized by EXOR and Philip flop.

First, when a transition is made from the ECP mode reverse phase to the ECP mode forward phase, the host 81 reverses (holds) this parity code.
Data not used in the tour-to-forward phase
Drive to taline 83. The peripheral device 82 fetches the time-series parity code of the data line 83 at the timing of the event 49 (see FIG. 14) and compares the time-series parity code of the data transmitted by itself with the parity comparison circuit 8.
A comparison is made at 25 (S122 in FIG. 12). At this time, when there is a difference in the comparison result, that is, when a time-sequence parity error occurs, the peripheral device 82 notifies the host 81 of retransmission via an unused line (periphClk: L) (S123 in FIG. 12). Host 81 uses nReverseR
By changing the request signal (FIG. 14) to L (S124 in FIG. 12), transition to the ECP mode reverse phase is again made (S125 in FIG. 12), and the data corresponding to the error bit is retransmitted in byte units (FIG. 12). S126).

As described above, according to the third embodiment, from the host to the peripheral device in the ECP mode forward phase or the peripheral device in the ECP mode reverse phase without changing the IEEE1284 standard. The reliability of data transferred from the device to the host can be improved. Although the vertical parity check has not been described, the vertical parity check can be added in the third embodiment as well as the vertical parity check in the byte mode in FIG.

It should be noted that the present invention is based on the above-described embodiments.
Although an example in which the present invention is applied to a data transfer method conforming to the EE1284 standard has been described, the present invention is generally applicable to a case where the data transfer method which does not define an error detection function is extended to add an error detection function. Applicable.

[0051]

According to the present invention (claim 1), only data is transmitted from the first device to the second device in the first phase, and the error code is generated on the second device side. The second phase from the second apparatus to the first apparatus is transmitted to the first apparatus, and the first apparatus performs an error check. Even when a transfer method must be constructed in accordance with a specific communication standard for which no definition has been made, it is possible to add an error detection function while complying with the communication standard. Therefore, errors in transmission from the first device to the second device can be reduced, and reliable data transfer can be performed.

According to the present invention (claim 2), when the result of the comparison by the comparing means does not match in the above invention (claim 1), an error is sent from the first device to the second device. Since the detection is notified and the data corresponding to the error is retransmitted, transmission errors can be reduced, and reliable data transfer can be performed.

According to the present invention (claim 3), the first method for transferring data from a peripheral device to a host using a control line is provided.
In this phase, the error code cannot be transferred together with the data, but the error code can be generated from the transfer data on the host side and the generated error code can be sent to the peripheral device in the second phase. The error code of the data before transmission and the error code after transmission can be compared by the comparison circuit prepared in (1), and the error can be detected.
Therefore, errors in transmission from the peripheral device to the host can be reduced, and reliable data transfer can be performed.

According to the present invention (claim 4), the error code cannot be transferred together with the data in the first phase in which the data is transferred from the peripheral device to the host using the data line. In the second phase, the generated error code can be sent to the peripheral device in the second phase, so that the error code of the data before transmission and the error code after transmission are The codes can be compared, and errors can be detected. Therefore, errors in transmission from the peripheral device to the host can be reduced, and reliable data transfer can be performed.

According to the present invention (claim 5), the error code cannot be transferred together with the data in the first phase in which the data is transferred from the host to the peripheral device using the data line. In the phase, the error code generated by the peripheral device can be sent to the host, so that the error code of the data before transmission and the error code after transmission can be compared by the comparison circuit prepared in the host on the transmission side, and the error Detection becomes possible. Therefore, errors in transmission from the host to the peripheral device can be reduced, and reliable data transfer can be performed.

According to the present invention (claim 6), the first
(For example, a horizontal parity check) and a check for a second error code (for example, a vertical parity check) can be used together, and the reliability of data transfer can be further improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a data transfer system of a host and peripheral devices according to a first embodiment.

FIG. 2 is a diagram for explaining transition of a communication mode in the IEEE1284 standard;

FIG. 3 is an operation flowchart of the first embodiment.

FIG. 4 is a detailed timing chart for returning from a nibble mode to a compatible mode via a termination.

FIG. 5 is a schematic diagram of a data transfer system between a peripheral device 1 and a host 2;

FIG. 6 is a schematic flowchart of a vertical parity check.

FIG. 7 is a schematic flowchart of a horizontal parity check.

FIG. 8 is a schematic diagram of a data transfer system from a host to a peripheral device.

Fig. 9: EC from ECP mode forward phase
FIG. 13 is a schematic flowchart of a third embodiment when a transition is made to a P-mode reverse phase.

FIG. 10: Start from ECP mode forward phase
FIG. 13 is a schematic flowchart of a third embodiment when returning to the compatible mode via mining.

FIG. 11 is a schematic diagram of a data transfer system from a peripheral device to a host.

FIG. 12: ECP from the ECP mode reverse phase
FIG. 4 is a schematic flowchart of an embodiment when a transition is made to a mode forward phase.

FIG. 13 is a detailed timing chart for returning from ECP mode to compatible mode via termination.

FIG. 14: From ECP mode forward phase to E
Detailed timing chart for transition to the CP mode reverse phase.

[Explanation of symbols]

11, 51, 81: host computer (host), 1
11, 511, 814... Receiving unit, 112, 512, 81
1 ... transmitting unit, 113,812 ... parity generation circuit, 51
Reference numeral 3 denotes a horizontal parity generation circuit, reference numeral 514 denotes a vertical parity generation circuit, reference numeral 515 denotes a vertical parity comparison circuit, and reference numeral 813 denotes a parity comparison circuit. 12, 52, 82 ... peripheral devices (eg, printer), 121, 521, 821 ... receiving units, 122, 52
2,823: a transmission unit; 123, 824: a parity generation circuit; 523, a horizontal parity generation circuit; 124, a parity comparison circuit; 524, a horizontal parity comparison circuit; 525, a vertical parity generation circuit; 1
3, 53, 83: data bus (bidirectional or unidirectional); 124: parity comparison circuit.

Claims (6)

[Claims] 1. A data transfer method including a first phase in which data can be transmitted from a first device to a second device and a second phase in which data can be transmitted from the second device to the first device, A first generating means for generating an error code relating to data transmitted in the first phase, and an error code generated by the first generating means and a second
A second generating means for generating an error code relating to data received in the first phase, a second generating means for generating an error code for data received in the first phase; The error code generated by the means is transferred to the second phase in the first phase.
A data transfer method characterized by adding error code transmitting means for transmitting to an apparatus. 2. The method according to claim 1, wherein when the comparison results in no match, the first device notifies the second device that an error has been detected and retransmits data corresponding to the error. The data transfer method according to claim 1, wherein 3. The first device is a peripheral device, the second device is a host computer, and the first phase is an operation state of transmitting data of the peripheral device to the host computer using a control line, 2. The data transfer method according to claim 1, wherein the second phase is an operation state in which data of the host computer can be transmitted to the peripheral device using a data line to which a transition is made after the end of the first phase. 4. The first device is a peripheral device, the second device is a host computer, and the first phase is an operation state in which data of the peripheral device is transmitted to the host computer using a bidirectional data line. 2. The data transfer according to claim 1, wherein the second phase is an operation state in which data of the host computer can be transmitted to the peripheral device using a bidirectional data line to which a transition is made after completion of the first phase. method. 5. The first device is a host computer,
The second device is a peripheral device, the first phase is an operation state of transmitting data of the host computer to the peripheral device using the bidirectional data line, and the second phase transits after the first phase ends. 2. The data transfer system according to claim 1, wherein the data transfer system is in an operation state in which data of a peripheral device can be transmitted to a host computer using a bidirectional data line. 6. A first apparatus comprising: third generating means for generating a second error code relating to data transmitted in a first phase; and using the generated second error code in a first phase. Means for simultaneously transmitting data to the second device through a control line not provided, and a fourth generating means for generating a second error code from data received from the first device in the second device. And a second comparing means for comparing the second error code generated by the fourth generating means with the second error code received via the control line and detecting an error. The data transfer method according to any one of claims 1 to 2, and claims 4 to 5.