JPH11509667A - Sense amplifier with automatic offset invalidation - Google Patents

Abstract

(57) Abstract: A sense amplifier for determining a state of a memory cell of a random access memory includes first and second transistors connected in the form of a differential amplifier. The first and second transistors have their control electrodes connected to the "bit" and "bit B" lines, respectively, for sensing the state of the memory cell. The sense amplifier further includes third and fourth transistors connected in the form of a differential amplifier. The differential amplifier configuration has an offset error and provides a differential output indicating the state of the memory cell in the read phase. The sense amplifier further includes first and second capacitors connected between the control electrodes of the third and fourth transistors and a reference potential, respectively, and a "bit" line and a "bit B" line that are not being read. A feedback circuit for connecting a voltage representing an offset error in the first phase to the first and second capacitors. The first and third transistors are connected in series or in parallel. Similarly, the second and fourth transistors are connected in series or in parallel. By nullifying the offset error, the RAM access time is reduced.

Description

Description: FIELD OF THE INVENTION The present invention relates to a sense amplifier for a random access memory, and more particularly to a sense amplifier for canceling an offset error using a feedback technique. Related to amplifiers. BACKGROUND OF THE INVENTION A typical random access memory (RAM) includes a row and column array of memory cells. A row of memory cells is accessed by activating a word line. The memory cells in each column are connected to the sense amplifier by "bit" lines and inverted bit ("bit B") lines. During a memory read access, a sense amplifier determines the state of a memory cell having an active word line. The memory includes a sense amplifier for each memory cell along a word line. In another form, two or more sets of "bit" and "bit B" lines are multiplexed to the sense amplifier. One of the main parameters of the RAM is its access time. The access time to the memory cell is the time to activate the word line, the time to transfer the signal from the memory cell to the "bit" and "bit B" lines, and the "bit" and "bit B""Is the sum of several components including the time to detect the line. In a typical 4 megabit 100 MHz RAM, the voltage change on the active "bit" line is typically about 100 millivolts, with potentials on the "bit" and "bit B" lines at a rate of about 30 millivolts / nanosecond. Occurs. Thus, producing 100 millivolts on the "bit" and "bit B" lines requires about 3 nanoseconds, representing 30% of the access time. Sense amplifiers are typically configured as differential amplifiers with offset errors on the order of 10-20 millivolts. The access time is increased for one of the states of the memory cell because the potential on the "bit" line must overcome this offset error in order to switch the sense amplifier. The remainder of the access time is accounted for by row decoder and word line activation, both typically through the use of low resistance interconnect metal strapping and / or by chip segmentation. Reduced. A high-speed DRAM in which the bit lines are pre-charged to half the supply voltage for faster detection is a P.D. Gillingham et al., "IEEE Journal of Solid State Circuit", August 1991, Vol. 26, Part 8, pages 1171-1175. The form of DRAM in which the offset of the sense amplifier is stored in the bit line is described in T.K. Sugibayashi et al., "ISSCC95 Digest of Technical Papers", Feb. 17, 1995, pages 254 and 255. SUMMARY OF THE INVENTION According to the present invention, there is provided a sense amplifier for determining the state of a memory cell of a random access memory. The memory cell has a "bit" line and a "bit B" line connected thereto. The sense amplifier includes first and second transistors connected in the form of a differential amplifier. The first and second transistors have control electrodes connected to the "bit" and "bit B" lines, respectively, for sensing the state of the memory cell. The sense amplifier further includes third and fourth transistors connected in a differential amplifier configuration. The differential amplifier configuration has first and second differential outputs having an offset error and indicating the state of the memory cell in the read phase. The sense amplifier further includes first and second capacitors connected between the control electrodes of the third and fourth transistors, respectively, in a nullification phase where the "bit" and "bit B" lines are not being read. A feedback circuit for connecting a voltage representing an offset error to the first and second capacitors, and a bias circuit for biasing the first, second, third and fourth transistors to operate in a read phase and a nullification phase And In the first and second embodiments, the third transistor is connected in series with the first transistor in a cascode configuration, and the fourth transistor is connected in series with the second transistor in a cascode configuration. The positions of the first and third transistors are interchangeable, and the positions of the second and fourth transistors are interchangeable in cascode form. In the third embodiment, the third transistor is connected in parallel with the first transistor, and the fourth transistor is connected in parallel with the second transistor. The feedback circuit is connected between a first differential output and a gate of a third transistor, and between a fifth differential transistor and a gate of the fourth transistor. And a control circuit for turning on the fifth and sixth transistors in the invalidation phase and turning off the fifth and sixth transistors in the readout phase. The sense amplifier further includes a bit line equalization circuit connected to the "bit" and "bit B" lines to precharge the "bit" and "bit B" lines to an equal voltage in the pre-charge phase. Is desirable. Preferably, the invalidation phase and the pre-charge phase are simultaneous. Peak current is reduced, if necessary, by disabling each sense amplifier or group of sense amplifiers in the RAM to be distributed at different times. BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention, reference is made to the accompanying drawings, which are incorporated herein by reference. FIG. 1 is a schematic diagram of a random access memory suitable for incorporating the sense amplifier of the present invention, FIG. 2 is a schematic diagram of a first embodiment of a sense amplifier according to the present invention, and FIG. FIG. 4 is a schematic diagram of a second embodiment of the sense amplifier of the present invention, and FIG. 5 is a schematic diagram of a third embodiment of the sense amplifier of the present invention. It is. An example partial block diagram of a random access memory (RAM) 10 is shown in schematically Figure 1 suitable for incorporation of the detailed description the invention. Memory cells 14, 16, 18, 20, etc. are arranged in an array of rows and columns. A typical RAM contains a large number of memory cells. The memory cells in each row are connected to a word line. Thus, for example, memory cells 14 and 16 are connected to word line 24, and memory cells 18 and 20 are connected to word line 26. A row decoder 30 activates one of the word lines during a read or a write. The memory cells in each column are connected to a "bit" line and an inverted bit (bit B) line. Thus, for example, the memory cells 14, 18 are connected to a “bit” line 32 and a “bit B” line 34. Bit line 32 and “bit B” line 34 are connected to sense amplifier 40. The sense amplifier senses the potential on the "bit" and "bit B" lines and provides an output indicative of the state of the memory cell having the active word line. Thus, for example, when word line 24 is active, sense amplifier 40 provides an output representative of the state of memory cell 14. In another form, two or more sets of bit lines are multiplexed into a sense amplifier under the control of a column decoder. It is understood that the random access memory has a variety of different forms. The present invention is applicable to a RAM having a "bit" line and a "bit B" line connected to a memory cell for sensing the state of the memory cell. The invention is particularly applicable to static random access memories (SRAMs). A schematic diagram of a first embodiment of the sense amplifier according to the present invention is shown in FIG. A "bit" line 50 and a "bit B" line 52 are selectively connected to memory cells 54 in the memory cell array. “Bit” line 50 is connected to the gate of transistor 56 and “bit B” line 52 is connected to the gate of transistor 58. The sources of transistors 56 and 58 are connected to node 60 in the form of a differential amplifier. This node 60 is grounded via a bias transistor 62. The drain of transistor 56 is connected in cascode to the source of transistor 66. The drain of transistor 58 is connected in cascode to the source of transistor 68. The drain of transistor 66 is connected to power supply voltage VDD via bias transistor 70. The drain of transistor 68 is connected to power supply voltage VDD via bias transistor 72. The transistors 56, 58, 62, 66, 68, 70 and 72 constitute a differential amplifier. The differential outputs OUTB and OUT of this amplifier appear at the drains of transistors 66 and 68, respectively. The differential outputs OUT and OUTB are typically connected to a second stage 74 of a sense amplifier that provides the required load drive capability. Transistors 62, 70 and 72 form a bias circuit that biases transistors 56, 58, 66 and 68 of the differential amplifier during operation. In the embodiment of FIG. 2, transistors 56, 58, 62, 66 and 68 are N-type MOS transistors, and transistors 70 and 72 are P-type MOS transistors. As is well known in the art, differential amplifiers have offset errors due to process variations, aging, temperature variations, and the like. By compensating for aging, field reliability is improved. Typical offset errors are on the order of 10-20 millivolts. In the context of a sense amplifier for a RAM, offset errors manifest themselves as threshold deviations. That is, the threshold voltage for detecting the state “1” of the memory cell is different from the threshold voltage for detecting the state “0” of the memory cell. This offset error results in different access times for the 1 and 0 states of the memory cell, because the threshold level of the differential amplifier is reached at different times according to the state of the memory cell. According to the present invention, the sense amplifier includes a circuit that automatically nullifies the offset error. Capacitor 80 is connected between the gate of transistor 66 and a reference potential such as ground. Capacitor 82 is connected between the gate of transistor 68 and a reference potential such as ground. Transistor 84 has a source connected to the drain of transistor 66, and a drain connected to the gate of transistor 66 and capacitor 80. Transistor 86 has a source connected to the drain of transistor 68, and a drain connected to the gate of transistor 68 and capacitor 82. Transistors 84 and 86 are electronically controlled to connect each differential output of the sense amplifier to capacitors 80 and 82 in a nulling phase of operation when memory cell 54 is not being read. Function as a switch. The transistors 84 and 86 are P-type MOS transistors. As described below, transistors 84 and 86 and capacitors 80 and 82, in conjunction with cascode transistors 66 and 68, provide nulling of offset errors in the sense amplifier. Preferably, the sense amplifier includes a bit line equalization circuit 90 connected to a "bit" line 50 and a "bit B" line 52. Transistor 92 is connected between precharge voltage VP and “bit” line 50. Transistor 94 is connected between precharge voltage VP and “bit B” line 52. Transistor 96 is connected between “bit” line 50 and “bit B” line 52. Transistors 92, 94 and 96 may be P-type MOS transistors, each of which receives an inverted enable (ENB) control signal that is active during the precharge operating phase. When the control signal is active, transistors 92, 94 and 96 are turned on. In the precharge phase, "bit" line 50 and "bit B" line 52 are connected to precharge voltage VP and are interconnected. In a preferred embodiment, the pre-charge voltage VP is half the power supply voltage VDD. Thus, for example, when the power supply voltage V _DD is 5.0 volts, the pre-charge voltage VP is 2.5 volts. A typical timing signal for the operation of the sense amplifier of FIG. 2 is shown in FIG. The ENB control signal is applied to the gates of the transistors 84 and 86 in the offset error nullification circuit and the gates of the transistors 92 and 94 in the bit line equalization circuit 90. This ENB control signal is generated by a control circuit 98 that controls the operation of the RAM. When the ENB signal is low, the word line connected to memory cell 54 is disabled, inhibiting reading of the memory cell. When the ENB signal is low, the transistors 92, 94, 96 of the bit line equalization circuit are switched on, precharging the "bit" line 50 and the "bit B" line 52 to the precharge voltage VP. Further, transistors 84 and 86 are turned on when the ENB signal is low. Transistor 84 applies the voltage at the drain of transistor 66 to capacitor 80, and transistor 86 applies the voltage at the drain of transistor 68 to capacitor 82. Since the inputs to the sense amplifier on "bit" line 50 and "bit B" line 52 are equivalent due to the activation of bit line equalization circuit 90, the differential outputs OUT and OUT B at the drains of transistors 68 and 66 are sensed. Represents the offset error of the amplifier. This differential output is connected by transistors 84 and 86 to capacitors 80 and 82 and the gates of transistors 66 and 68, respectively. A feedback device nullifies the offset error. In particular, if the offset error causes the output voltage to be higher than its nominal value, this higher voltage will be applied to the gate of transistor 68, causing another current to flow through transistor 68 and reducing the output voltage to its nominal value. Occurs. Conversely, if the output voltage is lower than its nominal value, this lower voltage is applied to the gate of transistor 68, causing a decrease in the current flowing through transistor 68 and an increase in the output voltage to its nominal value. The nulling circuit, including transistors 66 and 84 and capacitor 80, operates in a similar manner. When the ENB control signal is deactivated to a high state during the reading of the memory cell, transistors 84 and 86 are turned off and the required feedback voltage is stored on capacitors 80 and 82. The voltage stored on capacitors 80, 82 is applied to the gates of transistors 66, 68 during reading of memory cell 54, thereby substantially nullifying the offset error. As shown in FIG. 3, the word line connected to memory cell 54 is in an active high state during times when it does not overlap with the EN B control signal. In the read operation phase in which the word line is active, the capacitors 80, 82 remain at the appropriate voltage to counteract offset errors and the transistors 84, 86 remain off. The pre-charging of the "bit" line 50 and the "bit B" line 52 and the nullification of the offset error occur simultaneously during the active state of the ENB control signal in the embodiment of FIGS. As an example, the precharge and invalidate operations can be repeated at 4 millisecond intervals. It will be appreciated that different spacings may be used depending on the value of the capacitors 80, 82 and the accuracy of the desired offset error nullification. Peak current is reduced, if necessary, by disabling each sense amplifier or group of sense amplifiers in the RAM into a distributed state at different times. The capacitance values of the capacitors 80, 82 are selected to keep the threshold adjustment within desired accuracy after leakage. A 1 millivolt difference between capacitors 80 and 82 is considered reasonable if the droop at both is 200 millivolts. This accuracy can be changed by changing the ratio of transistors 66, 68 to transistors 56, 58. The minimum value of the capacitance should be at least as large as the gate-to-drain overlap capacitance of transistors 84,86. The common mode rejection of the sense amplifier provides insensitivity to capacitor voltage decay. The maximum value of the capacitance is limited by area constraints and should be chosen so that the capacitors fit within the pitch of the bit line pairs of the memory. A practical range for the capacitance value is about 0.1 to 1.0 picofarads. However, other capacitance values can be used within the scope of the present invention. Larger capacitors require less frequent refreshing, thus reducing power. However, larger capacitors require more chip area and require more time to charge. In the case of the sense amplifier shown in FIG. 2, the power supply voltage VDD is 5.0 volts, and the bias voltage applied to the gates of the transistors 70 and 72 is 0 volts. The sense amplifier is enabled by applying a 5 volt inverted power down (PDB) signal to the gate of transistor 62. Different bias circuit configurations can be used within the scope of the present invention. For example, transistors 70 and 72 can be replaced with a current mirror circuit. The transistors 70 and 72 can be controlled by a PDB signal. Preferably, "bit" line 50 and "bit B" line 52 are precharged to an equal voltage of 2.5 volts. Different precharge voltages can be used within the common mode range of the sense amplifier. In the disable and precharge operating phases, the voltage at node 60 is typically on the order of 1.0 volt, and the voltages at outputs OUT and OUTB are on the order of 3.0 to 3.5 volts. In the read operation phase, memory cell 54 causes "bit" line 50 and "bit B" line 52 to differ by about 100 millivolts. The difference voltage applied to the transistors 56 and 58 changes the differential outputs OUT and OUTB in proportion to the gain of the differential amplifier. As previously mentioned, the offset error voltage stored on capacitors 80 and 82 causes the sense amplifier to have a substantially equal threshold for any state of memory cell 54. FIG. 4 shows a second embodiment of the sense amplifier of the present invention. Similar elements in FIGS. 2 and 4 have the same reference numbers. Memory cell 54, bit line equalization circuit 90, control circuit 98, and second stage 74 have been omitted from FIG. 4 for simplicity of illustration. The circuit of FIG. 4 differs from the circuit of FIG. 2 in that the positions of transistors 56 and 66 are interchanged and the positions of transistors 58 and 68 are interchanged. Thus, the differential outputs OUT and OUTB of the sense amplifier appear at the drains of transistors 58 and 56, respectively. The drain of transistor 66 is connected to the source of transistor 56, and the drain of transistor 68 is connected to the source of transistor 58. The sources of the transistors 66 and 68 are connected to the node 60. The source of transistor 84 is connected to the drain of transistor 56, which constitutes differential output OUTB. The source of transistor 86 is connected to the drain of transistor 58, which constitutes differential output OUT. The operation of the sense amplifier of FIG. 4 is substantially the same as the operation of the sense amplifier shown in FIG. 2 and described above. The offset error of the differential amplifier is nullified by the combination of transistors 66, 68, 84, 86 and capacitors 80, 82. The embodiment of FIG. 4 causes a slightly higher precharge voltage VP (see FIG. 2) to be applied to the "bit" line 50 and the "bit B" line 52. A third embodiment of the sense amplifier of the present invention is shown in FIG. Similar elements in FIGS. 2 and 5 have the same reference numbers. The memory cell 54, bit line equalization circuit 90, control circuit 98 and second stage 74 have been omitted from FIG. 5 for simplicity of illustration. The sense amplifier of FIG. 5 differs from the sense amplifier of FIG. 2 in that transistors 56 and 66 are connected in parallel and transistors 58 and 68 are connected in parallel. Further, the drains of transistors 56 and 66 are connected together to form a differential output OUTB. The sources of the transistors 57 and 66 are connected to the node 60. The drains of the transistors 58, 58 are connected together to form a differential output OUT. The sources of the transistors 58 and 68 are connected to the node 60. The transistor 84 is connected between the differential output OUTB and the gate of the transistor 66, and the transistor 86 is connected between the differential output OUT and the gate of the transistor 68. The third embodiment has a higher gain at the expense of different layout constraints, which means that the sense amplifier can be a single bit line pair (or group if multiplexed) for efficient area utilization. It is advantageous if it is necessary to match the spacing between them. The operation of the sense amplifier of FIG. 5 is substantially the same as the operation of the sense amplifier shown in FIG. 2 and described above. In the sense amplifier of FIG. 5, the total current in each leg of the differential amplifier is divided between the transistors connected in parallel. In each of the sense amplifiers shown and described above, the differential output of the sense amplifier is controlled in part by the bit line voltage and in part by the offset error of the differential amplifier. Since the offset error is nullified, the access time of the memory cell is reduced. The offset nullification according to the present invention allows longer bit lines, thereby reducing the word line distribution for a given memory size. This reduces the activation time of the word line, thereby further reducing the access time. In addition, for embedded applications that must be pitch-matched to other circuit blocks to make efficient use of the silicon area, a different memory aspect ratio defined as the number of columns divided by the number of rows can be used. . The sense amplifier of the present invention has been described with reference to a CMOS configuration. It will be appreciated that the techniques of offset error nullification described herein are applicable to other techniques such as, for example, BICMOS and bipolar technologies. While what has been described and described as presently preferred embodiments of the present invention, those skilled in the art will recognize that various changes and modifications can be made without departing from the scope of the present invention as defined by the appended claims. It will be obvious.

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Claims (1)

[Claims] 1. Sense amplifier for determining state of memory cell of random access memory A "bit" line and a "bit B" line to which said memory cell is connected. And a sense amplifier having   It is connected in the form of a differential amplifier and uses the "bit" to detect the state of the memory cell. And a control electrode connected to the "bit" line and the "bit B" line, respectively. A second transistor;   A differential output that has an offset error and indicates the state of the memory cell during the read phase. A third and a third each having a control electrode connected in the form of a differential amplifier for applying force. Four transistors,   Each of the third and fourth transistors is connected between a control electrode and a reference potential. First and second capacitors,   In the invalidation phase in which the “bit” line and the “bit B” line have not been read. Connecting a voltage representing the offset error to the first and second capacitors A feedback circuit to   The first, second, third and third operations with respect to operation during the read phase and the invalidation phase. And a bias circuit for applying a bias to the transistor No. 4 A sense amplifier comprising: 2. The feedback circuit includes one of the differential outputs and the first capacitor. A fifth transistor connected between the second differential output and the second A sixth transistor connected between the third transistor and the capacitor; Fifth and sixth transistors are switched on, and in the read phase the And a control circuit for switching off the fifth and sixth transistors. Amplifier. 3. The third transistor is cascoded in series with the first transistor; And the fourth transistor is connected in series with the second transistor. 2. The sense amplifier according to claim 1, wherein the sense amplifier is connected in a scode configuration. 4. The third transistor is connected in parallel with the first transistor; 2. The method according to claim 1, wherein a fourth transistor is connected in parallel with the second transistor. Sense amplifier. 5. Equal voltages on the "bit" and "bit B" lines during the precharge phase Bit line connected to the "bit" line and the "bit B" line for pre-charging 2. The sense amplifier according to claim 1, further comprising an equalizing circuit. 6. 6. The sense amplifier according to claim 5, wherein the invalidation phase and the precharge phase are simultaneous. Breadboard. 7. Sense amplifier for determining state of memory cell of random access memory Wherein the memory cell has a "bit" line connected thereto and a "bit B" The sense amplifier having a "   The gate is a "bit" line and a "bit B" to detect the state of the memory cell. First and second transformers, each connected to a respective line and connected in the form of a differential amplifier. With the Jista,   First and second differential outputs indicating the state of a memory cell in a read phase Each having a drain and a gate connected in the form of the differential amplifier having Third and fourth transistors,   Connected between the gates of the third and fourth transistors and a reference potential, respectively First and second capacitors,   In the invalidation phase in which the “bit” line and the “bit B” line have not been read. The first and second differential outputs are connected to gates of the third and fourth transistors. Feedback circuits connected to the   For operations during the read phase and the invalidation phase, the first, second, A bias circuit for imposing a bias on the third and fourth transistors; A sense amplifier comprising: 8. The feedback circuit includes a first differential output and a third transistor. A fifth transistor connected between the second differential output and the second differential output; A sixth transistor connected between the fourth transistor and the gate of the fourth transistor; Turning on the fifth and sixth transistors in an enable phase and And a control circuit for switching off said fifth and sixth transistors during the phase. The sense amplifier according to claim 7, wherein 9. Equal voltages on the "bit" and "bit B" lines during the precharge phase , The bit connected to the "bit" line and the "bit B" line The sense amplifier according to claim 7, further comprising a line equalization circuit. 10. The sense according to claim 9, wherein the invalidation phase and the precharge phase are simultaneous. amplifier. 11. The first and second capacitors are connected to the third and fourth transistors 8. The sense amplifier according to claim 7, wherein said sense amplifier is connected between a gate of said first transistor and ground. 12. Sense amplification to determine the state of memory cells in random access memory Device, wherein said memory cell is connected to a "bit" line and a "bit" line. In the sense amplifier having a "B" line,   Connected in the form of a differential amplifier to detect the state of the memory cell. A first and a second having gates respectively connected to the "bit" line and the "bit B" line. And a second transistor;   The first and second transistors are connected in series, respectively, A drain and a gate, the drain being the state of the memory cell in the read phase. And fourth transistors constituting the first and second differential outputs When,   Connected between the gates of the third and fourth transistors and a reference potential, respectively First and second capacitors,   In an invalidation phase where the "bit" and "bit B" lines are not being read , The first and second differential outputs are connected to gates of the third and fourth transistors. A feedback circuit connected to the   For operations during the read phase and the invalidation phase, the first, second, third and And a bias circuit for imposing a bias on the fourth transistor; A sense amplifier comprising: 13. The feedback circuit includes a first differential output and a third transistor. A fifth transistor connected between the second differential output and A sixth transistor connected between the fourth transistor and a gate of the fourth transistor; Turning off the fifth and sixth transistors in the invalidation phase and A control circuit for switching off the fifth and sixth transistors in the output phase. 13. The sense amplifier of claim 12, comprising: 14． Sense amplification to determine the state of memory cells in random access memory Wherein the memory cell has a "bit" line and a "bit B" line connected to it. In the sense amplifier,   Connected in the form of differential amplifiers, each having a drain and a gate, The gate is connected to the "bit" line and the "bit" to detect the state of the memory cell. B "line and the drain is the state of the memory cell in the read phase. The first and second transistors constituting the first and second differential outputs And   The first and second transistors are connected in series with each other, and each is connected to a gate. Third and fourth transistors having gates;   A third transistor connected between the gates of the third and fourth transistors and a reference potential; A first and a second capacitor;   In an invalidation phase where the "bit" and "bit B" lines are not being read , The first and second differential outputs are connected to gates of the third and fourth transistors. And a feedback circuit respectively connected to   The first and the second are operated so as to operate in the readout phase and the invalidation phase. , A bias circuit for applying a bias to the third and fourth transistors, and A sense amplifier comprising: 15. The feedback circuit includes a first differential output and a third transistor. A fifth transistor connected between the second differential output and A sixth transistor connected between the fourth transistor and a gate of the fourth transistor; Turning off the fifth and sixth transistors in the invalidation phase and A control circuit for switching off the fifth and sixth transistors in the output phase. The sense amplifier of claim 14, comprising: 16. Sense amplification to determine the state of memory cells in random access memory The memory cell is connected to a "bit" line and a "bit B" " In the sense amplifier having a line,   Connected in the form of differential amplifiers, each having a drain and a gate, The gate is connected to the "bit" line and the "bit" to detect the state of the memory cell. A first and second transistor respectively connected to the "B" line;   The transistors are connected in parallel with the first and second transistors, respectively. A drain and a gate of the first and third transistors, wherein a drain of the first and third transistors is a first differential And the drains of the second and fourth transistors constitute a second differential output. Wherein the first and second differential outputs are the states of the memory cells in a read phase. Third and fourth transistors that display   A third transistor connected between the gates of the third and fourth transistors and a reference potential; A first and a second capacitor;   In an invalidation phase where the "bit" and "bit B" lines are not being read , The first and second differential outputs are connected to gates of the third and fourth transistors. And a feedback circuit respectively connected to   For operations during the read phase and the invalidation phase, the first, second, third and And a bias circuit for imposing a bias on the fourth transistor; A sense amplifier comprising: 17． The feedback circuit includes a first differential output and a third transistor. A fifth transistor connected between the second differential output and A sixth transistor connected between the fourth transistor and a gate of the fourth transistor; Turning off the fifth and sixth transistors in the invalidation phase and A control circuit for switching off the fifth and sixth transistors in the output phase. 17. The sense amplifier of claim 16, including: