JPH1146138A - Device for charging and discharging current - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate with voltage that is higher than the withstand pressure of a single transistor and also to improve an output constant current characteristic by serially connecting each transistor between a power source and a ground potential and specifying each gate voltage. SOLUTION: In a charge pump circuit of a PLL, an output transistor is a cascode structure and also respectively selects gate voltage of each transistor. That is, plural MOS transistors 1 and 2, and 3 and 4 are cascaded between a power supply terminal and an output terminal and between the output terminal and a ground terminal respectively. Bias voltages which bring the transistors 1 and 4 into a saturation state are applied to the gates of respective 1st transistors 1 and 4, and also, voltage of a voltage level which brings the transistors 2 and 3 into a saturation state or non-conductive state is switched and applied to the gates of 2nd transistors 2 and 3 in accordance with the on/off of a pulse. Thus, a PLL circuit having high performance which acquires constant current in a wide range is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for charging and discharging a current, and more particularly, to a device for charging and discharging a PLL (Ph).
The present invention relates to a charge pump circuit for stably charging and discharging current in a pulsed manner, which is used in an ase-looked loop circuit.

[0002]

2. Description of the Related Art An example of a conventional charge pump circuit is shown in FIG. 5 (Sogo Denshi Publishing Co., Ltd .: "Practical Technology for PLL Frequency Synthesizer II, Chapter 4, How to Use PLL LSI" 4.2.
Phase Comparator / Charge Pump Circuit ", pp. 83-84). The charge pump circuit is constituted by a single-stage FET. The source of the P-chFET 44 is connected to the power supply terminal, the drain is connected to the output terminal 43, and the gate is connected to the input terminal 4
1 connected. The N-chFET 45 has a source connected to the ground terminal, a drain connected to the output terminal 43, and a gate connected to the input terminal 42. This circuit is a circuit in which signals .PHI.P and .PHI.R input from a phase comparator in a PLL frequency synthesizer are input from input terminals 41 and 42, respectively, and current flows from an output terminal 43 based on the values.

FIG. 2 shows the principle of operation. The phase comparator detects rising edges of the reference signal fr and the comparison signal fp, and outputs a pulse proportional to the phase difference. That is, when the comparison signal fp is delayed (fr> fp), the phase difference pulse .PHI.P is output to the terminal 41, whereby the P-chFET of the charge pump circuit is turned on, current flows out from the terminal 43, and the output terminal The control voltage of the VCO (voltage control transmitter) connected to the subsequent stage is increased. Also, the comparison signal fp
Is advanced (fr <fp), the phase difference pulse ΦR
Is output to the terminal 42, and the N-chF
ET is turned on, current flows from the output terminal 43,
The control voltage of the VCO is decreased.

Here, ideally, the P-chFE
It is necessary for the T and N-ch FETs to output a constant current over a wide range of the voltage at the output terminal 43. In this conventional example, all of the operation characteristics depend on the characteristics of a single transistor. However, with the recent reduction in the level of microfabrication of integrated circuits, the breakdown voltage of transistors tends to decrease.
Since the operating voltage such as CO is still high, the external VC
The charge pump circuit that drives O needs to operate at a voltage higher than the withstand voltage of the transistor alone.

Therefore, as a method of increasing the withstand voltage between the source and the drain of the transistor, a method of connecting the transistor to a cascode (cascade connection) and dividing the voltage applied between each source and drain to improve the withstand voltage has been considered. I have. As a cascode-connected transistor, there is, for example, a transistor described in Japanese Patent Application Laid-Open No. 62-290204 shown in FIG. This cascode-connects one transistor 61 and the other transistor 62,
The gate terminals of the two transistors are commonly connected to a terminal 63, and the drain of the one transistor is used as a current output signal terminal 64.

However, since the purpose of this circuit is not to improve the breakdown voltage but to improve the characteristics when applied to an operational amplifier, such a structure is used as it is in the PLL of the present invention. When used in a charge pump circuit, the withstand voltage is improved, but the constant current characteristics of the output are not improved. In addition, since each Vth is added by cascode connection, and each transistor does not become saturated, when used alone, There is a problem that the voltage range for operating at a constant current becomes narrower than that of the conventional method.

[0007]

As described above, the conventional circuit cannot cope with the reduction in the withstand voltage of the transistor due to the recent microfabrication of the integrated circuit, and the improvement of the constant current output characteristics cannot be expected. In view of the above situation, it is an object of the present invention to cascode output transistors so that they can operate at a voltage higher than the withstand voltage of a single transistor, and to improve output constant current characteristics. It is.

[0008]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a PLL
In the charge pump circuit of the above, the output transistor has a cascode structure, so that it can operate at a voltage higher than the withstand voltage of a single transistor, and by appropriately selecting the gate voltage of each transistor, a wide range of output terminal voltages can be obtained. An output current characteristic capable of outputting a constant current can be obtained.

According to a first aspect of the present invention, a plurality of MOS transistors are connected in cascade between a power supply terminal and an output terminal, and between the output terminal and a ground terminal, wherein the plurality of MOS transistors are at least one of a first transistor and a second transistor. A bias voltage that causes the transistor to saturate is applied to the gate of the first transistor, and the transistor is set to a saturated state or non-conductive to the gate of the second transistor. The voltage of the voltage level is switched and applied according to the ON / OFF of the pulse.

According to a second aspect of the present invention, in the first aspect, the plurality of MOS transistors cascaded between the power supply terminal and the output terminal are first and second P-ch transistors.
A plurality of P-chFETs each comprising
A bias voltage for saturating the P-chFET is applied to the gate of the second P-chFET.
An FET is connected to the output terminal, and its gate terminal is switched and connected to a first bias power supply terminal or the power supply terminal by a first switch, and is cascaded between the output terminal and the ground terminal. The MOS transistor includes a plurality of N-channel FETs including first and second N-ch FETs.
a bias voltage for applying saturation to the gate of the first N-chFET is applied to the gate of the first N-chFET; the second N-chFET is connected to the output terminal; The second switch is connected to the second bias power supply terminal or the ground terminal by switching.

According to a third aspect of the present invention, a plurality of MOS transistors and a switch that is turned on / off in response to an applied pulse are cascaded between the power terminal and the output terminal, and between the output terminal and the ground terminal, respectively. A voltage level that causes each of the transistors to be in a saturated state is applied to the gate of the MOS transistor.

According to a fourth aspect of the present invention, in the third aspect, the plurality of MOS transistors cascade-connected between the power supply terminal and the output terminal are P-chFETs,
The plurality of MOS transistors cascade-connected between the output terminal and the ground terminal are N-chFETs.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a first embodiment of the present invention, and shows an example of a cascode connection of two-stage transistors. P-chFET
1, 2 are connected in series between the power supply terminal and the output terminal 13, the drain of the P-ch FET 2 is connected to the output terminal, and the gate terminal is connected to the bias voltage input terminal 6 through the switch 9. It has become. The switch 10 is a switch that is turned on when the switch 9 is turned off, that is, a switch that performs an inversion operation with the switch 9 and is connected to a power supply terminal. On the other hand, the gate of the transistor 1 is connected to the bias voltage terminal 5.

The N-chFETs 3 and 4 are connected in series between the connection terminal and the output terminal 13, the drain of the N-chFET 3 is connected to the output terminal 13, and the gate terminal of the N-chFET 3 is connected to the bias voltage input terminal 7 through the switch 11. Is to be connected to. The switch 12 is the switch 1
A switch that is turned on when 1 is off, ie, switch 11
And a switch that performs an inversion operation and is connected to a ground terminal. The gate of the transistor 4 is connected to the bias voltage terminal 8.

In this state, the signal .PHI.P from the phase comparison circuit is connected to the control signal terminal of the switch 9, the inverted signal thereof is connected to the control signal input terminal of the switch 10, and the signal .PHI.
R is connected to the control signal terminal of the switch 11, and the inverted signal is connected to the control signal input terminal of the switch 12. On the other hand, an appropriate bias voltage is applied to each of the bias voltage input terminals 5, 6, 7, and 8, and a constant current is applied to the output terminal 13.
Output.

Next, the principle of operation of the first embodiment of the present invention will be described with reference to FIG. When the present charge pump circuit is actually applied to a PLL, a phase comparison circuit is connected at the preceding stage, and FIG. 7 shows a connection example in a conventional configuration for reference. The phase comparator outputs the reference signal fr
And a rising edge of the comparison signal fp, and outputs a pulse proportional to the phase difference. That is, when the comparison signal fp is delayed (fr
> Fp), the phase difference pulse φP is output, whereby the switch 9 of the charge pump circuit is turned on and the switch 10 is turned off. At this time, since ΦR is an L output, the switch 11 is turned off and the switch 12 is turned on, and the gate voltage of the transistor 3 becomes H.
It turns off. On the other hand, a bias voltage is applied to the gates of the transistors 1 and 2, and a constant current flows out of the output terminal 13.
The control voltage of O can be increased.

When the comparison signal fp is advanced (f
At r <fp), the phase comparison circuit outputs a phase difference pulse ΦR, whereby the switch 11 of the charge pump circuit is turned on and the switch 12 is turned off. At this time, ΦP
Is an H output, the switch 9 is turned off and the switch 10 is turned on. Therefore, the gate voltage of the transistor 2 becomes H, and the transistor 2 is turned off. On the other hand, since the bias voltages are respectively connected to the gates of the transistors 3 and 4 as described above, a constant current can flow from the output terminal 13 and the control voltage of the VCO can be lowered.

As an example of a bias voltage circuit for obtaining a constant current characteristic over a wide range of output voltages, there is an improved cascode constant current source circuit (“Analog integrated circuit design technology for ultra LSI (bottom) Baifukan, 12 MOS amplifier) Design, Basic Element Circuit of 12.2 MOS Analog IC "2
Pages 86-288). FIG. 3 shows an embodiment in which the bias circuit is applied to the first embodiment of the present invention. In the figure, the transistor M1 corresponds to the transistor 4 in FIG. 1, and the transistor M2 corresponds to the transistor 3 in FIG. In this embodiment, a source follower M5 for shifting the voltage level is inserted in series with the gate of the transistor M2 so that the drain of the transistor M1 is more positive than the gate by a threshold voltage,
1 is biased to operate just at the end of the saturation characteristic, and as shown in FIG. 3B, a constant current operation is performed at a voltage of 2 V or more, and a voltage range in which the constant current operation is performed is wider than that of a single transistor. .

As described above, according to the present invention, the gate voltage of each of the transistors connected in series can be applied independently, so that the output current characteristics can be easily improved, which is very effective.

FIG. 4 shows a second embodiment of the present invention, and shows an example of a cascode connection of two-stage transistors. In FIG. 4, P-chFET1
Reference numerals 4 and 15 are connected in series between the power supply terminal and the intermediate output terminal 24, and the switch 22 is inserted between the intermediate output terminal 24 and the output terminal 26. The gates of the transistors 14 and 15 are connected to the bias voltage input terminals 18 and 19, respectively. The N-ch FETs 16 and 17 are connected in series between the ground terminal and the intermediate output terminal 25,
A switch 23 is provided between the intermediate output terminal 25 and the output terminal 26.
Is inserted.

The principle of operation of this circuit is as shown in FIG. 2, and its operation is the same as that of the first embodiment. That is,
The phase comparator detects rising edges of the reference signal fr and the comparison signal fp, and outputs a pulse proportional to the phase difference. When the comparison signal fp is delayed (fr> fp), a phase difference pulse φP is output, and the switch 22 of the charge pump circuit is turned on. At this time, ΦR is an L output,
The switch 23 is turned off. On the other hand, transistors 14,
Since an appropriate bias voltage is connected to each of the 15 gates, a constant current flows out of the output terminal 26, and the control voltage of the VCO connected to the subsequent stage of the output terminal can be increased. When the comparison signal fp is advanced (fr <fp), the phase difference pulse ΦR is output, and the switch 23 of the charge pump circuit is turned on. At this time, Φ
P is an H output, and the switch 22 is turned off. On the other hand,
Since an appropriate bias voltage is connected to the gates of the transistors 16 and 17 as described above, a current can flow from the output terminal 26 and the control voltage of the VCO can be reduced. Each Pch, N-chFET, that is, each transistor is connected in series between the output terminal and the power supply terminal or the ground terminal, so that it can be operated at a higher voltage than a single transistor.

In the second embodiment, the number of switches to be inserted can be reduced as compared with the first embodiment. In the first embodiment, the voltage applied to the gate of the transistor at the output terminal is controlled. In the second embodiment, the control is performed by inserting a switch between the output terminal and the bias voltage while always applying the bias voltage.

[0023]

As described above, according to the first and second aspects of the present invention, since each transistor is connected in series between the power supply and the ground potential, operation at a voltage higher than the withstand voltage of a single transistor. In addition, since the gate electrodes of the respective transistors connected in series are configured to be individually applied, the constant current output characteristics can be improved by applying each gate voltage to an appropriate value, and a wider range can be obtained. Thus, a high-performance PLL circuit that can obtain a constant current output can be realized. According to the third and fourth aspects of the present invention, in addition to having the same effects as those of the first and second aspects of the present invention, a bias voltage is always applied to the gate of each transistor. There is no possibility that the bias voltage fluctuates according to the switching of the above, and a more stable operation of the device can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a signal diagram for explaining the operation principle of the present invention and the prior art.

FIG. 3 is a diagram showing an example of a cascode constant current source circuit using the present invention.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional charge pump circuit.

FIG. 6 is a diagram showing a conventional example of cascode connection.

FIG. 7 is a diagram showing a conventional example of a circuit in which a phase comparator is connected to a charge pump circuit.

[Description of Signs] 1, 2, 14, 15 ... P-chFET, 3, 4, 16,
17: N-chFET, 13, 26: output terminal, Cox
... Gate oxide film pressure, Iref ... Reference current source, L ... Gate length, Vt ... Threshold voltage of transistor, W ... Gate width, μ
... channel mobility.

Claims (4)

[Claims] A plurality of MOS transistors are connected in cascade between a power supply terminal and an output terminal, and between the output terminal and a ground terminal, and the plurality of MOS transistors include at least one first transistor and a second transistor. A bias voltage for saturating the transistor is applied to the gate of the first transistor, and a voltage of a voltage level for saturating or non-conducting the transistor is applied to the gate of the second transistor. A device for charging / discharging a current, which is switched and applied according to on / off of a pulse. 2. The plurality of MOS transistors cascaded between the power supply terminal and the output terminal include first and second MOS transistors.
P-chFETs comprising a plurality of P-chFETs,
A bias voltage for saturating the transistor is applied to the gate of the first P-chFET, the second P-chFET is connected to the output terminal, and the gate terminal is connected to the first switch by a first switch. A MOS switch connected to a first bias power supply terminal or the power supply terminal and cascaded between the output terminal and the ground terminal;
The transistor is a plurality of N-chFETs including a first and a second N-chFET, wherein the first N-chFET is
A bias voltage that causes the transistor to saturate is applied to the gate of the transistor, the second N-chFET is connected to the output terminal, and the gate terminal of the second N-chFET is connected to a second bias power supply terminal or The device for charging and discharging a current according to claim 1, wherein the device is switched and connected to the ground terminal. 3. A power supply terminal, an output terminal, and a plurality of MOS transistors and a switch that is turned on / off in response to an applied pulse are cascaded between the output terminal and the ground terminal, and connected to gates of the plurality of MOS transistors. A device for charging / discharging a current, wherein a voltage level that brings each of the transistors into a saturated state is applied. 4. The plurality of MOS transistors cascaded between the power supply terminal and the output terminal are P-ch FEs.
4. The apparatus according to claim 3, wherein the plurality of MOS transistors are T-connected, and the plurality of MOS transistors cascaded between the output terminal and the ground terminal are N-chFETs.