JPH1145585A - Content-addressable memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to decrease the number of coincidence detection operation times and to reduce the electric power consumption by carrying out a coincidence detection operation only when a change is induced in the result of the previous retrieval by a change in a retrieval bit pattern. SOLUTION: At the time of the coincidence detection operation, a power source VDD potential is outputted through transistors(TRs) M15, M25 to M55 for coincidence detection to a coincidence detection signal line 14A in the case of all the coincidence of the bit patterns stored in memory cells 111 to 115 and the bit patterns of the retrieval data inputted through bit lines 231 to 235 and bit bars 261 to 265. A coincidence detection signal CS is supplied to a coincidence detection signal output circuit 13. At the time of a noncoincidence detection operation, the coincidence detection signal line 14A is grounded through the TRs corresponding to the noncoincidence among the TRs M16, M26 to M56 and a noncoincidence signal CS is supplied to a coincidence detection signal output circuit 13 in the case of the noncoincidence of either of the bit patterns stored in memory cells 111 to 115 and the bit patterns of the retrieval data inputted through the bit lines 231 to 235 and the bit bars 261 to 265.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a content addressable memory circuit, and more particularly to a content addressable memory circuit having a search function for searching for word data by matching stored word data with a bit pattern of input search data. About.

[0002]

2. Description of the Related Art This type of content addressable memory circuit (C
Ontet Addressable Memory (hereinafter referred to as a CAM circuit) is also called an associative memory circuit, and search data is input to a large number of word memory cells, and a match / mismatch between a bit pattern of the search data and data stored in the word memory cell is determined. A search result is output from a match detection signal line corresponding to the word memory cell.

Referring to FIG. 4, which shows a block diagram of a conventional CAM circuit, this conventional CAM has word memories 11a, 11b,..., Each consisting of 5-bit memory cells for holding search data. 11f, an address decoder 15 for decoding each memory cell in the word memory, a data input / output circuit 12 for reading / writing a search data bit pattern and data stored in the memory cell, A match detection signal output circuit 13 that outputs a priority address signal AD in response to the supply of the match signal CS.

Next, the operation of the conventional content addressable memory circuit will be described with reference to FIG. 4. First, a one-word search data bit pattern is input to the data input / output circuit 12. The data input / output circuit 12 latches the search data, and stores all or a predetermined part of the bit pattern of the search data and the word memories 11a, 11b,.
.., 11f, the bit pattern is compared with the bit pattern of a portion corresponding to the bit pattern.

As a result of this comparison, each word memory 11a, 1
, 11f corresponding to each of the word memories (eg, 11a, 11c) having the same bit pattern. A match signal CS corresponding to the mismatched word memory is output to the match detection signal line corresponding to the word memory of the mismatch, and a match signal CS corresponding to the mismatch of logic '0' is output to the match detection signal output circuit 13. Supply the result.

The coincidence detection signal output circuit 13 outputs a coincidence signal C
The highest priority matching line (for example, 11
The priority address signal AD corresponding to a) is output and supplied to the address decoder 15. The address decoder 15
The priority address signal AD is decoded, and one of the word lines 24a, 24b,..., 24f corresponding to each of the word memories 11a, 11b,. An access signal is output to the word lines (24a in this example). Thus, the data stored in the word memory 11a corresponding to the word line 24a to which the access signal has been output is stored in the data input / output circuit 12a.
Is read out.

One word memory 11a of the conventional CAM circuit shown in FIG. 4 (word memory 11 for convenience of description below)
5 is a circuit diagram showing the configuration of the conventional C.
The word memory 11 of the AM circuit includes memory cells 111, 112,...
4 is provided.

[0008] The memory cell 111 includes inverters I11 and I12 each having a mutual input connected to a mutual input to form a memory element for storing information of logic "1" or logic "0".
And a transistor M11 in which each output of the inverters I11 and I21 is connected to the bit line 231 and a gate is connected to the word line 24, and an output of the inverter I12 is connected to the bit bar line 261 and each gate is connected to the word line 24. , And transistors M13 and M14 connected in series with each other so as to connect the bit line 231 and the bit bar line 261 to each other.

Similarly, memory cells 112,..., 11
5 are inverters I21 and I22,..., I51 and I52 which form a memory element, data input / output transistors M21,... M51, and transistors M22,. And transistors M23, M24,..., M53, and M54.

The transistors M13, M23,... M5
3 have inverters I11, I21,.
The transistors M14, M24,...
Each gate of M54 is connected to inverters I12, I22,.
..Connect to the output of I52.

The match detection signal line 14 has a gate connected to the transistors M13 and M14, M23 and M24,..., M53 of each of the memory cells 111, 112,.
, M54 connected to the series connection point of each pair of the transistors M15, M25,... M55, and one transistor M15 of the match detection signal line 14. A transistor M5 having one end connected to the other end and one end connected to the ground potential GND, and a gate connected to the CLK line 30, and an input connected to the other end of the other transistor M55 of the match detection signal line 14, and a match signal CS from the output. , A P-channel transistor P1 connected between the input of the inverter I1 and the power supply VDD and receiving a clock CLK at its gate, and a P-channel transistor P2 having its gate connected to the output of the inverter I1. Is provided.

Next, with reference to FIG. 5, a detailed operation of the conventional CAM circuit at the time of matching / mismatch search of the word memory 11a will be described.
It becomes 0 ', and the transistor P1 becomes conductive, precharging the coincidence detection signal line 14. At this time, the transistor M5 is turned off and the coincidence detection signal line 14 is connected to the ground G.
The precharge is performed by being separated from the ND. In this manner, first, after the match detection signal line 14 is precharged, a match search is performed.

Here, it is assumed that the memory cell 111 stores logic "1". In this case, the inverter I11
Is logic '1', and the transistor M13 is conducting. A logic '
It is assumed that 1 'is searched. That is, the bit line 231
Is logic '1' and the bit bar line 261 is logic '0'. Further, the word line 24 is maintained in a state of logic “0”. The CLK line 30 becomes logic "1", and the transistor M5 becomes conductive. In this case, since the transistor M13 is conducting, the logic
1 ′ is connected to the transistor M13 via the transistor M13.
15 to the gate of the transistor M
15 becomes conductive. That is, the bit information stored in the memory cell 111 and the bit line 231 and the bit bar line 2
When the bit information in the search data input via 61 matches, the corresponding transistor M15 is turned on.

As described above, the memory cells 111, 112,
... Bit pattern and bit line 2 stored in 115
, 232,..., 235, bit bar line 261,
When all the bit patterns of the search data input through 262,..., 265 match, the charge precharged to the match detection signal line 14 is the transistor M5.
5,..., M25, M15, M5, thereby discharging the coincidence detection signal line 14, and the part on the side of the inverter I1 becomes a state of logic '0'. Inverter I1 inverts this logic "0" and outputs the logic "
1 ′ as a match detection signal CS
Supply 3

Next, it is assumed that the memory cell 111 stores information of logic "0", contrary to the above. In this case, the output side of the inverter M12 is logic "1", and the transistor M14 is turned on. It is assumed that a logic "1" match search is performed on the memory cell 111 in the same manner as described above. That is, the bit line 231 is at logic '1' and the bit bar line 261 is at logic '0'. CLK line 30 is logic '
1 ', and the transistor M5 is turned on. In this case, since the transistor M14 is conducting, the logic '0' of the bit bar line 261 is supplied to the gate of the transistor M15 via the transistor M14, but the transistor M15 is supplied with the logic '0'. In response, the non-conductive state is maintained. That is, in the case of a mismatch, the charge precharged to the match detection signal line 14 is not discharged.

As described above, the memory cells 111, 112,
... Bit pattern and bit line 2 stored in 115
, 235, and the bit bar line 26
When any one of the bit patterns of the search data input via 1, 262,..., 265 does not match, the match detection signal line 14 holds the state of logic “1” due to precharge. And the inverter I1 has the logic '
The logic '0' is supplied to the transistor P2 by inverting the logic '1'. The transistor P2 latches the logic '0' and outputs the logic '0'.
It is supplied to the match detection signal output circuit 13 as a match signal CS corresponding to the mismatch of 0 '.

The logic of the clock CLK becomes "0" in the next CLK cycle, and the match detection signal line 14 is precharged to prepare for the next match detection operation.

However, in the above match detection operation, the bit pattern stored in the word memory 11 and the bit line 2
4, even when the bit pattern of the search data input via the bit bar line 26 is matched each time in a plurality of CLK cycles, the match detection signal line 14
Performs a discharge operation and a precharge operation, which are match detection operations, every CLK cycle. Therefore, each CLK
Although the match detection result output in step (1) does not change, the detection circuit operates, so that useless current is consumed, which causes an increase in current consumption.

[0019]

In the above-described conventional content addressable memory circuit, in the match detection operation, when match detection is performed when the same result as in the previous detection operation can be expected, that is, when the same word is detected. Even if the match detection occurs continuously in the memory, the match detection operation and the precharge operation are repeated every CLK cycle, so that useless current is consumed, which is a drawback of increasing power consumption. .

It is an object of the present invention to provide a content addressable memory circuit which reduces power consumption when the same result as the result of the previous match detection can be expected.

[0021]

SUMMARY OF THE INVENTION A content addressable memory circuit according to the present invention responds to the supply of a match signal of a match between a memory cell having a bit number of one word, a search data pattern, and a match between a stored data pattern. A memory cell array including a match detection signal line for performing a match detection operation and generating a match detection signal, and having a plurality of word memories for storing the search data for each word, and reading and writing the search data pattern and the storage data. And a data input / output circuit for outputting a match detection output signal in response to the supply of the match detection signal, wherein the match detection signal line is connected to the memory cell. The match between the search data and the memory cell corresponding bits of each of the storage data for each of A cell match detection circuit having the number of bits of one word for generating the match detection signal for each of the memory cells, having first and second detection elements for independently detecting a mismatch; I have.

[0022]

FIG. 2 is a block diagram showing a first embodiment of the present invention, in which constituent elements common to those in FIG. The content addressable memory (CAM) circuit of the present embodiment shown in FIG. 1 includes an address decoder 15, a data input / output circuit 12, and a match detection signal output circuit 13 which are common to those of the prior art. Instead, a word memory 11Aa, which includes a match detection circuit composed of memory cells of 5 bits each and detects a match / mismatch for each memory cell and outputs the detection result data for each memory cell as a match detection signal.
, 11Af are provided.

Word memory 1 characterizing the present embodiment
1Aa (word memory 11A for the sake of convenience in the following description) is provided with common reference characters / numerals for components common to FIG. 5, and FIG. The word memory 11A of the content addressable memory (CAM) circuit in the form of
, 115 and memory cells 111, 112,... Instead of the conventional coincidence detection signal line 14.
, 115 and the bit lines 231, 232,.
..235, bit bar lines 261,262,... 26
A match detection circuit 4 for detecting the match / mismatch with the search input data supplied through the memory 5 for each memory cell and outputting the detection result data for each memory cell as a match detection signal.
, 45, and outputs a match detection signal CS.

Each of the coincidence detecting circuits 41, 42,..., 45 has the same configuration.
11, 112,..., 115
13, M14, M23 and M24, ..., M53 and M5
4 connected to the series connection point of each set
.. M55 connected in series to form A, and a drain connected to one end of the transistor M55 that outputs the match detection signal CS, and a gate connected to the transistors M15, M25,. M5
5, a P-channel type transistor M16 for detecting mismatch, in which the source is connected to the ground potential GND, respectively,
M26,... M56. The other end of one transistor M15 of the match detection signal line 14A is connected to the power supply VDD.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2. First, the operation at the time of coincidence detection will be described. Here, the memory cell 111 stores logic "1". Therefore, the output of the inverter I11 is logic "1", and the transistor M13 is conducting. Logic "1" is applied to this memory cell 111.
Shall be searched. That is, the bit line 231 is set to logic “1” and the bit bar line 261 is set to logic “0”. Further, the word line 24 is kept at the state of logic “0”. Since the transistor M13 is conducting, the logic “1” of the bit line 231 changes to the transistor M1.
3, and supplied to the gate of the transistor M15, whereby the transistor M15 is turned on. That is, when the bit information stored in the memory cell 111 matches the bit information in the search data input via the bit line 231 and the bit bar line 261, the corresponding transistor M15 is turned on. On the other hand, the signal of logic “1” of the bit line 231 is also supplied to the gate of the transistor M16, but the transistor M16 remains off.

As described above, the memory cells 111, 112,
... Bit pattern and bit line 2 stored in 115
, 235, and the bit bar line 26
When all the bit patterns of the search data input via the first, second,..., 265 match, the match detection signal lines 14A are connected to the match detection transistors M15, M2.
, M55 to output the potential of the power supply VDD. As a result, the coincidence detection signal line 14A becomes a state of logic "1", and supplies this logic "1" to the coincidence detection signal output circuit 13 as the coincidence detection signal CS.

Next, the operation at the time of mismatch detection will be described. Conversely, it is assumed that the memory cell 111 stores information of logic "0". In this case, the inverter M1
The output of 2 is logic '1' and transistor M14 is conductive. It is assumed that a logic "1" match search is performed on the memory cell 111 in the same manner as described above. That is, the bit line 231 is set to logic “1”,
Are set to logic '0' respectively. In this case, since the transistor M14 is conducting, the bit bar line 261
Is supplied to the gate of the transistor M15 via the transistor M14.
15 keeps the non-conductive state in response to the supply of the logic "0". On the other hand, the logic level is also applied to the gate of the transistor M16.
0 is supplied, and the transistor M16 outputs the logic '0'
Become conductive in response to the supply of

As described above, the memory cells 111, 112,
... Bit pattern and bit line 2 stored in 115
, 235, and the bit bar line 26
If any one of the bit patterns of the search data input via the first, second,..., 265 does not match, the match detection signal line 14A is connected to the transistor M16,
M26,... M56 are connected to the ground GND via the transistor corresponding to the mismatch, so that the match detection signal line 14A is in a logic '0' state,
The logic “0” is supplied to the match detection signal output circuit 13 as a match signal CS corresponding to the mismatch.

As described above, in the CAM circuit of the present embodiment, the bit pattern stored in the word memory and the bit pattern of the search data input via the bit line and the bit bar line change, and the previous search is performed. Since the match detection operation is performed only when a change occurs in the result, the power consumption can be reduced by suppressing the match detection operation when the same result as the previous search result is expected.

More specifically, in a simulation, when the power consumption is calculated under exactly the same conditions for a 4-bit × 64-word CAM circuit having the same circuit configuration, the same detection result is obtained continuously. In such a case, the power consumption can be reduced by as much as 95%, confirming the effectiveness of the invention.

Next, referring to FIG. 3, which shows a second embodiment of the present invention in which components common to those in FIG. This embodiment is different from the first embodiment in that the data input / output circuit 12 and the word memories 11Aa, 11Ab,
, 11Af, a latch circuit 16 for latching the match search data bit pattern in response to the supply of the clock CLK is provided.

The operation of this embodiment will be described with reference to FIG. 3. In the above-described first embodiment, the data input / output circuit 12 outputs the match search data bit pattern from the memory cells 111, 112,. The search is started at the time when the data is input to 115, and the match detection signal CS is supplied to the match detection signal output circuit 13. This coincidence detection signal output circuit 13
When designing a system that operates with an arbitrary system CLK using the priority address signal AD which is the output data of the above, the output timing of the priority address signal AD is determined depending on the input timing of the match search data bit pattern. Would. Therefore, the timing design of the entire system becomes difficult.

In this embodiment, since the latch circuit 16 latches the match search data bit pattern from the data input / output circuit 12 in response to the supply of the clock CLK, the timing design of the whole system of this type is facilitated. .

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made. For example, the match detection and mismatch detection transistors may be composed of N-channel and P-channel transistors, respectively, or the match detection transistor may be connected to GND according to the output polarity, and the mismatch detection transistor may be connected to VDD.
May be connected. In the embodiment, 6 words, 5 words
Although a circuit configuration of bits is used, the number of words and the number of bits are not limited. In addition to the structure of the memory cell 111 described in this embodiment, many other structures are known, and the present invention includes those having variously changed configurations. Further, the latch circuit shown in the second embodiment may be inserted between the coincidence detection signal output circuit and the word memory to latch the data of the coincidence detection signal line without departing from the gist of the present invention. Of course, it can be applied.

[0035]

As described above, in the content addressable memory circuit according to the present invention, the coincidence detection signal line is provided for each of the memory cells so that the coincidence retrieval result of the retrieval data and the bit corresponding to each memory cell of the storage data is obtained. Is provided with first and second detection elements for independently detecting a match and a mismatch of a cell, and a cell match detection circuit for generating a match detection signal. The match detection operation is performed only when the bit pattern of the search data input via the interface changes and the previous search result changes, so if the same result as the previous search result is expected By suppressing the coincidence detection operation, there is an effect that power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a word memory characterizing a first embodiment of a content addressable memory circuit of the present invention.

FIG. 2 is a block diagram showing the present embodiment.

FIG. 3 is a block diagram showing a second embodiment of the content addressable memory circuit of the present invention.

FIG. 4 is a block diagram showing an example of a conventional content addressable memory circuit.

FIG. 5 is a circuit diagram showing a configuration of the word memory of FIG. 4;

[Explanation of symbols]

10, 10A Memory cell array 11a to 11f, 11Aa to 11Af Word memory 12 Data input / output circuit 13 Match detection signal output circuit 14a to 14f, 14Aa to 14Af Match detection signal line 15 Address decoder 16 Latch circuit 24a to 24f Word line 41 to 45 Match detection circuits 111 to 115 Memory cells 231 to 235 Bit lines 261 to 265 Bit bar lines I11, I12, I1 Inverters M11 to M16, M21 to M26, ..., M51 to M
56, M5, P1, P2 transistor

Claims (4)

[Claims] 1. Match detection in which a match detection operation is performed in response to supply of a match signal of a match search result between a memory cell having the number of bits of one word and a search data pattern and a storage data pattern to generate a match detection signal. A memory cell array including a signal line and a plurality of word memories for storing the search data for each word, a data input / output circuit for reading and writing the search data pattern and the storage data, and supplying the match detection signal A match detection signal output circuit that outputs a match detection output signal in response to the memory cell, wherein the match detection signal line is provided for each of the memory cells. There are first and second detection elements for independently detecting the match and mismatch of the match search result between the memory cell corresponding bits. Content addressable type memory circuit, characterized in that it comprises a cell match detection circuit of the number of bits of the one-word for generating each said coincidence detection signal for each of said memory cells Te. 2. The cell match detection circuit is connected in series between a first power supply and an output terminal of the match detection signal line in the order of the bit data of one word, and the first of each of the storage data is stored in the memory. A first transistor that conducts in response to the coincidence corresponding to the logical value of the first data, and a second transistor that conducts in response to the non-coincidence corresponding to the second logical value of each of the stored data to connect the output terminal to the second terminal. 2. The content-addressable memory circuit according to claim 1, further comprising the second transistor connected to a power supply. 3. The content addressable memory circuit according to claim 1, wherein the operation is performed without precharging the match detection signal line. 4. A content according to claim 1, further comprising a latch circuit between the memory cell array and the data input / output circuit, the latch circuit latching the match search data pattern in response to supply of a clock signal. Address type memory circuit.