JPH1145564A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a wide data band without increasing the production cost. SOLUTION: A data line 120 runs parallel with bit line pairs 400, 500 and is commonly used plural memory cell plates 15, 16 as well as two sets of the bit line pairs 400, 500 and 401, 501. Two piece of transfer gate control signals 20, 30 run orthogonally with the bit line pairs and are respectively commonly used in the same memory cell plate 15. A register 100 is connected to the data line 120. The one bit line 400 of the bit line pairs is electrically connected by the transfer gate control signal 20 and the other bit line 402 is connected by the transfer gate control signal 30 to respectively common data line 120.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device such as a dynamic RAM requiring a wide data bandwidth or a device equipped with the dynamic RAM.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device of this type, a column switch selection signal runs on a plurality of memory cell plates, and data of a selected column address is transferred to a data line pair orthogonal to a bit line pair. Had been transferred to.

FIG. 6 is a circuit diagram showing a first conventional example of a semiconductor memory device.

The conventional semiconductor memory device is composed of two memory cell plates 15 and 16 and has a data bus width of 2 bits, that is, 2-bit data can be read from the global data buses 11 and 12 simultaneously.
The sense amplifiers 201,... Are shared by the right and left memory cell plates 15,.

Memory cells 1000 and 12 having the same address
The operation of reading 00 2-bit data will be described. First, when the word line 300 selected by the row address is activated, the memory cells 1000, 1100, 1200,
The data of 1300, 1800, and 1900 are bit lines 400, 401, 402, 403, 408, and 409, respectively.
Is read out. At the reference level, the potential difference between the paired bit lines 500, 501, 502, 503, 508, and 509 is the sense amplifier 210, 201, 212, 2
Amplified at 03,218,209. The column address is decoded by the column decoder circuit 10, and a column switch selection signal 110 running parallel to the bit line pair is activated. The bit line pairs 400, 500 and 402, 502 amplified by the sense amplifiers 210, 212 are connected to the bit line pairs 400, 500, 402, 502 via column switches 600, 700, 602, 702, respectively.
Of local data buses 41, 51 and 6 orthogonal to
1 and 71, respectively. The 2-bit data is amplified by data amplifiers 81 and 91 and transferred to global data buses 11 and 12.

The operation of writing data to a memory cell will be described. The 2-bit write data of the global data buses 11 and 12 is written to the sense amplifiers 210 and 212 by the data amplifiers 81 and 91 via the column switches 600, 700, 602 and 702, and is written to the memory cells 1000 and 1200. .

[0007] DRAM of present 16 Mbit class or higher
However, although the chip size and the space of the column address are large, the minute potential difference needs to be amplified at high speed by the sense amplifier. Therefore, the bit line pair cannot be long in order to suppress the parasitic capacitance. Therefore, column decoder circuits having a large occupied area are collectively arranged, column switches are dispersed, and low resistance metal wiring such as aluminum is used for a column switch selection signal. However, in the current state of the art of LSI manufacturing, compared with silicide and polycide, which are the material of bit lines, it is necessary to increase the thickness of metal wiring in order to reduce the layer resistance and secure the wiring life. Due to the limitations of the etching technique, a wiring pitch twice or more is required. Therefore, in the configuration of FIG. 3 in which one column switch selection signal simultaneously selects two sets of column switches, the pitch of the column switch selection signal is four times the pitch of the bit line, so that even in manufacturing at a high yield. It is advantageous.

FIG. 7 is a circuit diagram showing a second conventional example of the semiconductor memory device.

This conventional example is generally called a VRAM or a dual-port RAM. As in the first conventional example, data in the memory cell 1000 is stored in the column switch 6.
Global data buses 11 and 12 via 00 and 700
And can be input / output via the parallel port. In addition, the data of the memory cell 1000 can be latched by the register 2100 via the data transfer switches 2400 and 2500, and is transferred to the global serial data bus 2011 via the serial address switches 2600 and 2700, and Can be input / output via the serial port. In this configuration, since the memory cell data is transferred to the register 2100, while the data is being input / output through the serial port, the word line 3
00 can be deactivated.

[0010]

In recent years, as the performance of microprocessors has been improved, the bandwidth with respect to the main memory, that is, the data transfer speed has become a bottleneck in performance. As one of the solutions, one-chip integration of logic and DRAM has been proposed.

In the semiconductor memory device of the first conventional example shown in FIG. 6, in order to increase the bus width in order to improve the bandwidth, the number of data line pairs running perpendicular to the bit lines must be increased. Absent. Therefore, there is a problem that the chip area is greatly increased.

Further, a method of extending a concept of the semiconductor memory device of the second conventional example shown in FIG. 7 and providing a register shared by a plurality of memory cell plates and transferring data by a data line is also conceivable. In this method, the data in the register is written via the data line to the sense amplifier in which the memory cell data has been amplified. Therefore, the data line must be a complementary pair. In addition, since the data line from each memory cell plate to the shared register becomes longer, the data line must be a metal wiring so that the access time does not deteriorate. That is, one pair of data lines is required for each pair of bit lines. However, as described above, since the pitch of the metal wiring needs to be twice or more the bit line pitch, in order to manufacture with a high yield,
Four layers of metal wiring for the data line are required, and the number of steps is increased, so that the manufacturing cost is significantly increased.

In Japanese Patent Application Laid-Open No. 62-76093,
Adjacent true complement bit lines share one data line,
There has been proposed a method of transferring half the data of the activated sense amplifier. However, this method also requires one data line for each pair of bit lines, and requires two layers of metal wiring for the data lines.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of realizing a wide data bandwidth without increasing the manufacturing cost.

[0015]

In order to achieve the above object, a semiconductor memory device according to the present invention runs in parallel with a bit line pair and has a plurality of memory cell plates and a plurality of memory cell plates and N bit line pairs. A data line, N control signals running orthogonal to the bit line pair and shared in the same memory cell plate, and at least one register connected to each of the data lines. Means for selectively electrically connecting one of a pair of the N bit line pairs to the common data line in accordance with the N control signals.

[0016]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention. FIG. 2 shows FIG.
5 is a timing chart showing operation waveforms of the semiconductor memory device of FIG.

The data line 120 is a pair of bit lines 400 and 5
00 in parallel with a plurality of memory cell plates 15,
16 and two bit line pairs 400, 500 and 40
1,501. The two transfer gate control signals 20 and 30 run orthogonally to the bit line pair and are shared in the same memory cell plate 15. The register 100 is connected to the data line 120. The transfer gate control signal 20 causes one bit line 400 of the bit line pair, and the transfer gate control signal 30 causes the other bit line 402 to
Each is electrically connected to a common data line 120.

The semiconductor memory device of the present embodiment can simultaneously transfer half the number of sense amplifiers that are activated at the same time, that is, three data out of the six sense amplifiers shown in FIG. .

Memory cells 1000, 1200, 1800
The operation procedure for simultaneously reading data from memory cells 10
A description will be given with reference to the operation waveform of FIG. First, the word line 3 selected by the row address
00 is activated, and the memory cell 1
000,1100,1200,1300,1800,1
900 data are sense amplifiers 210 and 20 respectively.
It is amplified at 1, 212, 203, 218, 209. Subsequently, the transfer gate control signal 20 is activated,
One of the bit lines 400, 402, 408 of the bit line pair amplified by the sense amplifiers 210,... Is transferred to the bit line 40 via transfer gates 130, 132, 138.
Data lines 120, 122, 12 running parallel to 0,.
8 and the memory cells 1000, 120
Three data of 0,1800 are transferred. These data are amplified by the registers 100, 102, and 108, and are simultaneously output to the outside of the memory cell plate 15. When the data is transferred to the registers 100,..., The word line 300 is deactivated and the sense amplifiers 210,. Can be prepared.

In order to write data D1 to memory cell 1000, first, data D1 is written to register 100. To write this to the memory cell 1000, the following procedure is performed. That is, the selected word line 300
Are activated again, and the transfer gate control signal 20 is activated. Sense amplifiers 210, 201,
Since 212, 203, 218 and 209 are not yet activated, the transfer gates 130, 132 and 138 are not activated.
, One of bit lines 400, 402, 40 of a bit line pair connected to data lines 120, 122, 128
8, the data of the registers 100, 102, and 108 is written. That is, the memory cell 1000
Is destroyed by the data D1 of the register 100. Of course, if the data in the register 100 is not rewritten, the same data as the memory cell 1000 is written since the original memory cell data is held in the register 100. One of the bit lines 401, 403, and 409 of the bit line pair is connected to the data line 12
Transfer gate 1 connected to 0, 122, 128
31, 133, 139 transfer gate control signal 3
Since 0 is inactive, data of the memory cells 1100, 1300, 1900 selected by the common word line 300 is transferred to the bit line pair 401,. That is, the data Q2 held in the memory cell 1100 is applied to one of the bit lines 401 of the bit line pair as in the case of reading.
Is held. When the sense amplifiers 210,... Are activated, the data of the registers 100,. Bit lines 401 and 40 connected to
3, 409, the data of the memory cells 1100,... Are amplified and written to the memory cells 1100,.

As described above, the semiconductor memory device of the present embodiment can be treated as a write-back operation when the register is regarded as a cache. That is, when the memory cell data at a certain address is transferred to the register, not only when the data at that address is read but also when the data is written, only the register is written and the memory cell is not accessed. When an address different from the register data is accessed, if the register data has been rewritten, the word line of the original address is selected, the write back to the memory cell is performed in the above procedure, and then a new address is accessed. . When the frequency of writing is relatively low, there is a control method of writing back every time data is written to the register, and this can be easily realized by the configuration of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention. FIG. 4 is a timing chart showing operation waveforms of the semiconductor memory device of FIG.

In the semiconductor memory device of the present embodiment, one data line runs for each pair of bit lines, so that the bandwidth is twice that of the first embodiment. In this case, although two layers of metal wiring are required as data lines, the manufacturing cost is increased.
It is overwhelmingly advantageous in terms of cost-effectiveness as compared with the two-layer metal wiring method described in JP-A-76093. In this example, all the memory cells selected by activating one word line are transferred to the register. Therefore, as shown in the operation waveform of FIG. 4, when writing data,
Before activating the word line 300, the transfer gate control signal 20 can be activated. Therefore, the sense amplifier can be activated without waiting for the time for decoding the row address and the time for the register to invert the data of the memory cell, and there is an advantage that the sensing can be performed at high speed and stably as compared with the first embodiment. .

FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention.

The semiconductor memory device of this embodiment has two registers 100 and 101 for one data line 120. By switching the registers using the register control signals 13 and 14, memory cells having different row addresses or different transfer control signals can be stored in different registers. It can be controlled as a so-called 2-way set associative system, and further improvement in performance can be expected.

[0026]

As described above, according to the present invention, assuming that N is a natural number, the present invention runs in parallel to a bit line pair and has a plurality of memory cell plates and a plurality of data lines shared by N sets of bit line pairs. , N control signals running orthogonal to the bit line pairs and shared in the same memory cell plate, at least one register connected to each of the data lines, and N control signals. Means for selectively electrically connecting one of the N pairs of bit lines to a common data line without increasing the number of metal wiring layers and without increasing manufacturing costs. A wide data bandwidth can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart showing operation waveforms of the semiconductor memory device of FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention.

FIG. 4 is a timing chart showing operation waveforms of the semiconductor memory device of FIG. 3;

FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention.

FIG. 6 is a circuit diagram showing a first conventional example of a semiconductor memory device.

FIG. 7 is a circuit diagram showing a second conventional example of a semiconductor memory device.

[Explanation of symbols]

10 Column decoder circuit 11, 12, 150, 151, 152, 153, 15
8,159 Global data bus 13,14 Register control signal 15,16 Memory cell plate 20,21,30,31 Transfer gate control signal 40,41,42,50,51,52,60,61,6
2, 70, 71, 72 local data buses 80, 81, 82, 90, 91, 92 data amplifiers 100, 101, 102, 103, 108, 109 registers 110, 111, 118, 119 column switch selection signals 120, 121, 122, 123, 128, 129 Data lines 130, 131, 132, 133, 138, 139, 1
40, 141, 142, 143, 148, 149 Transfer gate 201, 203, 209, 210, 212, 218, 2
21, 223, 229 Sense amplifiers 300, 301, 309, 310, 311, 319 Word lines 400, 401, 402, 403, 408, 409, 4
10,411,412,413,418,419,50
0, 501, 502, 503, 508, 509, 51
0, 511, 512, 513, 518, 519 Bit line 600, 601, 602, 603, 608, 609, 6
11,613,619,700,701,1702,7
03, 708, 709, 711, 713, 719 Column switch 1000, 1001, 1009, 1010, 1011
1019, 1100, 1101, 1109, 1110,
1111, 1119, 1200, 1201, 1209,
1210, 1211, 1219, 1300, 1301,
1309, 1310, 1311, 1319, 1800,
1801, 1809, 1810, 1811, 1819,
1900, 1901, 1909, 1910, 1911,
1919 memory cell 2010 serial counter circuit 2011 global serial data bus 2020 data transfer control signal 2040, 2050 local serial data bus 2020 serial data amplifier 2100, 2101, 1091 serial register 2110, 2111, 119 serial address switch selection signal 2400, 2401, 409 , 2500, 2501,
2509 data transfer switches 2600, 2601, 2609, 2700, 2701,
2709 Serial address switch

Claims (5)

[Claims] 1. A memory cell plate on which a plurality of memory cells are arranged on a matrix of a plurality of word lines and a plurality of bit line pairs, and columns of sense amplifiers connected to the respective bit line pairs. A semiconductor memory device comprising at least two memory cell plates, comprising: a plurality of data lines running parallel to the bit line pairs and shared by the plurality of memory cell plates; A single control signal running orthogonally to and shared within the same memory cell plate; at least one register connected to each of the data lines; and Means for electrically connecting one of the line pairs to the data line. Means for activating the sense amplifier after the control signal is inactive and one of the word lines is selected in the same memory cell plate;
2. The semiconductor memory device according to claim 1, further comprising: means for activating said sense amplifier after said control signal is activated without selecting any of said word lines. 3. A means for activating the sense amplifier after the control signal is inactive and one of the word lines is selected in the same memory cell plate;
2. The semiconductor memory device according to claim 1, further comprising: means for activating said sense amplifier after one of said word lines is selected and said control signal is activated. 4. A memory cell plate on which a plurality of memory cells are arranged on a matrix of a plurality of word lines and a plurality of bit line pairs, and columns of sense amplifiers respectively connected to the bit line pairs. In a semiconductor memory device including at least two memory cell plates, if N is an integer of 2 or more, the semiconductor memory device travels in parallel with the bit line pair and has a plurality of the memory cell plates and N sets of the bits. A plurality of data lines shared by a pair of lines, N control signals running orthogonal to the bit line pairs and shared by the same memory cell plate, and connected to each of the data lines; And at least one register, and the N control signals
Means for selectively electrically connecting one of the pair of bit line pairs to the common data line. 5. In the same memory cell plate, means for activating the sense amplifier after one of the word lines is selected while none of the control signals are inactive, and one of the word lines is 5. The semiconductor memory device according to claim 4, further comprising: means for activating said sense amplifier after one of said selected control signals is activated.