JPH1141925A - Switching power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a dynamic output control available by installing a duty control circuit for controlling the duty of a PWM signal to be input into a switching circuit based on the output of a judging circuit. SOLUTION: A judging circuit 11 judges which is larger and smaller between a voltage signal Ddc and reference data Dst and then sends the judgement result to a duty controlling circuit 12. To the duty control circuit 12, a rapid clock CLK is input. The duty control circuit 12 divides the frequency of the clock CLK and makes a frequency of a PWM clock suitable for the operation of a switching circuit 2 and then sends out a PWM signal appropriate for an initial condition. Based on the output of the duty control circuit 12, a driver circuit 6 drives a switching device (transistor TR) of the switching circuit 2. The switching circuit 2 takes in electric energy by a switching operation from a DC voltage source VBB and then supplies specified DC current to a secondary side of a high frequency transformer T.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a switching power supply. The present invention is particularly applicable to a system in which a digital high-speed clock is built in a device such as an exchange, an A / D converter such as a subscriber circuit can be easily used, and a constant current value or a constant voltage value for any purpose. Can be used for a device that is required to be set freely and periodically.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing a configuration example of a conventional switching power supply circuit. In the figure, reference numeral 1 denotes a load connected between an A terminal and a B terminal of a power supply. Here, an example in which a telephone is used as a load is shown. That is, the power supply circuit shown in the figure functions as a power supply circuit for the telephone.

[0003] Reference numeral 2 denotes a switching circuit for switching the DC voltage VBB by a switching element. In the switching circuit 2, TR is a transistor as a switching element, and the primary winding L1 of the high-frequency transformer T is connected to the collector load. That is, the DC voltage VBB
Is applied to a series circuit of the primary winding L1 and the transistor TR.

L2 is a secondary winding of the high frequency transformer T, D2
Is a rectifying diode connected in series with the secondary winding L2, and L3 is a choke coil connected in series with the diode D2. D1 is a diode connected in parallel to a series circuit of the secondary winding L2 and the diode D2. The diode D1 is for forming a loop when a current flows from the energy stored in the choke coil L3 to the load when the diode D2 is turned off by switching.

[0005] C1 is a capacitor connected between one end of the choke coil L3 and the common line. The capacitor C1 and the choke coil L3 constitute a smoothing circuit. That is, it is a circuit for rectifying and smoothing the high-frequency alternating current generated on the secondary side of the high-frequency transformer T by switching by the transistor TR.

R3 is a current detection resistor for detecting a current flowing through the load 1. Reference numeral 3 denotes an output current detection circuit that receives a voltage generated across the current detection resistor R3 and generates a signal Vdc corresponding to the output current. Reference numeral 4 denotes an error amplifier that compares the output voltage Vdc of the output current detection circuit 3 with the reference voltage Vst and generates a signal corresponding to the difference. The error amplifier 4 includes an input resistor R1 receiving Vdc, an operational amplifier U1, a feedback resistor R2 connected between the input and output of the operational amplifier U1, and a capacitor C2 connected in parallel with the feedback resistor R2. ing. The output voltage Vdc is input to one input of the operational amplifier U1, and the reference voltage Vst is input to the other input.

Reference numeral 5 denotes a duty control circuit for generating a PWM pulse signal by comparing the output of the error amplifier 4 with a sawtooth wave. The duty control circuit 5 controls the ON time of the switching transistor TR to be variable. 6
Is a buffer as a driver circuit that receives the output of the duty control circuit 5, and the output of the buffer 6 drives the switching transistor TR. The operation of the circuit thus configured will be described as follows.

During normal operation, the duty control circuit 5
Outputs a PWM signal having a constant duty ratio to switch the switching transistor TR. The DC voltage VBB is turned on / off at a constant duty ratio, and a high-frequency alternating current is generated on the secondary side of the high-frequency transformer T. The generated high-frequency AC is rectified by the rectifying diode D2.

While the switching transistor TR is on, the secondary coil L2 is connected to the secondary circuit of the high-frequency transformer T.
A current flows through a loop of → diode D2 → choke coil L3 → resistor R3 → load 1 → secondary coil L2. At this time, the capacitor C1 is charged. At this time, a smoothing circuit is formed by the choke coil L3 and the capacitor C1, and converts a DC pulsating current into a flat DC voltage. On the other hand, when the switching transistor TR is turned off, the energy stored in the choke coil L3 is changed from the diode D1 to the choke coil L3 to the resistor R3 to the load 1 to the load 1.
A current flows through the loop of the diode D1. In this way, the load current (output current) Idc flows through the load 1 continuously.

Here, if the load current decreases for some reason, the error amplifier 4 gives a control signal to the duty control circuit 5 to increase the on-time of the transistor TR.
Conversely, if the load current increases for some reason, the error amplifier 4 gives a control signal to the duty control circuit 5 to reduce the on-time of the transistor TR. Such PW
By the M control, the load current Idc is controlled to be constant. That is, when the output decreases, the output level of the error amplifier 4 decreases, the duty control circuit 5 outputs a PWM pulse having a duty such that the on-time increases, and when the output increases, the output level of the error amplifier 4 increases. The duty control circuit 5 outputs a PWM pulse with a duty that shortens the on-time, and keeps the output constant.

FIG. 11 is a flowchart showing the operation of the conventional circuit. First, the output current I is detected by the output current detection circuit 3.
dc is detected, and a voltage Vdc proportional to Idc is output (S1). At this time, a voltage Vst corresponding to a target current is supplied from the reference voltage generator to the error amplifier 4 (S2). The error amplifier 4 sends a voltage obtained by amplifying a difference voltage (error) between the detection voltage Vdc and the reference voltage Vst to the duty control circuit 5 (S3). At this time, the error amplifier 4 forms an integrator (low-pass filter), and changes the output slowly even when the Vdc changes sharply.

The duty control circuit 5 steadily generates a sawtooth wave or a triangular wave, compares the output of the error amplifier 4 with the sawtooth wave, and creates a PWM clock (PWM pulse) (S4). Here, the PWM duty (the ratio of the ON time of the transistor TR in one cycle) changes when the DC level of the error amplifier 4 rises or falls while the sawtooth wave is constant. Finally, the negative feedback circuit shown in FIG. 11 goes to Vdc = Vst.

In the driver circuit (here, the buffer 6),
The switching transistor TR of the switching circuit (DC / DC converter) 2 is driven according to the output (logic level) of the duty control circuit 5 (S5). DC / DC
The converter 2 takes in the electric energy by switching from the DC voltage VBB of the main body, and
A predetermined DC current is supplied to the next side (S6). A desired current or voltage can be supplied to the load 1 by repeating the above operation in order from step S1 to S6.

Most of the switching power supplies described above output a required power supply (for example, +5 V or +3.3 V) from a predetermined main power supply (for example, AC 100 V or DC 48 V) in a fixed manner. The purpose of such a power supply is to obtain a stable output with high efficiency, and there has been no request other than fine adjustment of the output to make the output variable.

[0015]

For example, in a subscriber circuit or the like, a function of supplying power to a terminal, which is called power supply, is required. This circuit is a kind of power supply, but is characterized by a small output of about 2 W, and requires a constant current and complicated control of switching from a constant current to a constant voltage by line resistance. Such demands have not been found in conventional switching power supplies. Today, switching power supply technology has been required in subscriber circuits for the purpose of power saving.

The present invention has been made in view of the above problems, and has as its object to provide a switching power supply capable of performing dynamic output control.

[0017]

[Means for Solving the Problems]

(1) FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 10 are denoted by the same reference numerals. In the figure,
1 is a load, 2 is a switching circuit (for example, a DC / DC converter) for supplying a current or a voltage to the load 1, R3 is a detection resistor for detecting the power supplied from the switching circuit 2 to the load 1, and 3 is a detection resistor R3. An output current detection circuit 10 for receiving the output of the switching circuit 2 and detecting the output current of the switching circuit 2 is an A / D converter which receives the output Vdc of the output current detection circuit 3 and converts it into a digital signal.
In the switching circuit 2, TR is a main switching element for switching the DC voltage VBB, for example, a transistor.

Reference numeral 11 denotes an output Dd of the A / D converter 10.
c is a judgment circuit that compares the reference value Dst with the reference value Dst and outputs a comparison result.
Reference numeral 2 denotes a duty control circuit that controls the duty of the PWM signal input to the switching circuit 2 so that the output current or the output voltage becomes constant upon receiving the output of the determination circuit 11. The present invention is characterized in that all components are realized by digital circuits. Reference numeral 6 denotes a driver circuit that receives the output of the duty control circuit 12 and drives the switching circuit 2.

According to the configuration of the present invention, since all the components of the switching power supply have a digital configuration, the output can be instantaneously and flexibly controlled by digital information or software.

(2) In this case, the duty control circuit inputs a high-speed clock, generates a required periodic clock of a PWM signal from the clock, and generates a PWM signal.
When changing the pulse width, control is performed by increasing or decreasing the width of one pulse of the clock as a minimum variable range.

According to the configuration of the present invention, the output can be varied with one pulse of the high-speed clock as a minimum unit. (3) The determination circuit compares the output of the output detector with a reference value, and increases the pulse width when the output of the output detector is smaller than the reference value. When the output of the output detector is equal to the reference value, Is characterized in that a control signal for maintaining the pulse width and reducing the pulse width when the output detector output> the reference value is given to the duty control circuit.

According to the configuration of the present invention, the output of the power supply circuit is digitally compared with the reference value, and the output of the power supply circuit is controlled by negative feedback control so that the output and the reference value become equal according to the comparison result. Stabilization can be achieved.

(4) In the PWM control, there is no particular limitation on the increase or decrease of the pulse in the steady state, and the pulse width is randomly increased or decreased. According to the configuration of the present invention, the output of the switching power supply can be kept constant by a simple configuration of the duty control circuit.

(5) In the PWM control, the pulse width in the steady state is limited by an increase / decrease, a constant increase / decrease pattern is provided, and the duty control in the pattern is performed for a certain period of time. And selecting a new pattern for increasing or decreasing the output of the switching circuit based on the determination result.

According to the configuration of the present invention, several PWM patterns for driving the switching circuit are provided, and one of these PWM patterns is selected according to the output, thereby suppressing low-frequency noise in the power supply unit. Switching power supply can be realized.

(6) In the PWM control, when the output load changes suddenly and it is necessary to greatly change the pulse width of the switching element, the width of the duty pulse is increased over several clocks. It is characterized by changing.

According to the configuration of the present invention, it is possible to quickly cope with a sudden change in the output load. (7) Further, the duty control pattern is stored in a memory in the form of pattern data, and the pattern data is read out during the duty control, and the PWM pulse width is controlled by the pattern data.

According to the configuration of the present invention, a PWM pattern can be easily created by storing in the memory a pattern having a certain limitation on the increase and decrease of the pulse.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. An embodiment of the present invention will be described with reference to the principle block diagram shown in FIG.

FIG. 2 is an explanatory diagram of the PWM control according to the present invention. (A) is a clock CLK, (b) is a PWM pulse waveform, and (c) is a waveform obtained by adding one clock to the PWM pulse waveform. The duty control circuit 12 of FIG.
A high frequency clock CLK as shown in FIG.
This clock is frequency-divided to generate a PWM pulse having a constant period as shown in FIG. In (b), Ton is the time when the switching element is turned on, and Toff is the time when the switching element is turned off. Ton + Toff
Is one cycle of the PWM pulse. When the output current decreases, the time during which the switching element is turned on is increased as shown in FIG. However, since it is not an analog circuit but a digital circuit, Ton increases or decreases stepwise with a width of one clock.

The operation of the circuit shown in FIG. 1 will be described below with reference to the flowchart shown in FIG. FIG. 3 is a flowchart showing the operation of the duty random control according to the present invention. The output current detection circuit 3 receives the voltage generated across the resistor R3 due to the flow of the output current Idc, and outputs a voltage signal Vdc proportional to Idc (S
1). The A / D converter 10 converts Vdc into digital data and outputs it as Ddc (S2). on the other hand,
The register 13 holds the reference data Dst corresponding to the target current value and outputs the same to the determination circuit 11 (S3).

The determination circuit 11 determines the magnitude relationship between Ddc and Dst (S4). The following types can be considered as the determination result. Ddc <Dst Ddc = Dst Ddc> Dst The judgment circuit 11 outputs the judgment result to the duty control circuit 1
Give to 2. A high-speed clock CLK is input to the duty control circuit 12. Duty control circuit 12
Divides the clock CLK to generate a PWM clock cycle suitable for the operation of the switching circuit 2. Then, PWM of an appropriate duty is transmitted as an initial state (S
5). The specific operation is as follows.

In the case of Ddc <Dst In this case, since the output current is smaller than the target value, the width of the current PWM clock is increased by one clock.

When Ddc = Dst Since the output current is in the target range, the current clock width is not changed. In the case of Ddc> Dst In this case, since the output current is larger than the target value, the current PWM clock width is reduced by one clock.

The driver circuit 6 switches the switching circuit 2 according to the output (logic level) of the duty control circuit 12.
Is driven (S6). The switching circuit 2 takes in electric energy by switching from the DC voltage VBB and supplies a predetermined DC current to the secondary side of the high-frequency transformer T (S7).
As described above, the current supplied to the load 1 can be kept constant by repeating the operations from step S1 to step S7.

In this embodiment, the case of constant current control has been described as an example, but the same applies to the case of constant voltage control.
That is, an output voltage detection circuit is used instead of the output current detection circuit 3. Other operations are exactly the same.

In this embodiment, since the output current is compared with the reference current value and negative feedback control is performed so that the output current and the reference current value become equal, the output is the output of the duty control circuit 12. The duty of the PWM pulse changes randomly.

Further, according to this embodiment, the duty control circuit 12 inputs a high-speed clock, generates a required periodic clock of the PWM signal from the clock,
When changing the pulse width as PWM, 1
By controlling the pulse width by increasing or decreasing the width of the pulse as the minimum variable range, it is possible to vary the output in units of one high-speed clock pulse as the minimum unit.

The determination circuit 11 compares the output Ddc of the A / D converter 10 with the reference value Dst, and increases the pulse width when Ddc <Dst, and increases the pulse width when Ddc = Dst. The width is maintained, and the pulse width is reduced when Ddc> Dst. By providing a control signal to the duty control circuit 12, the output of the power supply circuit is digitally compared with a reference value. The output can be stabilized by negative feedback control such that the circuit output is equal to the reference value.

Further, in the PWM control, there is no particular limitation on the increase / decrease of the pulse in the steady state, and the output of the switching power supply can be kept constant by controlling the pulse width at random.

FIG. 4 is an explanatory diagram of the first control method (duty random change method) of the present invention, and shows the case of the above-described duty random control. (A) PWM pulse waveform at the time of equilibrium, (b) PWM at the time of random control
It is a pulse waveform. This example shows an example in which the output current is small and the time Ton during which the switching element is turned on is increased by one clock. The present invention is characterized in that Ton discretely changes within a width of one clock.

In the present invention, the duty takes a discrete value represented by the following equation (see FIG. 2). Duty = Ton / (Ton + Toff) (1) This is a point different from the prior art. In the prior art, since an analog waveform such as a sawtooth wave or a triangular wave is used, any value of duty can be realized. The output voltage of the switching power supply according to the present invention is represented by the following equation. Output voltage = K × (Ton / (Ton + Toff)) × VBB = K · Duty (%) · VBB (2) where K is a proportionality constant determined by the turns ratio of the transformer and the like.

Therefore, the fact that the duty (%) takes a discrete value means that the output value becomes discrete. For example, with a high-speed clock of 32.7 MHz, 256
When creating a cycle of kHz, only 128 discrete values can be obtained. For example, the accuracy of the A / D converter is reduced to a practical 7 bits (0 to 127 in 1 mA steps).
mA) Even if the control is performed, the duty of 128 steps is insufficient.

In order to solve such a problem, the frequency of a high-speed clock must be further increased,
It is not impossible to further reduce, but it is not practical due to many technical requirements.

In order to solve such a problem, a predetermined output can be obtained by dynamically increasing or decreasing the width of the duty pulse between adjacent pulses. FIG. 5 is a diagram showing a main part of the first embodiment of the present invention, which solves the above problem. In the figure, the A / D converter 10 operates at a sampling period of 8 kHz, and the number of bits is 8 bits. The reference value of the determination circuit 11 is also 8 bits corresponding to the number of bits. The judgment circuit 11
Also operates at 8 kHz. The duty control circuit 12
It comprises a bit up / down counter 12a, a 7-bit duty counter 12b, and a period counter 12c.

The up / down counter 12a is a down / up (Down / Up) output from the determination circuit 11.
A Ton time is set by receiving a signal, an enable (EN) signal, a clock of 8 kHz, and an initial setting value as a load signal. The duty counter 12b
32.7 MHz clock, output of up / down counter 12a, 256 kHz from cycle counter 12c
Upon receiving the load clock of z, it outputs a PWM pulse. The cycle counter 12c divides the frequency of the 32.7 MHz clock to create a 256 kHz clock, and provides the clock to the duty counter 12b. The operation of the circuit thus configured will be described as follows.

As shown by the logic shown in FIG. 6, the determination circuit 11 converts the enable signal EN and the (Down / Up) signal into an up / down counter 12 of the duty control circuit 12.
Give to a.

That is, when the output Ddc> the reference value Dst, the enable signal EN is activated at L level,
The Down / Up signal is output at the L level to make it count down. When the output Ddc = the reference value Dst, the enable signal EN is set at the H level to be IN active, and Dow.
The n / Up signal is undefined (either H or L), and when the output Ddc <Dst, the enable signal EN is activated at the L level, and the Down / Up signal is output at the H level to count up. .

Output Da of up / down counter 12a
ta is controlled by the result of the determination circuit 11. The output Data of the up / down counter 12a becomes data of the initial value of the duty counter 12b. The cycle counter 12c divides the frequency of 32.7 MHz to create 256 kHz, and sends a load signal to the duty counter 12b every cycle of 256 kHz.

The duty counter 12b has a frequency of 256 kHz.
At the timing of z (every 3.9 μsec), the data of the up / down counter is fetched as an initial value. The duty counter has a maximum value (FFFFF)
FF) is counted up using 32.7 MHz as a clock. When the counter reaches the maximum value, a ripple carry is transmitted, and the ripple carry is input to the enable of the counter, so that counting up is stopped even if a clock is input after the maximum value. The counter restarts in the next 2
It is performed only after the initial value is loaded again at a cycle of 56 kHz. Therefore, the output of the ripple carry is 256
The PWM signal has a cycle of kHz and is turned on from the initial value to the maximum value of the counter. By dynamically changing the output Data (initial value) of the up / down counter 12a, the PWM pulse width (Ton) is dynamically varied.

That is, the circuit shown in FIG. 5 changes the count value of the up / down counter 12a based on the result of the determination circuit 11 and sets new duty information to the duty counter 12b every 8 kHz, thereby generating a PWM pulse. The output is dynamically changed to keep the output constant (duty random change method).

In the switching power supply circuit, it is necessary to stably follow a steep change in the detection output in order to stabilize the circuit, like a conventional error amplifier forms a low-pass filter. In the present invention, the function of the low-pass filter is that the A / D converter 10 takes in 8 k of data.
This is realized by sampling at every Hz, and by limiting the operation of the up / down counter to one every 8 kHz cycle.

The control of the PWM pulse according to the embodiment described above is as shown in FIG. 4. The Ton time of the PWM is randomly increased or decreased by one clock width according to the result of the determination circuit 11. You.

FIG. 7 is a circuit diagram showing a main part of the second embodiment of the present invention. The same components as those in FIG. 5 are denoted by the same reference numerals. The greatest feature of this embodiment is that the PW
The point is that the duty of the M pulse does not change randomly. The duty value is limited to a fixed pattern (duty limiting method).

In the duty control circuit 12, 12d
Is a pattern generation circuit in which a plurality of duty patterns are stored. For example, a ROM is used as the pattern generation circuit 12d. A ROM circuit 12e receives output data of the pattern generation circuit 12d as an address and outputs corresponding Ton time setting data.
The output of the ROM circuit 12e is provided as data to a duty counter 12b, and the duty counter 12b
Counts the clock during the time width given from the ROM circuit 12e. And the duty counter 1
2b outputs a PWM pulse.

FIG. 8 is a diagram showing an example of an occurrence pattern in the second control method (duty limitation method) of the present invention.
These patterns are stored in the pattern generation circuit 12d. (A) is a pattern at the time of equilibrium, (b) is a pattern that increases the Ton time by one clock at a constant period (pattern 1), and (c) is a pattern that increases the Ton time by one clock at a constant period shorter than (b). (Pattern 2),
(D) is a pattern (pattern 3) in which the Ton time is increased by one clock for a shorter period. Although only the pattern for increasing the clock is shown in the figure, the pattern for decreasing the clock is also stored in the pattern generation circuit 12d. The operation of the circuit thus configured will be described as follows.

The determination circuit 11 supplies the enable signal EN and the (Down / Up) signal to the pattern generation circuit 12d of the duty control circuit 12, as indicated by the logic shown in FIG. That is, when the output Ddc> the reference value Dst, the enable signal EN is activated at the L level, and when the output Ddc = the reference value Dst, the enable signal EN is enabled.
Is inactive at the H level, the Down / Up signal is undefined (either H or L), and the output Ddc <Dst
In this case, the enable signal EN is activated at the L level, and the Down / Up signal is output at the H level.

The pattern generation circuit 12d selects an optimum generation pattern according to the input signal and supplies the selected pattern to the ROM circuit 12e. The ROM circuit 12e receives the data given from the pattern generation circuit 12d as an address, and stores the data stored at the address in the duty counter 12d.
b.

Then, D which is the output of the ROM circuit 12e is
count a 32.7 MHz clock with a width of ata,
Output as a PWM pulse. The PWM pulse is 256
One cycle is kHz, and the pulse-on time Ton during that period is varied in several patterns. That is, the circuit shown in FIG. 7 changes the generation pattern of the pattern generation circuit 12d based on the result of the determination circuit 11, and sets new duty information in the duty counter 12b every 8 kHz.
The output is kept constant by changing the PWM pulse under a certain limit.

For example, when the output is slightly smaller than the reference value, pattern 1 (see FIG. 8) is output, and when the output is slightly smaller than the reference value, pattern 2 is selected, and the output is smaller than the reference value. When it becomes considerably smaller, select pattern 3. Conversely, when the output becomes larger than the reference value, the clock is reduced to generate a pattern in which Ton is shortened.

The effect of generating a PWM pulse under a certain restriction will be described. In the embodiment shown in FIG. 5, the duty of the PWM pulse is changed at random. In this case, Ton
The time is completely free to be random, and in the case of a circuit that is sensitive to noise such as a subscriber circuit, low-frequency noise in the power supply unit may be a problem.

256 kHz is a fundamental frequency. From 256 kHz of a rectangular wave, a harmonic of an integral multiple thereof is generated as noise. However, since the duty changes frequently, a spectrum component lower than 256 kHz is generated.
That is, in the case of the random control, a spectrum of a low frequency is generated.

On the other hand, when a certain limit is set for the change of the PWM width (see FIG. 8), the pattern 1 and the pattern 3
And 64 kHz and 128 kHz are generated, and the pattern 2
In this case, a spectrum component of 128 kHz is generated, but a spectrum lower than these is not generated in principle.

The operation of the circuit shown in FIG. 7 will be described below with reference to the flowchart shown in FIG. The output current detection circuit 3 detects the resistance R3
And outputs a voltage signal Vdc proportional to Idc (S1). A / D converter 10
Converts Vdc into digital data and outputs it as Ddc (S2). On the other hand, the register 13 holds the data Dst corresponding to the target current value,
(S3).

The determination circuit 11 determines the magnitude relationship between Ddc and Dst (S4). The following types can be considered as the determination result. Ddc <Dst Ddc = Dst Ddc> Dst The judgment circuit 11 outputs the judgment result to the duty control circuit 1
Give to 2. A high-speed clock CLK is input to the duty control circuit 12. Duty control circuit 12
Creates a PWM clock cycle suitable for the operation of the switching circuit 2 by inserting or thinning out the clock CLK into Ton. Then, a PWM having an appropriate duty is transmitted as an initial state (S5). The specific operation is as follows.

In the case of Ddc <Dst In this case, since the output current is smaller than the target value, the pattern generating circuit 12d changes the current PWM pattern to a pattern having one duty greater than the current PWM pattern.

When Ddc = Dst Since the output current is in the target range, the current PWM pattern is not changed. In the case of Ddc> Dst In this case, since the output current is larger than the target value, the pattern generation circuit 12d changes the current PWM pattern to a pattern smaller by one data than the current PWM pattern.

The driver circuit 6 switches the switching circuit 2 according to the output (logic level) of the duty control circuit 12.
Is driven (S6). The switching circuit 2 takes in electric energy by switching from the DC voltage VBB and supplies a predetermined DC current to the secondary side of the high-frequency transformer T (S7).
As described above, the current supplied to the load 1 can be kept constant by repeating the operations from step S1 to step S7.

In this embodiment, the case of constant current control has been described as an example, but the same applies to the case of constant voltage control.
That is, an output voltage detection circuit is used instead of the output current detection circuit 3. Other operations are exactly the same.

In this embodiment, the output of the determination circuit 11 is connected to the pattern generation circuit 12d, and determines which of the patterns shown in FIG. 8 is to be used.
The Ton time is set in the duty counter 12b every time by the ROM circuit 12e, and the pattern generation circuit 12d outputs the address information of the ROM circuit 12e and sets the data. Pattern generation circuit 12d
Changes the required pattern at 8 kHz or longer.

According to this embodiment, a PWM pattern can be easily created by storing in the memory a pattern having a certain limit on the increase and decrease of the pulse.

Further, according to this embodiment, several PWM patterns for driving the switching circuit are provided, and one of these PWM patterns is selected in accordance with the output, so that the low-frequency range of the power supply unit can be reduced. A switching power supply with reduced noise can be realized.

Further, in any of the above-described duty random change method and the duty limit method, when the output load suddenly changes and it is necessary to greatly change the pulse width of the switching element. Can greatly change the width of the duty pulse over several clocks. According to this, it is possible to quickly cope with a sudden change in the output load.

[0074]

As described in detail above, according to the present invention, (1) a switching power supply for generating a constant DC output from a current or a rectified AC power supply, wherein the output is a constant current or It is a constant voltage, and to make its output a constant value,
In an apparatus for performing PWM control, means for detecting an output current or an output voltage, an A / D converter for converting the detection result into a digital signal (Ddc), and a target output current or output voltage value of a digital signal Shape (Ds
a storage circuit that holds the reference data at t), a determination circuit that compares Ddc and Dst of the digital signal,
A duty control circuit for generating a PWM signal for switching based on the output of the determination circuit. The output of the determination circuit drives a main switching element of the switching power supply unit by a driver circuit, so that all components of the switching power supply are digitally configured. Therefore, the output can be instantaneously and flexibly controlled by digital information or software.

(2) In this case, the duty control circuit inputs a high-speed clock, generates a required periodic clock of the PWM signal from the clock, and
When the pulse width is changed, the output can be varied with one pulse of the high-speed clock as the minimum unit by increasing or decreasing the width of one pulse of the clock as a minimum variable range.

(3) The determination circuit compares the output of the output detection unit with a reference value, and increases the pulse width if the output of the output detection unit is smaller than the reference value. In the case of, maintain the pulse width, and reduce the pulse width if the output detector output> reference value. By providing a control signal to the duty control circuit, digitally compare the output of the power supply circuit with the reference value. Then, the output can be stabilized by performing negative feedback control such that the output of the power supply circuit becomes equal to the reference value according to the comparison result.

(4) In the PWM control, there is no particular limitation on the increase or decrease of the pulse in the steady state.
The output of the switching power supply can be kept constant by the configuration of the control circuit.

(5) In the PWM control, the pulse width in the steady state is limited to increase or decrease, and a constant increase / decrease pattern is provided. By selecting a new pattern for increasing or decreasing the output of the switching circuit based on the determination result, several PWM patterns for driving the switching circuit are provided, and one of these PWM patterns is selected according to the output. A switching power supply that suppresses low-frequency noise of the power supply unit can be realized.

(6) In the PWM control, when the output load suddenly changes and it is necessary to greatly change the pulse width of the switching element, the width of the duty pulse is increased over several clocks. By changing it, it is possible to quickly cope with a sudden change in the output load.

(7) Further, the duty control pattern is stored in the form of pattern data in a memory, and the pattern data is read out during the duty control, and the pulse width of the PWM is controlled by the pattern data to thereby control the pulse width. By storing in a memory a pattern having a certain restriction on increase and decrease, a PWM pattern can be easily created.

As described above, according to the present invention, a switching power supply capable of performing dynamic output control can be provided.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is an explanatory diagram of PWM control according to the present invention.

FIG. 3 is a flowchart showing an operation of duty random control according to the present invention.

FIG. 4 is an explanatory diagram of a first control method of the present invention.

FIG. 5 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 6 is a diagram illustrating an operation logic of a determination circuit.

FIG. 7 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 8 is a diagram showing an example of an occurrence pattern in the second control method of the present invention.

FIG. 9 is a flowchart showing the operation of duty pattern restriction control according to the present invention.

FIG. 10 is a diagram illustrating a configuration example of a conventional switching power supply circuit.

FIG. 11 is a flowchart showing the operation of the conventional circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Load 2 Switching circuit 6 Driver circuit 3 Output current detection circuit 10 A / D converter 11 Judgment circuit 12 Duty control circuit 13 Register R3 Current detection resistance TR Switching element D1, D2 Diode L3 Choke coil C1 Capacitor

Claims (7)

[Claims] 1. A switching power supply for generating a constant DC output from a DC or rectified AC power supply, wherein the output is a constant current or a constant voltage. Means for detecting an output current or an output voltage, and A for converting the detection result into a digital signal (Ddc).
/ D converter, a storage circuit for holding a target output current or output voltage value as reference data in the form of a digital signal (Dst), a determination circuit for comparing Ddc and Dst of the digital signal, and a determination circuit And a duty control circuit for generating a PWM signal for switching from the output of the switching power supply, wherein the output of the determination circuit drives a main switching element of the switching power supply unit by a driver circuit. 2. The duty control circuit inputs a high-speed clock, generates a required periodic clock of a PWM signal from the clock, and changes the pulse width as one PWM by changing the width of one pulse of the clock. The switching power supply according to claim 1, wherein the switching power supply is controlled by increasing or decreasing the minimum variable range. 3. The determination circuit compares the output of the output detection unit with a reference value, and increases the pulse width when the output detection unit output <the reference value, and increases the pulse width when the output detection unit output = the reference value. 3. The switching power supply according to claim 2, wherein the control signal is supplied to the duty control circuit to maintain the pulse width and to reduce the pulse width when the output detection unit output> the reference value. 4. The switching power supply according to claim 3, wherein in the PWM control, there is no particular limitation on the increase or decrease of the pulse in a steady state, and the pulse width is increased or decreased at random. 5. In the PWM control, a restriction is made on increase / decrease of a pulse width in a steady state, a constant increase / decrease pattern is provided, and duty control in the pattern is performed for a certain period of time. 4. The switching power supply according to claim 3, wherein a new pattern for increasing or decreasing the output of the switching circuit is selected based on the following. 6. In the PWM control, when the output load changes suddenly and it is necessary to greatly change the pulse width of the switching element, the width of the duty pulse is greatly changed over several clocks. The switching power supply according to claim 5, characterized in that: 7. The duty control pattern is stored in a memory in the form of pattern data, the pattern data is read during duty control, and the PWM pulse width is controlled by the pattern data. The described switching power supply.