JPH114144A - Device for generating code group - Google Patents

Abstract

PROBLEM TO BE SOLVED: To instantaneously output another code group from the state of a shift register in a code group generating circuit to be reference even at the time of the code group provided with a drasitically long cycle when the two code groups being optionally different in phase are simultaneously generated and, moreover, to unnecessitate the shift register of another code group generating circuit and complicated initial value calculation. SOLUTION: A code group generating device is provided with a code generating means 1 for generating the longest group (M-group), which consists of the shift register 2 provided with optional bit width and an arithmetic circuit 3 for feeding-back, and an arithmetic means 4 for executing optional calculation from the respective register outputs of the shift register 2. In this case, the generation polynomical expression of the code generating means 1 and an arithmetic expression guided from an optional phase which is desired to progress are executed in the respective register outputs of the shift registers 2 so that the code group being different only in phase are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a longest sequence, Gol
The present invention relates to an apparatus for generating a code sequence such as a d-code.

[0002]

2. Description of the Related Art A digital code can be generated by using a register and an arithmetic circuit for performing an operation on the register contents, and feeding back the operation contents to the register. For example, a period 15 in which the generator polynomial is 1 + x + x ⁴
In the case of the longest sequence (M sequence), since the operation can be realized by one exclusive OR and the feedback method is simple, the configuration is simple as shown in FIG. In FIG. 6, reference numeral 20 denotes a shift register circuit including four registers R1 to R4, and reference numeral 21 denotes an exclusive OR circuit that calculates the exclusive OR of the registers R1 and R4, and outputs the output to the register R1. Register R
An initial value is set in each of the registers 1 to R4 (except when the contents of all registers are 0), a clock is applied to these registers R1 to R4, and the contents are shifted by the clock. An M-sequence code is generated.

FIG. 7 is a generalized version of the configuration of FIG.
Generator _{polynomial, 1 + h 1 x + h} 2 x 2 + h 3 x 3 + ··· + h k-1 x
^k-1 + x ^k ( _{where hn} is '1' or '0'). In FIG. 7, 22 is k
A shift register circuit including a plurality of registers R1 to Rk;
An arithmetic circuit 23 for feedback is formed by an exclusive OR circuit.

It is considered that these M-sequence code generation circuits simultaneously generate two code sequences. Here, the two code sequences use the same generator polynomial and the same initial value of the register, but when one code sequence is used as a reference, the other code sequence always advances by an arbitrary phase. It refers to something. That is, the code sequence has only a different phase.

For example, in two M-sequence code generation circuits 24 and 25 as shown in FIG.
1 to R4, the same initial value is set, and the M-sequence code generation circuit 2
A clock is supplied by 5 for an arbitrary phase to be advanced, and the state of the register is advanced. Thereafter, by applying the same clock to both sequence codes, a code sequence having only an arbitrary phase difference can be generated.

However, according to such a method,
Before generating two code sequences at the same time, it is necessary to advance the state of the shift register by an arbitrary phase.
If the M sequence has a period of about 15, it is easy to arbitrarily advance the phase. However, if the phase is arbitrarily advanced with a code sequence having a very long period, a very long time may be required.

When a part of a code sequence is continuously generated, for example, a code sequence generation circuit which repeats phases 0 to 7 is compared with a code sequence generation circuit whose phase is advanced by 8 (phases 8 to 15 are repeated). ) Is very difficult to implement because there is no physical time to advance the state of the shift register.

In such a case, the state of the shift register advanced by an arbitrary phase by the initial value calculation circuit 27 with respect to the reference code sequence generation circuit 26 as shown in FIG. In general, it is configured such that it can be set as an initial value of the other code sequence generation circuit 28.

However, it is complicated to calculate the state of the shift register advanced by an arbitrary phase, and when it is possible to arbitrarily set even the initial value of the reference code sequence generation circuit, the other side is required each time. It is necessary to calculate the initial value of the code sequence circuit.

[0010]

As described above, according to the prior art, when two code sequences having only arbitrarily different phases are simultaneously generated, and when a code sequence having a very long period is handled, one of the codes is used. There is a problem that it takes a very long time to advance the shift register state of the code sequence generation circuit. Also, when a part of the code sequence is continuously generated, the initial value of the shift register of the other code sequence generation circuit is not determined by a complicated calculation in advance for the reference code sequence generation circuit. There is a problem that must not be.

The present invention solves the above-mentioned conventional problem. When two code sequences having only arbitrarily different phases are simultaneously generated, even if the code sequence has a very long period, the reference code can be used. The other code sequence can be output instantaneously from the state of the shift register of the sequence generation circuit, and the shift register of the other code sequence generation circuit and complicated initial value calculation are not required. It is an object of the present invention to provide an excellent code sequence generation device capable of generating a code sequence at an arbitrary period by initializing a shift register of a code sequence generation circuit at an arbitrary timing.

[0012]

In order to solve the above problem, the present invention provides a code generation means for generating a longest sequence (M sequence) comprising a shift register having an arbitrary bit width and an operation circuit for feedback. And operation means for performing an arbitrary operation from each register output of the shift register. Further, the present invention is characterized in that the shift register can freely set an initial value by a load signal. The invention according to claim 3, wherein the arithmetic means stores a plurality of data having the same bit width as the shift register. Means, means for selecting one data from them, and for each element of the selected data B and each register output X of the shift register, y _k = BX = b ₁ x ₁ + b ₂ x ₂ + b ₃ x ₃ + ... + b
in that it consists of calculating circuit for performing calculation of _{k-1 x k-1 +} b k x k is obtained by the features.

As described above, when simultaneously generating two code sequences arbitrarily different only in phase, even if the code sequence has a very long cycle, the instantaneous shift from the state of the shift register of the reference code sequence generation circuit is performed. To output the other code sequence. In addition, the shift register of the other code sequence generation circuit and complicated initial value calculation are not required, and the shift register of the reference code sequence generation circuit is initialized at an arbitrary timing, so that it can be executed at an arbitrary period. An excellent code sequence generation device capable of generating a code sequence is obtained.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention provides a code generation means for generating a longest sequence (M sequence) comprising a shift register having an arbitrary bit width and an operation circuit for feedback. Operation means for performing an arbitrary operation from the output of each register of the shift register. If two code sequences having only arbitrarily different phases are simultaneously generated, even if the code sequence has a very long period, The other code sequence can be output instantaneously from the state of the shift register of the reference code sequence generation circuit. Further, it has the effect of eliminating the need for the shift register of the other code sequence generation circuit and complicated initial value calculation.

Further, the invention according to claim 2 is characterized in that the shift register can freely set an initial value by a load signal, and simultaneously transmits two code sequences having only arbitrarily different phases. When the code sequence is generated, the code sequence can be generated at an arbitrary cycle by initializing the shift register of the reference code sequence generation circuit at an arbitrary timing.

According to a third aspect of the present invention, the arithmetic means includes means for storing a plurality of data having the same bit width as the shift register, and means for selecting one of the data. For each element of the data B and each register output X of the shift register, y _k = BX = b ₁ x ₁ + b ₂ x ₂ + b ₃ x ₃ +... + B
which is characterized in that it consists of calculating circuit for performing calculation of _{k-1 x k-1 +} b k x k, if only phase to produce simultaneously the different code sequences Optionally the plurality of "arbitrary phase" Has the effect that a desired phase can be selected and output.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 shows a code sequence generating apparatus according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a code sequence generation circuit for generating a longest sequence (M sequence), which generates a reference code sequence by supplying a clock to the shift register circuit 2. The generator polynomial is 1 + h ₁ x + h ₂ x ² + h ₃ x ³ +... + H _k-1 x
^k-1 + ^xk ( _{where hn} is "1" or "0"). Reference numeral 2 denotes a shift register circuit having an arbitrary bit width (here, k bits), and reference numeral 3 denotes an operation circuit 3 for feedback, and these constitute a code sequence generation circuit 1. Numeral 4 denotes an arithmetic unit, which is a shift register circuit 2
, And outputs a code sequence advanced by an arbitrary phase from the code sequence generation circuit 1.

The operation of the above-configured code sequence generator will be described. First, regarding the code sequence generation circuit 1, the current state of each register of the shift register circuit 2 is X, the content of each register after advancing the n clock phase is Y, and the k × k matrix derived from the generation polynomial is A.
Then, the following equation is established. Y = [y ₁ y ₂ y ₃ ... Y _k−1 y _k ] = A ⁿ X (1) Here, the matrix A is defined as follows.

(Equation 1) ... (2)

Here, attention is paid to the element y k in the k-th column of Y. This is the value of the register Rk of the shift register circuit 2 in the state where the n clock phase is advanced, that is, the value of the output 1 of the code sequence generation circuit 1 in the state where the n clock phase is always advanced. I have. Therefore, assuming that this value is output 2, output 2 always outputs a code sequence with n clock phases ahead of output 1. A 1 × k matrix B representing a k-th row of a matrix obtained by raising A to the nth power is defined as follows. B = [b ₁ b ₂ b ₃ ... B _k-1 b _k ] = [000... 01] ^An ... (3) Then, y _k can be represented by the following equation. _{y k = BX = b 1 x} 1 + b 2 x 2 + b 3 x 3 + ... + b k-1 x k-1 + b k x k ··· (4) that is, to generate a code sequence advanced n clock phase It can be seen that the sum of the k-th row of the matrix obtained by raising the matrix A to the n-th power and the value of each register of the shift register circuit 2 may be calculated.

From the above, the arithmetic unit 4 in FIG.
2 has the configuration of the arithmetic unit 5 shown in FIG. 2, and performs the operation of the right term of the above equation (4). To explain these contents more specifically, showing the configuration when the generator polynomial is 1 + x + x ⁴ in FIG. 3.

[0021] In FIG. 3, the code sequence generating circuit 6 generates the longest sequence (M-sequence) of the period 15 of the generator polynomial 1 + x + x ^4, the arithmetic circuit 7 is an operational circuit for advancing the arbitrary phase. The output 2 outputs a code sequence that is advanced by an arbitrary phase from the output 1 of the code sequence generation circuit 6. Here, assuming that “arbitrary phase” is 4, the matrix B is as follows.

(Equation 2) _{y 4 = BX = b 1 x} 1 + b 2 x 2 + b 3 x 3 + b 4 x 4 = x 1 + x 4 ··· (7) from which generator polynomial is the 1 + x + x ^4, only the phase is 4 different code sequences Can be obtained at the same time. The configuration is shown in FIG. In FIG. 4, the arithmetic unit 8 performs the arithmetic operation of Expression 7, and generates the generator polynomial 1+
This is an arithmetic circuit including an exclusive OR circuit that always outputs a code sequence that is four phases ahead of the code sequence output 1 of x + x ⁴ .

As described above, according to the first embodiment of the present invention, an operation of y _k = BX is performed on a 1 × k matrix B derived from a code sequence generator polynomial and an arbitrary number of phases to be advanced. By providing an arithmetic circuit, when two code sequences having only arbitrarily different phases are simultaneously generated,
Even if the code sequence has a very long cycle, the other code sequence can be output instantaneously from the state of the shift register of the reference code sequence generation circuit. The shift register and complicated initial value calculation can be eliminated.

In the above description, the code generation circuit 1 is limited to a circuit for generating the longest sequence (M sequence) code. However, the code generation circuit 1 is arbitrarily defined in k-bit data X stored in the register. A code sequence that repeats the linear transformation with the k × k matrix A, that is, the register content Y when the phase is advanced by one.
Can be implemented similarly as a circuit that generates a code sequence represented by.

(Embodiment 2) A second embodiment according to the second aspect of the present invention uses a code sequence generation apparatus having the same configuration as that of the first embodiment. In the second embodiment,
The load signal and the initial value signal connected to the shift register circuit 2 of FIG. 1 are actively used. The shift register circuit 2 in FIG. 1 can set the state of each register to the state given by the initial value signal by setting the load signal to “1”. Therefore, by setting the load signal to “1” at an arbitrary timing, each register of the code sequence generation circuit 1 can be initialized, and a code sequence can be generated at an arbitrary cycle. Since the code sequence generation circuit 1 has an arbitrary cycle, the output of the arithmetic unit 4 also has a code sequence with an arbitrary cycle having a different phase.

As described above, according to the second embodiment of the present invention, by setting the load signal of the shift register circuit 2 to "1" at an arbitrary cycle, the shift register of the reference code sequence generation circuit can be changed. Initialization can be performed at an arbitrary timing, and when two code sequences having only arbitrarily different phases are simultaneously generated, a code sequence can be generated at an arbitrary cycle.

(Embodiment 3) FIG. 5 shows a third embodiment of the present invention.
This shows the configuration of the arithmetic unit 9 of the code sequence generation device according to the third embodiment corresponding to FIG. 2, and the configuration of the entire code sequence device is the same as that shown in FIG. In FIG. 5, the memory circuit 10 stores a plurality of 1 × k matrix data,
The selection circuit 11 selects one desired data from the plurality of data. Arithmetic circuit 12 for each element of each register output X of the selected data and the shift _{register, y k = BX = b 1} x 1 + b 2 x 2 + b 3 x 3 + ... + b k-1 x k-1 + b _{The operation of k} x _k (8) is performed. The memory circuit 10 stores data corresponding to a plurality of “arbitrary phases”, and the selecting circuit 11 is configured to select data of a desired “arbitrary phase”. Arbitrary phase "
Is input, and a desired phase can be output.

As described above, according to the third embodiment of the present invention, when simultaneously generating code sequences having only arbitrarily different phases, a plurality of "arbitrary phases" stored in the memory circuit 10 are supported. By selecting a desired “arbitrary phase” from the data to be input by the selection circuit 11 and inputting it to the arithmetic circuit 12, a desired phase can be selected from a plurality of “arbitrary phases” and output.

[0028]

As described above, the present invention provides a code generation means for generating a longest sequence (M sequence) comprising a shift register having an arbitrary bit width and an operation circuit for feedback, and each register of the shift register. A code sequence generation circuit serving as a reference even when a code sequence having a very long period is generated when two code sequences having only arbitrarily different phases are simultaneously generated by providing an arithmetic unit for performing an arbitrary operation from an output. , The other code sequence can be output instantaneously. In addition, the shift register of the other code sequence generation circuit and complicated initial value calculation are not required, and the shift register of the reference code sequence generation circuit is initialized at an arbitrary timing, so that it can be executed at an arbitrary period. An excellent effect that a code sequence can be generated is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a code sequence generation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of an arithmetic unit in FIG. 1;

FIG. 3 is a block diagram illustrating a specific example of a code sequence generation circuit in which the generation polynomial of the code sequence generation device is 1 + x + x ⁴ in the first embodiment of the present invention.

FIG. 4 is a block diagram showing a specific example of an arithmetic unit in which the generator polynomial of the code sequence generator according to the first embodiment of the present invention is 1 + x + x ⁴ , and the output 2 advances the phase of output 2 by 4 with respect to output 1

FIG. 5 is a block diagram illustrating a specific example of an arithmetic unit according to Embodiment 3 of the present invention.

FIG. 6 is a block diagram of an M-sequence code generation circuit whose generation polynomial is 1 + x + x ⁴

FIG. 7 shows that a generator polynomial is 1 + h ₁ x + h ₂ x ³ +... +
Block diagram of an M-sequence code generation circuit of h _k−1 x ^k−1 + x ^k

FIG. 8 is a block diagram of a conventional code sequence generation device that generates a code sequence that differs only in two phases at the same time by an M-sequence code generation circuit.

FIG. 9 is a block diagram showing the configuration of FIG.
Block diagram of a conventional code sequence generation device that generates a code sequence that differs only in two phases

[Explanation of symbols]

Reference Signs List 1 Code sequence generation circuit for generating longest sequence (M sequence) 2 Shift register circuit 3 Operation circuit for feedback 4 Operation device 5 y _k = BX = b ₁ x ₁ + b ₂ x ₂ + ... b _k-1 x
_k-1 + b _k x _k of the computing device generating polynomial is 1 + x + x code sequence generator is a ⁴ 7 arithmetic unit _{8 y 4 = x 1 + x} 4 operation unit 9 arithmetic unit 10 memory circuit 11 selects circuit 12 y ₄ = BX = B ₁ x ₁ + b ₂ x ₂ + b ₃ x ₃ + b
_{4 x 4 = x 1 + x} 4 arithmetic circuit 20 a shift register circuit 21 exclusive OR circuit 22 a shift register circuit _{23 1 + h 1 x + h} 2 x 2 + h 3 x 3 + ··· + h
^{_{k-1 x k-1 +}} x k in the arithmetic circuit 24 serving as a reference M-sequence code generation circuit 25 M-sequence code generation circuit becomes 26 reference code sequence generating circuit 27 initial value calculating circuit 28 code sequence generating circuit

Claims (3)

[Claims] 1. A code generation means for generating a longest sequence (M sequence) comprising a shift register having an arbitrary bit width and an operation circuit for feedback, and an arithmetic means for performing an arbitrary operation from each register output of the shift register And a code sequence generation device comprising: 2. The shift register according to claim 1, wherein an initial value can be freely set by a load signal.
The sequence code generation device according to the above. 3. The operation means includes means for storing a plurality of data having the same bit width as the shift register, means for selecting one of the data, and the selected data B and each register of the shift register. For each element of the output X, y _k = BX = b ₁ x ₁ + b ₂ x ₂ + b ₃ x ₃ +... B
_{k-1 x k-1 +} b k x k to an operational circuit for performing an operation that sequence code generating apparatus according to claim 1, wherein.