JPH1141106A - Delta sigma modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delta sigma modulator which prevents holding and feedback output of erroneous data of a delaying device which is caused because output change of a quantizer is asynchronous with a sampling clock and has an excellent S/N. SOLUTION: Data of a quantizer 210 are surely communicated on a feedback loop by making each feedback delaying device 212 to 214 hold the data in a frequency 2Fs after outputs of the device 210 are once held by a delaying device 211 in the frequency 2Fs which is twice as high that of a sampling frequency Also, noise increase which is caused by the difference between rise time and fall time of an output signal of the devices 212 and 213 is canceled by making an inputting part an integrated circuit of differential configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta-sigma modulator for an analog / digital converter that can be used in digital AV equipment and the like.

[0002]

2. Description of the Related Art A delta-sigma modulator is used in analog-to-digital conversion of digital AV equipment and the like. FIG. 3 is a block diagram of a conventional delta-sigma modulation circuit. In FIG. 3, reference numeral 301 denotes an input terminal, and 303 denotes a first terminal.
, 305 is a first integrator, 308 is a second subtractor, 309 is a second integrator, 310 is a quantizer, 311
Is a delay unit having an output delay function and a digital / analog conversion function, and 316 is an output terminal.

The signal input from the input terminal 301 is the first
After subtracting the difference from the feedback signal output from the delay unit 311 by the subtractor 303, the signal is integrated by the first integrator 305. The output of the first integrator 305 is obtained by the second subtractor 308 to obtain a difference from the feedback signal output from the delay unit 311, and then integrated by the second integrator 309. The output signal of the second integrator 309 is
After being quantized by 0, the signal is delayed by one sampling period by the delay unit 311 and becomes a feedback signal converted into analog. The output of the delay unit 311 is also taken out from an output terminal 316 as a digital output signal.

[0004] Assuming that an input signal is X, a quantization error generated when quantized by the quantizer 310 is Q, and an output signal is Y, the output Y of this system is expressed by (Equation 1).
Here, the transfer function Hi (Z) of the first integrator 305 and the second integrator 309 is represented by (Equation 2) in a Z-transform format.
(Strictly different, but the difference in characteristics within the band of interest is very small), and the transfer function of the delay unit 311 is represented by Z-1.

[0005]

## EQU1 ## Y = X + (1-Z ^-1 ) ² Q

[0006]

## EQU2 ## Hi (Z) = 1 / (1-Z ^-1 ) The coefficient (1-Z ^-1 ) ² of the quantization error Q in (Equation ¹ ) is 2
The following differential characteristic is shown, that is, the quantization error Q included in the output Y increases in magnitude toward higher frequencies and decreases in lower frequencies. Therefore, by sampling at a frequency sufficiently higher than the required band, noise in the band can be suppressed low.

However, in this delta-sigma modulator, the delay (31) which greatly affects the performance (SN ratio) of the entire system and converts a digital output signal into an analog feedback signal is used.
Since the output of 1 is supplied to three places, it is difficult to keep the performance of the converted analog feedback signal high. Therefore, it has been difficult to obtain high performance as a delta-sigma modulator.

For this reason, in an actual delta-sigma modulation device, a feedback signal supplied to each section is made independent. FIG. 4 shows a block diagram of an actual delta-sigma modulation circuit. In FIG. 4, reference numeral 401 denotes an input terminal;
Is the first subtractor, 405 is the first integrator, and 408 is the second integrator.
, 409 is a second integrator, 410 is a quantizer,
412 is a first delay unit, 414 is a second delay unit, 415
Is a third delay device, and 416 is an output terminal. Input terminal 4
01 to the quantizer 410 are input terminals 301 to 301 in FIG.
The operation is the same as that of the quantizer 310, and the operation thereof is the same. The signal quantized by the quantizer 410 is supplied to the first delay unit 4 every sampling period Ts.
12, is held by the second delay unit 414 and the third delay unit 415, is delayed by the sampling period Ts, is converted into an analog signal, and is converted into an analog signal by the first subtractor 403.
To the first integrator 405 and to the second subtractor 40
8, and is fed back to the second integrator 409.

[0009]

In the above-mentioned conventional delta-sigma modulator, an R is used as an integrator in order to improve the performance.
When the C integration is used, the operation of the delta-sigma modulation is performed continuously, so that the first delay unit 412 and the second delay unit 4
14. The holding of the output signal of the quantizer 410 to the third delay unit 415 is also performed at the same time. However, the quantizer 4
The operation of the first delay unit 412 and the second delay unit 41
4 and the third delay unit 415, the quantizer 41 immediately before or after the data holding timing due to element variation or clock timing.
If the output of 0 changes, the first delay unit 412, the second delay unit 414, and the third delay unit 415 may hold other data, thereby deteriorating the performance. As a result, it is difficult to obtain high performance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a high-performance delta-sigma modulation apparatus in which a feedback delay unit is made independent and erroneous data feedback or output is prevented. I do.

[0011]

In order to solve the above-mentioned problems, a delta-sigma modulator according to the present invention comprises a first subtractor for subtracting a feedback signal from an input signal, and an output of the first subtractor. A first integrator for integrating the output of the first integrator, a second subtractor for subtracting the feedback signal from the output of the first integrator, a second integrator for integrating the output of the second subtractor, A quantizer for quantizing an output of the second integrator; and a rate 2Fs which is twice the sampling frequency Fs, for outputting the output of the quantizer.
A first delay unit that holds the output of the first delay unit at a rate of 2 Fs, and then outputs a feedback signal to the first subtractor; and a first delay unit that holds the output of the first delay unit. A third delay unit that holds the output of the delay unit at a rate of 2Fs and then outputs a feedback signal to the second subtractor, and a fourth delay unit that holds the output of the first delay unit at the same rate Fs as the sampling frequency. Wherein the integration time constant Tc of the integrator has the same value as the sampling period Ts, and the output signal of the fourth delay unit is output.

With this configuration, after the output signal of the quantizer is held by the first delay unit and then held again by another feedback delay unit and output delay unit, data errors can be prevented.
A delta-sigma modulator that does not degrade performance can be provided.

According to another aspect of the present invention, there is provided a delta-sigma modulation apparatus for subtracting a feedback signal from a positive-phase input signal, and integrating an output of the first subtractor. A first integrator, a second subtractor for subtracting a sign-inverted feedback signal from the negative-phase input signal, a second integrator for integrating the output of the second subtractor, and the first integration A third operation of subtracting the output of the second integrator from the output of the integrator
, A fourth subtractor for subtracting the feedback signal from the output of the third subtractor, a quantizer for quantizing the output of the fourth integrator, and an output of the quantizer. A first delay unit that holds the sampling frequency Fs at a rate of 2Fs, and a second delay that holds the output of the first delay unit at a rate of 2Fs and then outputs a feedback signal to the first subtractor. , A third delay device that holds the inverted output of the first delay device at a rate of 2Fs, and then outputs a feedback signal to the second subtractor, and outputs the output of the first delay device at a rate of 2Fs.
a fourth delay unit that outputs a feedback signal to the fourth subtractor after holding at s, and a fifth delay unit that holds the output of the first delay unit at the same rate Fs as the sampling frequency. The integration time constant Tc of the integrator has the same value as the sampling period Ts, and the output signal of the fifth delay unit is output.

With this configuration, the input section has a differential configuration, and can compensate for noise and changes in characteristics of the input signal. Further, feedback signals having a complementary relationship to each other are supplied as differential signals. Since the influence of variations in the rise time and fall time of the feedback signal as an analog signal can be removed, the performance of the feedback signal, which greatly affects the performance of the entire system, can also be improved.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 is a block diagram showing a delta-sigma modulator according to Embodiment 1 of the present invention. In FIG. 1, 101 is an input terminal, 103 is a first subtractor, 1
05 is a first integrator, 108 is a second subtractor, 109 is a second integrator, 110 is a quantizer, 111 is a first delay unit, 112 is a second delay unit, 114 is a third delay unit. Delay device, 1
Reference numeral 15 denotes a fourth delay unit, and reference numeral 116 denotes an output terminal. Each delay unit has an output delay function and a digital-to-analog conversion function.

The signal input from the input terminal 101 is the first
After subtracting the difference from the feedback signal output from the delay unit 111 by the subtractor 103, the signal is integrated by the first integrator 105. The output of the first integrator 105 is obtained by the second subtractor 108 to obtain the difference from the feedback signal output from the delay unit 111, and then integrated by the second integrator 109. The output signal of the second integrator 109 is a quantizer 110
After that, the signal is held in the first delay unit 111 at a rate of 2Fs, which is twice the sampling frequency.
After that, the data held by the first delay unit 111 is output to the second delay unit 112, the third delay unit 114, and the fourth delay unit 115. Second delay device 112 and third delay device 11
4, the first subtractor 10 held at a rate of 2 Fs
3. The signal is output to the second subtractor 108, is held at the same rate as the sampling frequency in the fourth delay unit 115, and is then output from the fourth delay unit 115 to the output terminal 116 as an output signal.

For the sake of simplicity, a frequency twice the normal sampling frequency is set as a reference sampling frequency, the input signal is X, and the quantization error generated when the quantization is performed by the quantizer 110 is Q, Assuming that the output signal is Y, the output Y of this system is represented by (Equation 3). here,
Transfer function H of first integrator 105 and second integrator 109
i (Z) is expressed by the following equation (4) when expressed in the Z-transformation format (strictly different, but the difference in characteristics within the band of interest is very small), and the first delay unit 111 and the second delay unit Delay device 1
The transfer functions of the thirteenth and third delay units 114 are respectively represented as Z-1.

[0018]

## EQU3 ## Y = X + (1−Z ⁻² ) ² Q

[0019]

## EQU4 ## Hi (Z) = 1 / (1−Z ⁻² ) The coefficient (1−Z ⁻² ) ² of the quantization error Q in (Equation 3) can be obtained by considering the difference in the reference sampling frequency. Shows the same characteristics as the coefficient of the quantization error Q in the conventional example (Equation 1). That is, the transfer function is the same as that of the conventional delta-sigma modulator.

With such a configuration, in the delta-sigma modulation apparatus, the delay units that supply the feedback signals can be independent as the second delay unit 112 and the third delay unit 114, respectively, and at the same time, the first delay unit 112 and the third delay unit 114 can be independent of each other. Since the data held by the delay unit 111 at a rate of 2Fs, which is twice the sampling frequency Fs, is held again by the second delay unit 112 and the third delay unit 114, errors in data holding due to operation timing can be prevented. .

(Embodiment 2) FIG. 2 shows Embodiment 2 of the present invention.
1 is a block diagram of a delta-sigma modulation device according to the first embodiment. In FIG. 2, reference numeral 201 denotes a positive-phase input terminal;
Is the negative phase input terminal, 203 is the first subtractor, and 204 is the second subtractor.
, 205 is a first integrator, 206 is a second integrator, 207 is a third subtractor, 208 is a fourth subtractor, 2
09 is a second integrator, 210 is a quantizer, and 211 is a first integrator.
, 212 is a second delay, 213 is a fourth delay, 214 is a fifth delay, 215 is a fifth delay, 2
16 is an output terminal.

Hereinafter, the operation of the delta-sigma modulator configured as described above will be described.

A normal phase input terminal 201 and a negative phase input terminal 202
Are input with signals having phases opposite to each other. The signal input from the positive-phase input terminal 201 is subtracted by a first subtractor 203 from a feedback signal converted into an analog signal by a second delay unit 212, and then the signal is input by a first integrator 205. Is integrated. On the other hand, the signal input from the negative-phase input terminal 202 is output from the second subtractor 204 to the third delay unit 21.
After the difference from the inverted feedback signal whose sign has been converted to an analog signal in step 3 is obtained, the difference is integrated by the second integrator 206.

In the third subtractor 207, the outputs of the first integrator 205 and the second integrator 206 are added in opposite phases, but the output level is attenuated by half to match the gain. The output signal of the third subtractor 207 is subtracted by the fourth subtractor 208 from the feedback signal converted into an analog signal by the fourth delay 214, and then the second integrator 2
09. The quantizer 210 quantizes the output of the second integrator 209, and the first delay 211 generates a sampling rate 2F twice the sampling frequency Fs.
s.

The data held by the first delay unit 211 is output to a second delay unit 212, a third delay unit 213, and a fourth delay unit 214, and the data of the sampling frequency Fs
But at a third rate of 2Fs.
The input 13 is an inverted input, and inverted data is input. The data of the first delay unit 211 is simultaneously stored in the fifth delay unit 211.
Are held at the rate Fs by the delay unit 215, and are extracted as output signals from the output terminal 216.

Since the input section has a differential configuration, common-mode noise in the circuit is removed by the third subtractor 207, and the S / N ratio at the input section is improved by 3 dB. The outputs of the second delay unit 212 and the third delay unit 213 are output in opposite phases to each other, and these signals are also output to the third subtractor 2.
At 07, the opposite-phase addition is performed. Thereby, the second delay unit 21
2 to cancel the difference between the rise time and the fall time between the output of the third delay unit 213 and the output of the third delay unit 213, it is possible to eliminate one cause of deterioration of the SN ratio.
Further, the SN ratio can be improved.

In the above embodiment, the description has been made of an example in which the delta-sigma modulator is constituted by a second-order delta-sigma modulator. However, a delta-sigma modulator having a second-order or higher order can be similarly expanded.

[0028]

As described above, according to the delta-sigma modulation apparatus according to the present invention, it is possible to eliminate the cause of performance degradation due to malfunction caused by analog processing in the delta-sigma modulation apparatus. Ratio) can be obtained. In addition, if the input section has a differential configuration, it is possible to compensate for noise, change in characteristics, and the like of the input signal. In addition, by removing the influence of variations in the rise time and fall time of the feedback signal as an analog signal, the performance of the feedback signal, which greatly affects the performance of the entire system, can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a delta-sigma modulation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a delta-sigma modulation device according to a second embodiment of the present invention.

FIG. 3 is a first block diagram showing a conventional delta-sigma modulator.

FIG. 4 is a second block diagram showing a conventional delta-sigma modulator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Input terminal 103 1st subtracter 105 1st integrator 108 2nd subtracter 109 2nd integrator 110,210 Quantizer 111-115 1st-4th delay 116,216 Output terminal 201 Positive phase input terminal 202 Negative phase input terminal 203-204 First and second subtractors 205-206 First and second integrators 207-208 Third and fourth subtracters 209 Third integrator 211- 215 First to fifth delay units

Claims (2)

[Claims] 1. A first subtracter for subtracting a feedback signal from an input signal, a first integrator for integrating an output of the first subtractor, and a feedback signal from an output of the first integrator. A second subtractor for subtracting, a second integrator for integrating the output of the second subtractor, a quantizer for quantizing the output of the second integrator, and an output of the quantizer And a second delay unit that holds the output of the first delay unit at a rate of 2 Fs and then outputs a feedback signal to the first subtractor. A delay unit, a third delay unit that holds the output of the first delay unit at a rate of 2Fs, and then outputs a feedback signal to the second subtractor, and outputs the output of the first delay unit to a sampling frequency. And a fourth delayer for holding at the same rate Fs as the integration time constant T of the integrator. c is the same value as the sampling period Ts, and the output signal of the fourth delay device is used as an output. 2. A first subtracter for subtracting a feedback signal from a positive-phase input signal, and a first subtractor for integrating an output of the first subtractor.
An integrator, a second subtractor that subtracts a feedback signal whose sign is inverted from the negative-phase input signal, a second integrator that integrates an output of the second subtractor, and a second integrator that integrates the output of the first integrator. A third subtractor for subtracting an output of the second integrator from an output, a fourth subtractor for subtracting a feedback signal from an output of the third integrator, and an output of the fourth integrator. A quantizer for quantizing, a first delay unit for holding the output of the quantizer at a rate 2Fs which is twice the sampling frequency Fs, and a second delay unit for holding the output of the first delay unit at a rate of 2Fs. A second delay unit for outputting a feedback signal to the first subtractor; and a third delay unit for outputting a feedback signal to the second subtractor after holding the inverted output of the first delay unit at a rate of 2Fs. A delay unit and the fourth subtractor after holding the output of the first delay unit at a rate of 2Fs. And a fifth delay unit that holds the output of the first delay unit at the same rate Fs as the sampling frequency, and the integration time constant Tc of the integrator is the sampling period. A delta-sigma modulation device, which has the same value as Ts and outputs the output signal of the fifth delay unit.