JPH1141103A - D/a conversion circuit and communication terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent D/A conversion precision from falling by making the period of a data strobe signal for data input undesirably short. SOLUTION: An interpolation means 3 performs interpolation calculation for each input data by utilizing the duration of prescribed plural periods of a synchronizing clock signal CKS for the data interpolation, and data which are subjected to the interpolation are converted into an analog signal by D/A converting means 4 to 6. A resetting means 7 counts the number of periods of the synchronizing clock signal for a data interpolation operation for each period and generates a reset signal DADIGRES that resets the means 3 and the D/A converting means when the counted value does not reach a defined value corresponding to the duration which is needed for the interpolation processing in a new data input timing according to a data strobe signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A conversion circuit for performing D / A conversion by interpolating input data, and relates to a technique effective when applied to, for example, a mobile communication terminal device.

[0002]

2. Description of the Related Art A D / A conversion circuit for performing D / A conversion by interpolating demodulated digital data is provided in an analog front end section of a mobile communication terminal device. In this type of D / A conversion circuit, the interpolation circuit obtains interpolation data by performing an interpolation operation using a difference between previous and subsequent original data, and inserts interpolation data between the original data. For example, the interpolation circuit integrates the difference between the preceding and succeeding original data n times in synchronization with the synchronization clock signal for the interpolation operation, shifts the integration result right by n bits (1 / n), and converts the result to the right shifted data. The interpolation data is sequentially output based on the synchronization clock signal based on the interpolation data. The data output from the interpolation circuit is subjected to noise shaping by, for example, a delta-sigma modulation circuit, and then supplied to a D / A conversion unit such as a voltage potentiometer.

As an example of a document describing a D / A conversion circuit having an interpolation circuit, "Introduction to AD / DA Conversion Circuit" (published by Nikkan Kogyo Shimbun, November 28, 1991)
Pages 134 and 135.

[0004]

The present inventor has proposed the following D /
The A conversion circuit was studied. For example, it is assumed that the data strobe signal of the input data is 32 [KHz], and the data sampling frequency of the interpolation circuit and the delta-sigma modulation circuit is 2.4 [MHz]. In the above, the frequency of 2.4 [MHz] is 32 [KHz].
75 times of ± 1.2 to the data strobe signal
[MHz] jitter is allowed. At this time, considering the digital operation of the interpolation circuit and the like, it is desirable to make the number of integrations by the interpolation circuit a power of two. Therefore, the interpolation circuit synchronizes with the sampling clock signal (synchronization clock signal for interpolation operation) for each cycle of the data strobe signal, and calculates the difference between the preceding and succeeding input data by, for example,
Times integration, and shifts the integration result right by 6 bits (1/6
4) By doing so, interpolated data for interpolating between the original data at 1/64 gradation is generated, and this is subjected to D / A conversion.

However, if the cycle of the data strobe signal deviates greatly from the normal cycle, the above-mentioned 6 for interpolation is required.
Before the four integration operations are completed, the next data is input, the interpolation data takes an incorrect value with respect to the original data, and it is clarified that the D / A conversion accuracy is reduced. Was. The cycle of the data strobe signal is a signal synchronized with the clock signal generated by the clock pulse generator. As a situation where the cycle of the data strobe signal becomes shorter than the allowable range, the operation of the clock pulse generator becomes unstable immediately after the standby state of the communication terminal device is released, or an unexpected cause such as noise is caused. Conceivable.

An object of the present invention is to provide a D / A conversion circuit capable of preventing the D / A conversion accuracy from being lowered by undesirably shortening the period of a data strobe signal for data input, and a D / A conversion circuit. It is to provide a communication terminal device to which the D / A conversion circuit is applied.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, in the D / A conversion circuit (1), the frequency of the synchronous clock signal (CKS) for the data interpolation operation of the data interpolation means (3) is made higher than the frequency of the data strobe signal (IOEN) of the input data. The interpolating means performs an interpolating operation for each of the input data using a period of a plurality of predetermined cycles of the synchronous clock signal, and converts the interpolated data into D / A converting means (4, 5, 6) To convert to an analog signal. The D / A conversion circuit includes the D / A
Reset means (7) for resetting the conversion means and the interpolation means is provided. The reset means counts the number of cycles of the synchronous clock signal for the data interpolation operation by a counter (20) for each cycle of the data strobe signal, and at a new data input timing by the data strobe signal, the count value becomes A determination circuit (21) for determining a state in which a predetermined value equal to or longer than a value corresponding to a period required for the interpolation calculation is not reached.
When the determination is made in (1), a reset signal (DADIGRES) for resetting the interpolation means and the D / A conversion means is generated.

In the above means, for example, the data strobe signal of the input data is 32 [KHz], and the synchronous clock signal frequency (sampling frequency) for the operation of the interpolation means is 2.4 [MHz]. The frequency of 2.4 [MHz] is 32
It is 75 times [KHz]. At this time, considering the digital operation of the interpolation means and the like, the number of integrations by the interpolation means is 2
Therefore, the interpolation means performs, for each cycle of the data strobe signal, an integration operation of, for example, 64 times in synchronization with the sampling cycle for a difference between input data before and after, and shifts the result by 6 bits to the right. (1/64), and based on this, interpolation data for interpolating between the preceding and succeeding input data with 1/64 gradation is formed. The interpolation data is supplied to the D / A conversion means in synchronization with a synchronization clock signal having a frequency such as 2.4 [MHz]. The reset circuit counts the number of the sampling periods for each period of the data strobe signal, and the counted value is a predetermined value, for example, 70.
If the above value is not reached, in other words, if new data is input before the count value becomes 70 or more, the interpolation means and the D / A conversion means are reset. The resetting interpolator cancels the data in the middle of the interpolation calculation for the input data immediately before the new input data is input, and shifts to a new interpolation calculation for the new input data. Similarly, the internal state of the reset D / A conversion means is initialized, and the D / A conversion operation on the interpolation result of the new input data is enabled. As a result, when the cycle of the data strobe signal is undesirably shortened, the result of the integration operation that will cause an incorrect result with respect to the original data is discarded, and the D / A conversion accuracy is reduced by such an incorrect integration result. Can be prevented from decreasing.

The D / A conversion means includes a delta-sigma modulation circuit (4) for receiving the output of the interpolation means and performing noise shaping, and a decoding means (5) for decoding a feedback signal of the delta-sigma modulation circuit. And a D / A conversion analog circuit (6) for controlling a switch circuit in accordance with a decode signal output from the decode means to form an analog voltage signal.

The D / A conversion circuit can be arranged in an analog front end section of a communication terminal device. For example, the D / A conversion circuit of the analog front end unit receives data and a data strobe signal from a processing circuit such as a channel codec. The processing circuit and the D / A conversion circuit are supplied with a synchronous clock signal (CKS) from the clock pulse generator (32). That is, D
The original oscillation of the synchronous clock signal of the / A conversion circuit and the processing circuit is shared. According to this communication terminal device, the period of the data strobe signal is disturbed due to a transient period until the operation of the clock pulse generator is stabilized immediately after the standby state is released, or an unexpected cause such as noise. However, a decrease in D / A conversion accuracy can be prevented.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a D / D according to an example of the present invention.
A block diagram of the A conversion circuit is shown. D shown in FIG.
The / A conversion circuit 1 includes a serial / parallel conversion circuit 2, an interpolation circuit 3, a delta-sigma (ΔΣ) modulation circuit 4 as a digital filter, a decoder 5, a D / A conversion analog circuit 6, and a reset circuit 7. . PC
MIN is 16-bit input data supplied serially. The input data PCMIN is changed in synchronization with a clock signal IOCK of 2.4 [MHz]. IOEN is a data strobe signal, which has a frequency of, for example, 32 [KHz] and is a signal that indicates the input of the first bit of 16-bit input data by a pulse change. C
KS is the interpolation circuit 3, ΔΣ modulation circuit 4 and decoder 5
Is a clock signal representatively shown as an operation clock signal. This clock signal CKS is used as a sampling clock signal in the interpolation circuit 3 and the delta-sigma modulation circuit 4, and has a frequency of 2.4 [MHz]. CK96M
Is a clock signal having a frequency of 9.6 [MHz] selected as a clock signal having a higher frequency than the clock signal CKS. DIGRES is a system reset signal supplied from the outside. DADIGRES is a reset signal of the D / A conversion circuit 1.

The serial / parallel conversion circuit 2 converts the input data PCMIN into parallel. The interpolation circuit 3
A serial / serial /
The difference between the data before and after the data supplied from the parallel conversion circuit 2 is synchronized with the sampling clock signal CKS, for example, by 6
Integrate four times and shift right by 6 bits (1/64). Based on the selected data, interpolation data is sequentially calculated in synchronization with the sampling clock signal CKS and supplied to the ΔΣ modulation circuit 4.

The ΔΣ modulation circuit 4 is sequentially supplied from the interpolation circuit 3 in synchronization with the sampling clock signal CKS.
Noise shaping is performed on bit data. For example, the difference between the returned quantized signal and the input signal is integrated, and the integrated value is quantized and fed back. The lower the frequency component, the larger the feedback. This allows
A noise component such as a quantization error moves to a high frequency in frequency, so that a so-called noise shaping effect can be obtained.
This improves the S / N of the D / A conversion. The quantized feedback signal of the ΔΣ modulation circuit 4 has 6 bits and is supplied to the decoder 5.

The decoder 5 and the D / A conversion analog circuit 6 are not particularly limited.
/ A conversion format. For example, although not shown, a resistor circuit is arranged between the output of the operational amplifier receiving the reference voltage at the non-inverting input terminal and the ground of the circuit, and a feedback node of the resistor circuit is connected to the inverting input terminal of the operational amplifier. And a switch circuit for selectively taking out the divided voltage of the resistor circuit based on the level of the feedback node. The output of the switch circuit is output as an analog voltage signal via a voltage follower circuit or the like. The decoder 5 decodes the output of the ΔΣ modulation circuit 4 and forms a selection signal for selecting a switch of the switch circuit. As a result, an analog voltage signal having a voltage level corresponding to the input data PCMIN is formed.

As described above, data strobe signal IO
EN is 32 [KHz], and the data sampling frequency of the interpolation circuit 3 and the ΔΣ modulation circuit 4 is 2.4 [MHz] specified by the clock signal CKS. The frequency of 2.4 [MHz] is 32
It is 75 times [KHz]. At this time, considering the digital operation of the interpolation circuit 3 and the like, it is desirable to increase the number of integrations by the interpolation circuit 3 to a power of two.
Performs, for each cycle of the data strobe signal IOEN, an integration operation of, for example, 64 times in synchronization with the cycle of the sampling clock signal CKS, and shifts the difference by 6 bits to the right (1/64). . Based on this, interpolated data for interpolating between the input data with 1/64 gradation is formed sequentially in synchronization with the sampling clock signal CKS, and supplied to the ΔΣ modulation circuit 4. The reset circuit 7 counts the number of the sampling cycles for each cycle of the data strobe signal IOEN based on the sampling clock signal CKS, and when the count value does not reach a predetermined value, for example, 70 or more, in other words, When new data is input before the count value becomes 70 or more,
The serial / parallel conversion circuit 2, the interpolation circuit 3, ΔΣ
The modulation circuit 4 and the decoder 5 are connected to the reset signal DADIGR
Reset by ES.

FIG. 2 shows a specific example of the reset operation by the reset 7 circuit. Normal data strobe signal I
OEN is allowed to have a jitter of ± 1.2 [MHz].
The allowable range of this jitter is the sampling clock signal C
One cycle (one shot) of KS. When the count value of the sampling clock signal CKS is 69 or less, reset is instructed by the reset signal DADIGRES.

FIG. 3 shows an example of a specific logical configuration of the reset circuit 7. FIG. 4 shows an operation timing chart of the reset circuit 7 of FIG. In FIG. 3, 1
0 to 15 are D-type latches, 16 and 17 are AND gates, 18 and 19 are NOR gates, 20 is a 7-bit binary counter, 21 is an input CNTO of 1 ≦ CN
When TO <70, a determination circuit for setting the output signal CNTOPLS to a high level, and 22 is an inverter.

When the data strobe signal IOEN is changed to a high level (time t0 in FIG. 4), during this period, the D-type latch 10 latches the high level in synchronization with the rising edge of the clock signal CK96M (FIG. 4). Time t1
To t4). During this period, the change in the clock signal CNT_CK is suppressed, and as a result, the counter 20 maintains the value counted until immediately before the data strobe signal IOEN is changed. The D-type latch 14 receiving the output of the counter 20 at its input latches the input data in synchronization with the rising edge of the data strobe signal IOEN (at time t in FIG. 4).
1). The latched data CNTO is supplied to the determination circuit 21. The determination circuit 21 determines that the input CNTO is 1 ≦ CNTO.
It is determined whether <70. In the example of FIG.
Since the count value CNT latched at 1 is 70 or more, the output CNTOPLS of the determination circuit 21 maintains the low level. D-type latch 15 receiving output CNTOPLS as input
Performs a latch operation in synchronization with the falling edge of the clock signal CK96M. Since the external system reset signal DIGRES is a signal for instructing the reset operation at a low level and is at a high level, the NOR gate 19 Reset signal D output through
ADIGRES maintains a high level even after time t1 in FIG. 4 and until time t4. Thus, when the count value CNT is 70 or more, the interpolation circuit 3 and the ΔΣ modulation circuit 4 are not reset.

After the determination circuit 21 determines the latch data of the D-type latch 14, the counter 20 is reset at a time t2 in FIG. 4 by a counter reset signal CNTRES. That is, the clock signal C after the time t1 in FIG.
Since the serial two-stage D-type latches 11 and 12 latch the high-level signal IOENIN and the output of the D-type latch 13 maintain the low level in synchronization with the two falling edges of K96M. Output CNT of NOR gate 18
RES is set to low level, and the counter 20 is reset. When the clock signal CK96M falls three times from time t1, the D-type latch 13 also latches the high level signal IOENIN, so that the counter reset signal CNTRES is negated to low level at time t3 in FIG.

As described above, the determination operation by the determination circuit 21 and the reset operation of the counter 20 are completed in synchronization with the clock signal CK96M during the high level period of the data strobe signal IOEN. Therefore, the frequency of the clock signal CK96M is set to an appropriate frequency equal to or higher than 2.4 [MHz] of the sampling clock signal CKS. Therefore, when the data strobe signal IOEN is negated, the counter 20 starts a new counting operation from the initial value 0 in synchronization with CNT_CK.

Next, when the data strobe signal IOEN is changed to the high level (time t5 in FIG. 4), the D-type latch 10 latches the high level in synchronization with the rising edge of the clock signal CK96M in the same manner as described above. Times t6 to t9 in FIG. 4). During this period, the clock signal CNT_C
The change of K is suppressed, and as a result, the counter 20 maintains the counted value until immediately before the data strobe signal IOEN is changed. The D-type latch 14, which receives the output of the counter 20 at its input, latches the input data in synchronization with the rising edge of the data strobe signal IOEN (FIG. 4).
At time t6). The latched data CNTO is supplied to the determination circuit 21. The determination circuit 21 determines that the input CNTO is 1 ≦
It is determined whether CNTO <70. In the example of FIG. 4, since the count value CNT latched at the time t6 is less than 70, the output CNTOPLS of the determination circuit 21 is set to the high level. The D-type latch 15 receiving the output CNTOPLS as an input performs a latch operation in synchronization with the falling edge of the clock signal CK96M, and the external system reset signal DIGRES is negated to a high level. Is asserted at a low level during a period from time t6 to time t8 in FIG.

As described above, when the count value CNT is less than 70, the reset signal DADIGRES is asserted, and the interpolation circuit 3 and the ΔΣ modulation circuit 4 are reset. After a reset operation is instructed by the reset signal DADIGRES, the counter 20 is reset in exactly the same manner as described above, and the counter 20 is reset to CN in accordance with the next data input.
A new counting operation is started from the initial value 0 in synchronization with T_CK.

The reset operation by the reset signal DADIGRES is, in other words, when a new data input is instructed by the data strobe signal IOEN before the count value of the counter 20 reaches the predetermined value 70 or more. Therefore, the interpolating circuit 3 to which the reset is instructed by the reset signal DADIGRES cancels the data in the middle of the interpolation calculation for the input data immediately before the new input data is input, and performs the new interpolation calculation for the new input data. Can be migrated to.
Similarly, the reset ΔΣ modulation circuit 4 and decoder 5 are also initialized, and the D / A conversion operation on the interpolation calculation result of the new input data is enabled. As a result, when the cycle of the data strobe signal IOEN is undesirably shortened, the integration result that will cause an incorrect result with respect to the input data is discarded, and the D / A conversion accuracy is reduced by such incorrect data. It is possible to prevent the situation from lowering.

FIG. 5 is a block diagram showing an example of a mobile communication terminal to which the D / A conversion circuit 1 is applied. D /
The A-converter circuit (DAC) 1 is applied to an analog front-end unit (AFE) 30. The analog front-end unit 30 typically includes an A / D converter circuit (ADC) 31 and a clock pulse generator 32. ing. The output of the D / A conversion circuit 1 is provided to a speaker 33, and the A / D conversion circuit 31 is provided with an analog signal from a microphone.

The high frequency section (RF) 36 is a GMSK (Gaussian).
sian Filtered Minimum Shift Keying) or QPSK
(MOD) 3 that modulates a transmission signal using a modulation method such as (Quadrature Phase Shift Keying).
7, and amplifies it at a high frequency and outputs it from the antenna 39. The high frequency unit 36 detects a signal input from the antenna 39. The detected signal is demodulated by a demodulation circuit (DEM) 38.

The channel codec (CHC) 41 performs communication channel control or protocol processing. CPU ・
The DSP 40 includes a CPU (Central Processing Unit) and a DSP (Digital Signal Processor).
Digital signal processor), controls the entire mobile communication terminal device, and performs a filter operation and the like by digital signal processing. The modulation circuit 37 and the demodulation circuit 38 are coupled to, but not limited to, a channel codec 41. The D / A conversion circuit 1 and the A / D conversion circuit 31 are connected to a channel codec 41, although not particularly limited.

The data strobe signal IOEN, the clock signal IOCK, and the data PCMIN are supplied from the channel codec 41 to the D / A conversion circuit 1. Clock signals CKS and CK96M are applied from clock pulse generator 32 to D / A conversion circuit 1. The clock signal CKS is also supplied to the channel codec 40 and the CPU / DSP 40 as a synchronous clock signal for the operation in the example of FIG.

The mobile communication terminal is driven by a battery,
In the standby state, the operations of the clock pulse generator 32, the channel codec 41, and the like are stopped in order to reduce power consumption. When the standby state is released, it takes time until the operation of the clock pulse generator 32 is stabilized. When the received data is supplied to the D / A conversion circuit 1 in such a state, the cycle of the clock signal such as the data strobe signal IOEN may be undesirably shortened. Similarly, the cycle of the data strobe signal IOEN may be undesirably shortened under the influence of noise or the like. In such a case, the D / A conversion circuit 1 detects the state by itself and initializes the inside.
The initialization operation is completed after the next data input is instructed by the data strobe signal IOEN until the input of the next data is actually started. Therefore,
Discard only the data obtained by the interpolation operation that is incomplete due to the short period of the data strobe signal IOEN,
Processing of subsequent data can be continued. According to this mobile communication terminal device, the period of the data strobe signal IOEN is changed due to an unpredictable cause such as a transient period until the operation of the clock pulse generator is stabilized immediately after the standby state is released, or noise. Even if it is disturbed, it is possible to prevent a decrease in D / A conversion accuracy.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the frequencies of various clock signals are limited as described above, and can be appropriately determined according to the system to which the present invention is applied. Also, the number of integrations in the interpolation operation and the logical configuration of the reset circuit can be changed as appropriate.

[0033]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when the cycle of the data strobe signal is undesirably shortened, the D / A conversion circuit detects the state by itself and initializes the inside. The initialization operation is completed after the next data input is instructed by the data strobe signal until the input of the next data is actually started. Therefore, it is possible to discard only the data obtained by the interpolation operation that is incomplete due to the short period of the data strobe signal, and to continue the processing of the subsequent data. Therefore, it is possible to prevent a situation in which the D / A conversion accuracy is reduced due to an integration operation result that causes an incorrect result with respect to the original data. In addition, immediately after the standby state is released, the data strobe signal IOE is caused by an unexpected period such as a transient period until the operation of the clock pulse generator is stabilized or noise.
Even if the period of N is disturbed, it is possible to prevent a decrease in D / A conversion accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram of a D / A conversion circuit according to an example of the present invention.

FIG. 2 is an explanatory diagram showing a specific example of a reset operation instruction by a reset circuit.

FIG. 3 is a logic circuit diagram illustrating an example of a specific logic configuration of a reset circuit.

FIG. 4 is an operation timing chart of the reset circuit of FIG. 3;

FIG. 5 is a block diagram illustrating an example of a mobile communication terminal to which the D / A conversion circuit of FIG. 1 is applied;

[Explanation of symbols]

 Reference Signs List 1 D / A conversion circuit 2 Serial / parallel conversion circuit 3 Interpolation circuit 4 ΔΣ modulation circuit 5 Decoder 6 D / A conversion analog circuit 7 Reset circuit IOEN Data strobe signal PCMIN input data CKS sampling clock signal DADIGRES D / A conversion circuit Reset signal 30 Analog front end unit 36 High frequency unit

Claims (3)

[Claims] 1. A synchronous clock signal frequency for a data interpolation operation of a data interpolation means is made higher than a data strobe signal frequency of input data, and said interpolation means outputs, for each of said input data, a predetermined plurality of said synchronous clock signals. Interpolation operation is performed using the cycle, and the interpolated data is calculated as D /
A D / A conversion circuit for converting an analog signal into an analog signal by an A conversion means, comprising: reset means for resetting the D / A conversion means and the interpolation means, wherein the reset means is provided for each cycle of the data strobe signal. Counting the number of periods of the synchronous clock signal, and at a new data input timing by the data strobe signal, when the count value does not reach a prescribed value equal to or more than a predetermined value corresponding to a period required for the interpolation operation, the interpolation means and A D / A conversion circuit for generating a reset signal for resetting the D / A conversion means. 2. The digital-to-analog converter includes a delta-sigma modulation circuit that receives an output of an interpolation unit and performs noise shaping, a decoding unit that decodes a feedback signal of the delta-sigma modulation circuit, and the decoding unit. 2. A D / A conversion circuit according to claim 1, further comprising: a D / A conversion analog circuit that controls a switch circuit in accordance with a decode signal output from the control circuit to form an analog voltage signal. . 3. A D / A conversion circuit according to claim 1 or 2, and a processing circuit for supplying the data strobe signal and D / A conversion data to the D / A conversion circuit.
A communication terminal device comprising: a clock pulse generator that supplies a synchronous clock signal to the D / A conversion circuit and the processing circuit.