JPH1140683A - Semiconductor memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory with an MFIS(metal ferroelectric insulator semiconductor) transistor structure using a ferroelectric as a gate insulating film, which semiconductor memory permits a fine memory cell suitable for higher integration without processing damage to a channel part. SOLUTION: A source/drain diffusion layer 7 is formed of a stacked diffusion layer 3 consisting of polycrystalline silicon deposited on a substrate 1, and this stacked diffusion layer 3 is insulated by an oxide film 4 and a side wall insulating film 5 in a self-aligning manner. A groove is formed after the substrate in a channel part is exposed, and a ferroelectric film 8 is formed by interposing an anti-reflection film 6. The ferroelectric film 8 is processed on the insulating film 4 covering the stacked diffusion layer 3. An ion implantation layer 31 is of the same conductivity type as the diffusion layer 7. Thus, because the gate electrode 9 is processed on the insulating film, the processing damage to the gate edge of the channel part can be suppressed. The width of the groove to be the gate length can be produced with fine structure to be not larger than 0.1 μm and an extra-high integrated memory of a giga-bit class can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a non-destructive readable semiconductor memory device using a ferroelectric thin film as a gate insulating film of a field effect transistor, and a method of manufacturing the same. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Conventionally, metal-ferroelectric-semiconductor (MFS) transistors using a ferroelectric as a gate insulating film of a field effect transistor include, for example, IEE Transaction on Electron Devices, ED-21. roll,
No. 8, August 1974, pp. 499-504 (IEEE T
rans, Electron Devices, vol.ED-21, No.8, pp.499-50
4, Aug. 1974), and has a structure as shown in FIG. In FIG. 9, reference numeral 1 denotes a semiconductor substrate, 2 denotes an element isolation insulating film, 7 denotes a source / drain region, 8 denotes a ferroelectric film, and 9 denotes a gate electrode.

Taking a p-channel transistor as an example, when the polarization of the ferroelectric film 8 is directed toward the semiconductor substrate 1 as shown by an arrow in FIG. Therefore, even if a read pulse is applied to the gate electrode 9, the MFS transistor does not turn on. On the other hand, as shown in FIG. 2B, when a reverse voltage higher than the coercive electric field of the ferroelectric film 8 is applied to the gate electrode 9, the ferroelectric film 8
Is inverted, the channel portion is in an inverted state, and an inversion layer is formed. As a result, the MFS transistor is turned on. Therefore, like a flash memory or the like, it can be used as a memory element from which information can be read by turning on / off a transistor. In the case of an n-channel transistor, if a voltage is applied to the gate electrode so that the direction of polarization of the ferroelectric film 8 is opposite to that of the p-channel transistor, the on / off operation can be performed similarly. It is.

The structure of this memory element is such that one memory cell is used.
Since it can be composed of only MFS transistors, it is suitable for integration. This memory cell is also a non-volatile memory that can be written and read at high speed. When this memory cell is used, information can be read out in a non-destructive manner, so that rewriting at the time of reading out information is not required. Further, since the polarization of the memory cell composed of one MFS transistor is not inverted at the time of reading data, the characteristic of the ferroelectric substance is obtained by repeating the polarization inversion as in the case of the memory cell composed of one transistor and one ferroelectric capacitor. Does not deteriorate and the number of readings is not limited.

However, in the MFS transistor, since a direct interface between the ferroelectric and the semiconductor is used as a channel structure, carriers are injected at the interface, interdiffusion of materials at the interface, interface states and traps. A problem such as the formation of a film occurred, and good characteristics could not be obtained.

[0006] In order to solve these problems, for example, IEDM Technology Digest,
1994, pp. 7-16 (IEDM Tech. Dig., Pp.
7-16, 1994,), between the ferroelectric film 8 and the semiconductor substrate 1 as shown in FIG.
A metal-ferroelectric-insulator-semiconductor (MFIS) transistor structure containing one has been proposed.

According to the MFIS transistor structure,
When processing the laminated film of the ferroelectric film 8 / the reaction preventing film 101, there is a problem that the source / drain region 7 around the gate electrode is damaged due to processing and the transistor characteristics are remarkably deteriorated.

In order to solve this problem, as shown in FIG. 11, a method of forming and processing a ferroelectric film 8 after covering a source / drain region 7 of an MFIS transistor structure with a low dielectric constant film 111, Has been proposed. This manufacturing method is disclosed in JP-A-5-121760.

[0009]

However, the MF disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-121760.
According to the manufacturing method of the IS transistor structure, the source / drain region 7 and the channel region covered by the ferroelectric film 8 cannot be formed in a self-alignment manner, and thus are not suitable for high integration. In this manufacturing method, in order to solve the problem of misalignment, the low dielectric constant film 111 around the ferroelectric film 8 is removed by wet etching, and ion implantation is performed again to form a region 7a connected to the source / drain region 7. Form.

However, when a memory cell that can be used for a 256 Mbit to 1 Gigabit class highly integrated memory that requires a processing dimension of quarter micron or less is targeted, it is difficult to control the dimensions by processing using wet etching. Even if the size can be controlled, the width of the source / drain region must be at least as large as the minimum processing size in order to pattern the portion of the region 7a to be removed by wet etching, which is disadvantageous for high integration. . Further, there is a problem that the characteristics of the ferroelectric film 8 are significantly deteriorated by the activation heat treatment after the ion implantation.

An object of the present invention is to provide a highly integrated memory of 256 megabit to 1 gigabit class which does not cause processing damage to the source / drain regions around the gate electrode and requires a processing dimension of quarter micron or less. It is an object of the present invention to provide a usable semiconductor memory device having an MFIS transistor structure suitable for high integration and a method of manufacturing the same.

[0012]

The ferroelectric film is processed at a location away from the channel to avoid processing damage to the channel region. Specifically, as shown in FIG. 1, a structure in which a part of the diffusion layer is stacked on the semiconductor substrate 1 and the element isolation insulating film 2 is used, and the diffusion layer inside the substrate is formed by using the impurity diffusion therefrom. To form

The channel portion of the transistor is formed along the side wall and bottom surface of the groove inside the semiconductor substrate 1. That is, a channel portion is formed on the surface of the substrate where the gate electrode is in contact with the gate electrode via the gate insulating film in a normal MOS transistor, whereas the channel portion is formed on both the side and bottom surfaces of the groove in the MFIS transistor of the present invention. Is formed, the channel length becomes longer than the gate width.

Further, since the ferroelectric film has a structure in which the ferroelectric film is deposited via the reaction preventing film and is processed on the stacked diffusion layer, the channel portion is not damaged and the transistor characteristics are not affected.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention. In the structure shown in FIG. 1, reference numeral 1 denotes a p-type semiconductor substrate, 2 denotes an element isolation insulating film, 3 denotes a stacked diffusion layer, 4 denotes an oxide film serving as an interlayer insulating film, 5 denotes a sidewall insulating film, and 6 denotes a reaction. Prevention film, 7 is source /
An n-type impurity diffusion layer serving as a drain region, 8 is a ferroelectric film, 9 is a gate electrode, 10 is an interlayer insulating film, and 11 is a wiring.

By the way, when the element size of a normal MOSFET is reduced, the influence of the source / drain diffusion layer on the electric field in the channel portion becomes remarkable.
Problems such as a decrease in threshold voltage and a punch-through called a short channel effect occur. In order to suppress the short-channel effect, measures such as making the junction of the diffusion layer shallow and increasing the impurity concentration of the substrate have been taken. But,
If the junction of the diffusion layer is made shallow, the resistance of the diffusion layer increases and the performance deteriorates.

On the other hand, a stacked diffusion layer type MOS
It is known that the FET can reduce the diffusion layer resistance and, furthermore, the junction depth can be made substantially zero by combining with the trench type gate structure, which is effective in suppressing the short channel effect. ing.

Therefore, the semiconductor memory device of the present invention having the MFIS transistor structure shown in FIG. 1 is also effective in suppressing the short channel effect accompanying miniaturization, similarly to the stacked diffusion layer type MOSFET.

The MFIS transistor structure shown in FIG. 1 is self-aligned by the width of the trench whose gate length separates the stacked diffusion layer 3 and the thickness of the side wall insulating film 5 covering the side wall of the stacked diffusion layer 3. Therefore, a gate length smaller than the minimum processing size can be realized. If a high resolution technology such as a phase shift exposure method is used in the photolithography process, it is possible to process about 0.25 μm even if i-line is used as the light source wavelength, so that the thickness of the side wall insulating film 5 in the horizontal direction is reduced. If the thickness is 0.1 μm, miniaturization up to a gate length of 0.05 μm is possible.

Further, in the structure shown in FIG. 1, since the channel portion is formed inside the semiconductor substrate 1 along the bottom surface of the groove type gate electrode, the effective channel length is made larger than the gate length by making the groove deeper. Can also be longer. For this reason,
An MFIS transistor that operates stably even if the gate length is reduced can be realized. Therefore, the MFI according to the present invention
A semiconductor memory device having an S-transistor structure is suitable for realizing a gigabit class ultra-highly integrated memory.

FIG. 2 shows an embodiment of a method of manufacturing a semiconductor memory device having such an MFIS transistor structure.
This will be described with reference to FIG. First, an element isolation insulating film 2 is formed on a p-type semiconductor substrate 1 by using a selective oxide film growth method. Although not shown, boron was ion-implanted at about 1 × 10 ¹³ cm ⁻² using the silicon nitride film at the time of selective oxidation as a mask to improve element isolation characteristics.

Next, as shown in FIG. 2, the surface of the p-type semiconductor substrate 1 was exposed, and an amorphous silicon film 21 having a thickness of 100 nm was deposited by using a chemical vapor deposition method (CVD method). . At this time, the p-type semiconductor substrate 1 and the amorphous silicon film 21
Care must be taken to prevent the formation of a natural oxide film or the like at the interface of the substrate. An impurity having a conductivity different from that of the p-type semiconductor substrate 1 is ion-implanted into the amorphous silicon film 21.
However, it is assumed that the impurity ions remain in the amorphous silicon film 21 and do not reach the p-type semiconductor substrate 1. Specifically, phosphorus was ion-implanted under the conditions of 20 keV and 2 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 3, after an oxide film 4 is deposited at 450 ° C. by a normal pressure CVD method, the oxide film 4 and the amorphous silicon film 21 are used as source / drain regions of a transistor. To separate. Specifically, a desired resist pattern is formed using a photolithography method,
The oxide film 4 is processed by using this resist pattern as a mask, and after removing the resist pattern, the amorphous silicon film 21 is processed by using the oxide film 4 as a mask to form a stacked diffusion layer 3 serving as a source / drain diffusion source described later. Was formed.

Next, a thin oxide film (not shown) for protecting the surface is formed, and is stacked on the p-type semiconductor substrate 1 through this oxide film, and an impurity of the same conductivity type as that of the diffusion layer 3 is ion-implanted.
As shown in FIG. 4, an n-type ion implantation layer 31 is formed.
Specifically, arsenic was ion-implanted under the conditions of ¹⁵ keV and 1 × 10 ¹⁵ cm ⁻² . When this thin oxide film is formed, the stacked diffusion layer 3 made of amorphous silicon 21 is crystallized into polycrystalline silicon, and a part of the n-type impurity phosphorus implanted into the stacked diffusion layer 3 becomes p-type. Diffusion layer 7 that diffuses into semiconductor substrate 1 and becomes source / drain regions
Is formed. After removing the thin oxide film for protecting the surface, a silicon nitride film having a thickness of 100 nm is deposited, and the silicon nitride film is etched only by the film thickness using an anisotropic dry etching method to leave the silicon nitride film 5 only on the side walls. The stacked diffusion layers 3 were insulated consistently.

Next, as shown in FIG.
The p-type semiconductor substrate 1 exposed between them is dug down by an anisotropic dry etching method to form a groove-like channel region 51. The depth of the trench that digs down the p-type semiconductor substrate 1 is set to a position slightly deeper than the diffusion depth of the n-type ion-implanted layer 31 formed by ion implantation. Specifically, since the diffusion depth of arsenic when the silicon nitride film 5 was deposited was about 50 nm, the p-type semiconductor substrate 1 was dug down by 60 nm.
This groove is formed continuously on a mask pattern like a gate electrode pattern in a normal MOS transistor which forms a source / drain region in a self-aligned manner with respect to a gate electrode when viewed in a planar layout. Of course, it is formed so as to divide the source / drain region.

After the dry etching damage layer formed on the substrate surface during the anisotropic dry etching was removed by washing, a reaction preventing film 6 was deposited as shown in FIG. In this embodiment, cerium oxide (CeO ₂ ) having a thickness of 10 nm is deposited at a temperature of 900 ° C. by an evaporation method in an ultra-high vacuum of 10 ⁻⁹ Torr or less. CeO ₂ has good lattice matching with silicon, and has functions of preventing generation of interface states and traps, and preventing interdiffusion between ferroelectric and silicon. In the previous step of depositing the silicon nitride film 5 and the step of depositing the reaction prevention film 6, the crystallization of the stacked diffusion layer 3 made of amorphous silicon further progresses to polycrystalline silicon, and the amorphous silicon film 21 The source / drain region 7 formed by diffusing part of the implanted phosphorus into the p-type semiconductor substrate 1 becomes deeper.

Next, as shown in FIG. 7, a ferroelectric film 8 is deposited. The voltage applied to the gate electrode is divided by the ferroelectric film 8 and the reaction prevention film 6, so that a voltage sufficient to reverse the polarization of the ferroelectric film at a low voltage is applied. For this purpose, a ferroelectric film having a small relative dielectric constant is desirable. In this embodiment, lead lanthanum titanate having a thickness of 100 nm and a relative dielectric constant of about 200 was formed by a reactive evaporation method. Since the relative dielectric constant of CeO ₂ is about 26,
When the gate voltage is 5 V, about 2.8 is applied to the ferroelectric film.
Since a voltage of V is applied, the polarization can be sufficiently inverted.

Next, as shown in FIG. 8, a gate electrode 9 is deposited, and the gate electrode is formed in a desired pattern using photolithography and dry etching. In this embodiment, ruthenium is used as a gate electrode material. When the gate electrode 9 is processed using the resist 81 as a mask, the oxide film 4 on the stacked diffusion layer 3 serves as a base, so that the channel portion is not damaged.
Therefore, the transistor characteristics are not affected when the gate electrode is processed.

Finally, an interlayer insulating film 10 was deposited, contact holes were opened, and wirings 11 were formed to complete the semiconductor memory device of the present invention shown in FIG.

In this embodiment, lanthanum lead titanate is used as the ferroelectric film 8. However, lead titanate, lead zirconate titanate having a composition containing more titanium than zirconium, and zirconate titanate are used. Bismuth layered ferroelectric materials such as lanthanum lead or bismuth titanate may be used.

Although the silicon nitride film is used as the side wall insulating film 5 in the present embodiment, the silicon nitride film 5 and the ferroelectric film 8 are not formed because the step coverage of the reaction prevention film 6 is insufficient. When there is a possibility that a reaction occurs, titanium oxide or zirconium oxide is stacked and used as the sidewall reaction preventing film 121 between the sidewall insulating film 5 and the reaction preventing film 6 as shown in FIG. It is possible to improve the performance. When the resistance of the stacked diffusion layer 3 is to be reduced, the silicide film 122 is deposited immediately after the deposition of the amorphous silicon film to be the stacked diffusion layer 3. By performing ion implantation through the silicide film 122, favorable results can be obtained. 12, the same components as those in FIG. 1 are denoted by the same reference numerals, and the detailed description thereof will be omitted.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention. Of course.

[0034]

As is apparent from the above-described embodiments of the present invention, according to the method of manufacturing a semiconductor memory device according to the present invention, damage to the periphery of a transistor channel region due to dry etching of a ferroelectric film is prevented. Can be suppressed,
A ferroelectric nonvolatile memory having an MFIS transistor structure can be manufactured without deteriorating transistor characteristics.

The structure of the semiconductor memory device according to the present invention can be miniaturized to a gate length of about 0.1 μm.
A gigabit class ultra-highly integrated memory can be realized.

When the semiconductor memory device according to the present invention is used as a memory cell, not only a highly integrated ferroelectric nonvolatile memory can be realized, but also a high-density integrated memory of these memory cells and a logic LSI on the same chip. Functional LSI
Also, a field programmable logic LSI whose wiring can be changed by a ferroelectric nonvolatile memory can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a cross-sectional view showing one embodiment of a method for manufacturing a semiconductor memory device according to the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing a manufacturing step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step subsequent to FIG. 4;

FIG. 6 is a sectional view showing a manufacturing step subsequent to FIG. 5;

FIG. 7 is a sectional view showing a manufacturing step subsequent to FIG. 6;

FIG. 8 is a cross-sectional view showing a manufacturing process subsequent to FIG. 7;

FIG. 9 is a sectional view showing a conventional example of a semiconductor memory device using a ferroelectric film as a gate insulating film.

FIG. 10 is a cross-sectional view showing another conventional example of a semiconductor memory device using a ferroelectric film as a gate insulating film.

FIG. 11 is a cross-sectional view showing another conventional example of a semiconductor memory device using a ferroelectric film as a gate insulating film.

FIG. 12 is a cross-sectional view showing another embodiment of the semiconductor memory device according to the present invention.

FIG. 13 is a sectional view for explaining the operation of the ferroelectric gate field effect transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate, 2 element isolation insulating film, 3 stacked diffusion layer, 4 interlayer insulating film, 5 side wall insulating film (silicon nitride film), 6 reaction prevention film, 7 impurity diffusion layer (source /
Drain region), 8: ferroelectric film, 9: gate electrode, 1
0 ... interlayer insulating film, 11 ... wiring, 21 ... amorphous silicon film, 31 ... ion implantation layer, 51 ... channel region, 81 ...
Resist: 101: gate insulating film; 111: low dielectric constant film; 121: side wall reaction preventing film; 122: silicide (metal silicide).

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/10 451 27/108 21/8242 29/78

Claims (8)

[Claims] A second conductive type semiconductor region formed at predetermined intervals on a first conductive type semiconductor substrate having an element isolation region; and a reaction prevention film on the semiconductor substrate between the second conductive type semiconductor regions. And a gate electrode via a laminated film of a ferroelectric film,
In a semiconductor memory device for controlling a current flowing between semiconductor regions of the second conductivity type according to a polarization direction of a ferroelectric film generated by a voltage applied to the gate electrode, the semiconductor regions of the second conductivity type are stacked on a semiconductor substrate. A diffusion region formed in the semiconductor substrate using the second conductivity type semiconductor region as a diffusion source and a second conductivity type ion implantation region below the sidewall insulating film as a source / drain region; The side wall insulating film covering the side wall is insulated from the laminated film of the reaction preventing film and the ferroelectric film, and the ferroelectric film is in contact with the substrate surface portion not covered by the side wall insulating film via the reaction preventing film, and the gate electrode A semiconductor memory device extending over an interlayer insulating film covering the semiconductor region of the second conductivity type. 2. The ferroelectric film according to claim 1, wherein the ferroelectric film is any one of lead titanate, lead lanthanum titanate, lead zirconate titanate, lead lanthanum zirconate titanate, and a bismuth layered ferroelectric such as bismuth titanate. 2. The semiconductor memory device according to claim 1, comprising: 3. The semiconductor memory device according to claim 1, wherein said reaction preventing film is made of cerium oxide. 4. The semiconductor device according to claim 1, wherein the sidewall insulating film is one of a silicon nitride film, a stacked film of a silicon nitride film and titanium oxide, or a stacked film of a silicon nitride film and zirconium oxide. 13. The semiconductor memory device according to item 9. 5. The semiconductor memory device according to claim 1, wherein said semiconductor region of the second conductivity type is a laminated film of a polycrystalline silicon film and a metal silicide. 6. The semiconductor memory device according to claim 1, wherein said ion implantation layer is an arsenic ion implantation layer. 7. A reaction preventing film formed on a semiconductor substrate of a second conductivity type formed at predetermined intervals on a semiconductor substrate of a first conductivity type having an element isolation region and a semiconductor substrate between the semiconductor regions of the second conductivity type. And a gate electrode via a laminated film of a ferroelectric film,
In a method of manufacturing a semiconductor memory device for controlling a current flowing between semiconductor regions of a second conductivity type according to a polarization direction of a ferroelectric film generated by a voltage applied to a gate electrode, an amorphous semiconductor of a second conductivity type is formed on a semiconductor substrate. Depositing a first stacked film of a quality semiconductor and an insulating film; separating the first stacked film at predetermined intervals to form a second conductivity type semiconductor region;
A step of covering a side wall of the first laminated film with an insulating film;
Forming a conductive type impurity region; etching a semiconductor substrate not covered with the sidewall insulating film to separate a second conductive type impurity diffusion region to form a groove-shaped region; Depositing a second laminated film comprising a reaction prevention film, a ferroelectric film, and a gate electrode on the portion;
Processing the laminated film of the above on an interlayer insulating film covering the semiconductor region of the second conductivity type. 8. The second conductivity type amorphous semiconductor is an amorphous silicon film containing phosphorus as an impurity, and the second conductivity type impurity region is a region formed by arsenic ion implantation. A method for manufacturing a semiconductor memory device according to claim 7.