JPH1140680A - Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily, flexibly and quickly cope with the specification change by using connection holes for feeding a specified potential to specified conductivity type semiconductor regions as a connection hole pattern for feeding a specified potential to electrode patterns against soft-error. SOLUTION: A pattern of connection holes 23a for leading regions 3 is used as a pattern of connection holes 23b for plate electrodes 18. If the pattern for the electrodes 18 is required, it will suffice to lay only this pattern on a layout plane, thus eliminating the need of correcting the layout of the holes 23a. If the electrode 18 is not required, it will suffice to remove the plate electrode pattern, without correcting others. If the structure change occurs between the case the plate electrodes are provided and the case the plate electrodes are not provided, this change can be coped with whether providing or not providing the plate electrodes in the design stage, thereby facilitating the change work.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a technology of the semiconductor integrated circuit device, and more particularly to a method effectively applied to a manufacturing technology of a semiconductor integrated circuit device having an SRAM (Static Random Access Memory). It is about technology.

[0002]

2. Description of the Related Art An SRAM is a memory that uses a flip-flop circuit as a storage element of a memory cell and stores each of its bistable states in correspondence with information "1" and "0".

This SRAM includes a DRAM (Dynamic Ra).
Unlike an ndom access memory, a refresh operation is not required, and it is easy to use. This is because the use of a flip-flop circuit as a storage element allows the storage node to retain the stored contents, as long as the power supply voltage continues to be supplied, even if there is a leak current at the storage node, the leakage current is supplied from the power supply through the load element. Because you can continue.

This flip-flop circuit comprises two inverter circuits, the output of one inverter circuit being electrically connected to the input of the other inverter circuit, and the output of the other inverter circuit being the output of one inverter circuit. It is configured to be electrically connected to the input. Each inverter circuit has a driving transistor that contributes to storage of information and a load element that supplies a power supply voltage to the driving transistor.

The flip-flop circuit is disposed between a pair of two data lines, and a transfer transistor is interposed between the flip-flop circuit and each data line. . The transfer transistor is a switching element that electrically connects and insulates the flip-flop circuit and the data line.

[0006] Such SRAM memory cells include a CMOS type memory cell and a high resistance load type memory cell due to the difference in load element in the inverter circuit of the memory cell.

A CMOS type memory cell has a load element of p
Channel MOS / FET (Metal Oxide Semiconduc)
tor Field Effect Transistor) and the lowest power consumption. However, a p-channel type MOS.FET and an n-channel type MOS.FET must be mixed in a memory cell, and element isolation is required.

In order to reduce the memory cell area,
Even in a CMOS type memory cell, an n-channel type MOS • FET constituting a driving transistor is
There is also a so-called TFT (Thin Film Transistor) structure in which two polysilicon layers are provided and a p-channel type MOS • FET for a load element is formed by the polysilicon layers.

On the other hand, a memory cell of a high resistance load type uses a polysilicon resistor which is not doped with impurities or is slightly doped, as a load element. In this case, the area occupied by the resistor is small, and the resistor can be formed on the upper layer of the driving transistor or the like, so that the memory cell area can be minimized. Therefore, this high resistance load type is the mainstream of SRAM memory cells because it is most easily increased in capacity.

By the way, since an SRAM uses a flip-flop circuit as a storage element of a memory cell, it has a structure that is more resistant to soft errors due to α rays than a DRAM (Dynamic Random Access Memory) or the like.

However, as the memory cell area is reduced in order to increase the capacity and speed of the SRAM and the operating voltage is reduced in order to reduce the power consumption of the system, soft error resistance due to α-rays is decreasing. In some cases, a measure for improving soft error resistance due to α rays may be required in the SRAM.

The soft error caused by α-rays is caused by the fact that α-rays (He nuclei) contained in cosmic rays or α-rays emitted from radioactive atoms contained in a resin or the like of an LSI package are incident on a memory cell. Is a phenomenon that destroys

In order to improve the soft error resistance due to α rays, for example, it is effective to increase the capacity of the storage node of the memory cell. Therefore, in the SRAM, the memory cell is placed above the load element of the memory cell. By providing a plate electrode fixed at a predetermined potential so as to cover the capacitor, a capacitance element is formed between the plate electrode and a constituent part of the memory cell to increase the capacitance of the storage node, and α
We try to prevent the destruction of information due to lines.

Such a structure is basically the same regardless of whether the memory cell is the CMOS type or the high resistance load type. However, in the case of the high load resistance type, the GND potential is supplied to the plate electrode, whereas in the case of the CMOS type memory cell, the power supply voltage on the high potential side is supplied to the plate electrode. This is because the load element of the CMOS type memory cell is composed of a p-channel type MOS-FET, and when a GND potential is supplied to the plate electrode, the p-channel type MOS-FET is always turned on, which causes a problem. This is because it occurs.

The SRAM is described in, for example, Nikkan Kogyo Shimbun, September 29, 1987, “CMOS Device Handbook” P425-P440.
This document describes the memory cell structure, basic operation, and countermeasures against soft errors of a CMOS SRAM.

[0016]

However, the above-mentioned S
The present inventors have found the following problems in the RAM technology.

That is, in the SRAM, a case where a plate electrode is required as a countermeasure for the above-described soft error is provided.
Although it may not be particularly necessary, in the design stage of the SRAM, when the change is made, depending on whether the plate electrode is provided or not, a connection hole serving as a passage for supplying a predetermined potential to the plate electrode is provided. Since the arrangement positions are different, a correction work for the change is complicated, and the work is a troublesome work requiring time and labor.

An object of the present invention is to provide a semiconductor integrated circuit device having an SRAM in which the structure is changed between a case where an electrode pattern for soft error countermeasures is provided and a case where it is not provided. It is an object of the present invention to provide a technology capable of responding flexibly and promptly.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0020]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to a method of manufacturing a semiconductor integrated circuit device of the present invention, each of a plurality of SRAM cells provided on a semiconductor region of a predetermined conductivity type above a semiconductor substrate is provided on the semiconductor region of a predetermined conductivity type. Two drive transistors forming a memory element, two transfer transistors provided on the semiconductor region of the predetermined conductivity type to form a switching element, and provided on the drive transistor and the transfer transistor A method of manufacturing a semiconductor integrated circuit device comprising a load resistance element formed by a conductive film, wherein an electrode pattern for soft error countermeasures is provided on an upper layer of the load resistance element so as to cover an SRAM cell. In the design stage, at least a part of the electrode pattern supplies a predetermined potential to the semiconductor region of the predetermined conductivity type. And a step of arranging a connection hole pattern to be a path for supplying a predetermined potential to the semiconductor region of the predetermined conductivity type. And a step of using a connection hole pattern arranged in a part of the electrode pattern as a connection hole pattern serving as a passage for supplying a predetermined potential to the electrode pattern.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG. 1, and FIG. 3 is a semiconductor integrated circuit device of FIG. FIG. 4 is a sectional view of a main part of a memory cell region and a well power supply region of the semiconductor integrated circuit device of FIG. 1, and FIG.
6 is a plan view of a main part of a well power supply region of the semiconductor integrated circuit device of FIG. 1, FIGS. 6 and 7 are cross-sectional views of a main part showing a modification of the well power supply region, and FIGS. 8 and 9 are semiconductor integrated circuit devices of FIG. FIG. 4 is an explanatory diagram for describing a design process of FIG.

In this embodiment, a case where the present invention is applied to, for example, an SRAM will be described. That SR
FIG. 1 shows an overall plan view of the AM chip.

The SRAM chip 1 is made of, for example, silicon (S
i) A rectangular piece made of a single crystal is used as a substrate. On the main surface of the SRAM chip 1, for example, four memory cell regions M are arranged so as to divide the main surface of the SRAM chip 1 into four equal parts.

In each memory cell region M, a plurality of sub-memory cell regions Ms are arranged side by side along the longitudinal direction of the memory cell region M. In each sub-memory cell area Ms, a plurality of memory cells (SRAM cells) are regularly arranged in the vertical and horizontal directions in the area. Note that, here, for example, two sub-memory cell regions Ms form one set. FIG. 2 shows the set of sub-memory areas Ms.

One set of sub-memory cell regions Ms is arranged in a p-well (a semiconductor region of a predetermined conductivity type) 2. This p-well 2 has a set of sub-memory cell regions Ms
Each p well 2 is doped with, for example, a p-type impurity such as boron.

The set of sub memory cell regions Ms
, A lead-out region 3 is arranged so as to surround it. The extraction region 3 is formed above the p-well 2 as described later, and serves as a power supply region for supplying, for example, a ground potential (for example, 0 V) to the p-well 2. For example, p-type impurity such as boron is introduced into the extraction region 3 at a higher concentration than the p-well 2.

Next, FIG. 3 shows an equivalent circuit diagram of a memory cell in the SRAM of the present embodiment.

As the memory cell MC, for example, a memory cell of a high resistance load type is employed. The memory cell MC is arranged near the intersection of a pair of complementary data lines DL1, DL2 and a word line WL, and has a pair of driving circuits. MOSFETs Qd1 and Qd2, a pair of load resistors R1 and R2, and a pair of transfer MOSFETs Qt
1, Qt2. It should be noted that a pair of complementary data lines DL1 and DL2 are configured to flow signals inverted from each other.

The pair of driving MOS-FETs Qd1, Q
d2 and the pair of load resistors R1 and R2 constitute a flip-flop circuit. This flip-flop circuit
A storage element for storing 1-bit information ("1" or "0"). One end (on the load resistors R1 and R2 side) is electrically connected to the high-potential power supply Vcc, and the other end (for driving). MOS
The FETs Qd1 and Qd2) are electrically connected to the ground power supply GND. The voltage of the power supply Vcc is, for example, 3.3 V
For example, the voltage of the ground power supply GND is, for example, 0V.

Further, a pair of transfer MOS-FETs Qt1,
Qt2 connects the flip-flop circuit to the data lines DL1 and DL2.
These are switching elements for electrically connecting or insulating the data lines, and are interposed between the input / output terminals (storage nodes A and B) of the flip-flop circuit and the data lines DL1 and DL2, respectively. Note that a pair of transfer MOS / FE
Gate electrodes of TQt1 and Qt2 are electrically connected to a word line WL.

Next, the memory cell MC and the p-well power supply region will be described with reference to FIGS. FIG. 5 is a plan view of a main part of the p-well power supply region, and a cross-sectional view on the right side of FIG. 4 is a cross-sectional view taken along the line IVS-IVS in FIG.

The semiconductor substrate 1s is made of, for example, a p-type Si single crystal. A deep n-well 4 is formed at a predetermined depth from the main surface of the semiconductor substrate 1s, and the above-described p-well 2 is formed in an upper layer in the region of the deep n-well 4.

The deep n-well 4 has, for example, phosphorus or arsenic (As) as an n-type impurity introduced therein, and has a function of electrically separating the semiconductor substrate 1 s from the p-well 2.

A field insulating film 5 is formed in an isolation region on the main surface of the semiconductor substrate 1s. This field insulating film 5 is made of, for example, silicon dioxide (SiO 2).
₂ )

Here, the sectional structure of the memory cell MC will be described first. In the active region of the p well 2 surrounded by the field insulating film 5 in the formation region of the memory cell MC, the above-described driving MOSFETs Qd1 and Qd2 (see FIG. 3) and the transfer MOSFETs Qt1 and Qt2 (see FIG. 3) Reference) is formed.

The structures of the driving MOS-FETs Qd1, d2 are the same, and the transfer MOS-FETs Qt1, Qt1,
Since the structure of Qt2 is the same, FIG.
TQd2 and transfer MOSFET Qt1 are shown as representatives, and the structure of the MOSFET will be described.

The driving MOSFET Qd2 has a gate insulating film 6, a gate electrode 7, a source region and a drain region. The gate insulating film 6 is made of, for example, SiO ₂ or the like. The gate electrode 7 is made of a polysilicon film as a first-layer conductive material, and for example, phosphorus or As of an n-type impurity is introduced into the polysilicon film in order to reduce its resistance. I have.

An insulating film 8a is deposited on the upper surface of the gate electrode 7. This insulating film 8a is made of, for example, SiO ₂ or the like. Further, sidewalls 9 are formed on side surfaces of the gate electrode 7 and the insulating film 8a. This sidewall 9 is made of, for example, SiO ₂ or the like.

The source region and the drain region of the driving MOSFET Qd2 have a double drain structure of a low impurity concentration n- type semiconductor region 10a and a high impurity concentration n ^{+ type} semiconductor region 10b.

The transfer MOSFET Qt1 has a gate insulating film 11, a gate electrode 12, a source region and a drain region. The gate insulating film 11 is made of, for example, SiO ₂
Etc.

[0043] The gate electrode 12, the silicide film 12b made of a polysilicon film 12a which is a second layer of conductive material, such as tungsten silicide (WSi _X), etc.
The lower polysilicon film is doped with, for example, an n-type impurity such as phosphorus or As in order to reduce its resistance. This gate electrode 12 is also a part of the word line WL.

On the upper surface of the gate electrode 7, an insulating film 8b is deposited. This insulating film 8b is made of, for example, SiO ₂ or the like. Further, sidewalls 13 are formed on side surfaces of the gate electrode 12 and the insulating film 8b. The sidewall 13 is made of, for example, SiO ₂ or the like.

The source and drain regions of the transfer MOS · FETQt1 is a low impurity concentration n ^- LD with type semiconductor region 14 and the heavily doped n ⁺ type semiconductor region 10b
It has a D (Lightly Doped Drain) structure.

The source region (n ^{+ type} semiconductor region 10b) of the transfer MOSFET Qt1 is connected to the drive MOSFET FE.
It is formed integrally with the drain region of TQd1 (see FIG. 3), and the source region of the transfer MOSFET Qt2 (see FIG. 3) is the drain region (n
+ -Type semiconductor region 10b).

Such a driving MOS-FET Qd1, Q
d2 (see FIG. 3) and transfer MOSFETs Qt1, Qt2
(See FIG. 3) is an insulating film 8c made of, for example, SiO ₂ or the like.
Covered by

A ground wiring 15 is electrically connected to the source region (n ^{+ type} semiconductor region 10b) of the driving MOSFET Qd2 through a connection hole formed in the insulating film 8c or the like. This ground wiring 15 is formed of a polysilicon film 15.
on a made of, for example WSi _x, etc. silicide film 15b
Is deposited on the lower polysilicon film 15a.
In order to reduce the resistance value, for example, phosphorus or As as an n-type impurity is introduced.

The data line connection wiring 16 is electrically connected to the drain region (n ^{+ type} semiconductor region 10b) of the transfer MOSFET Qt1. The data line connection wiring 16 is formed on the polysilicon film 16a by, for example, W
Si _x such silicide film 16b is being deposited consisting of, the underlying polysilicon layer 16a, in order to reduce its resistance, phosphorus or As, for example, n-type impurity has been introduced.

The ground wiring 15 and the data line connection wiring 16 are covered with an insulating film 8d deposited on the semiconductor substrate 1s. The insulating film 8d is made of, for example, SiO ₂ or the like.
2 is formed. Since the structures of the load resistors R1 and R2 (see FIG. 3) are the same, the structure of the load resistor R1 is shown in FIG.

The load resistor R1 is made of, for example, a polysilicon film 17. The polysilicon film 17 has, for example, a predetermined amount of an n-type impurity such as phosphorus or phosphorus in order to make the resistance of the load resistor R1 a desired value. As has been introduced.

The load resistance R1 is determined by the insulating films 8a, 8c,
Transfer MOS-FET through connection hole drilled in 8d
It is electrically connected to the source region (n ^{+ type} semiconductor region 10b) of Qt1 and the gate electrode 7 of the driving MOSFET Qd2.

The load resistances R1 and R2 are formed on the insulating film 8d.
An insulating layer 8e is deposited so as to cover (see FIG. 3), and a plate electrode (electrode pattern) 18 is formed on the insulating film 8e by patterning.

The insulating film 8e is composed of, for example, a laminated film of a SiO ₂ film and a silicon nitride film, and is caused by α-rays by the polysilicon film 17 for load resistance, the insulating film 8e, and the plate electrode 18. A capacitive element for soft error countermeasures is formed.

The plate electrode 18 is made of, for example, a polysilicon film, and for example, phosphorus or As of an n-type impurity is introduced into the polysilicon film in order to reduce the resistance value. A ground potential (for example, 0 V) is supplied to the plate electrode 18.

On the upper surface of the insulating film 8e, for example, BPSG
(Boro Phospho Silicate Glass) or the like, and an interlayer insulating film 19a made of, for example,
8 are coated.

The data line DL is formed on the upper surface of the interlayer insulating film 19a.
1 is patterned. This data line DL1 is
For example, it is electrically connected to the data line connection wiring 16 through a buried conductor film 21 made of aluminum (Al), an Al alloy or a laminated film of an Al film and a titanium-based conductor film and buried in the connection hole 20. ing.

That is, the data line DL1 is electrically connected to the drain region (the n ^{+ type} semiconductor region 10b) of the transfer MOSFET Qt1 via the data line connection wiring 16. The buried conductor film 21 is formed, for example, by depositing a tungsten film on a tungsten film or a titanium-based conductor film.

An interlayer insulating film 19b is deposited on the upper surface of the interlayer insulating film 19a.
L1 is coated. The interlayer insulating film 19b is made of, for example, SiO ₂ or the like, and has a second layer wiring 22
Are patterned.

The second layer wiring 22 is made of, for example, Al, an Al alloy or a laminated film of an Al film and a titanium-based conductor film. On the upper surface of the interlayer insulating film 19b, for example, a surface protection film composed of a laminated film of a SiO ₂ film and a silicon nitride film is deposited, and the second-layer wiring 22 is thereby covered.
Its illustration is omitted.

Next, the cross section and plan structure of the p-well power supply region S will be described with reference to FIGS. In the p-well power supply region S, the above-described lead region 3 is formed in the active region of the p-well 2 surrounded by the field insulating film 5.

The lead region 3 is electrically connected to a ground wiring (not shown) through a connection hole 23a shown in FIG. 5, and is grounded to the p-well 2 via the lead region 3 from the ground line. A potential (for example, 0 V) is supplied.

In the present embodiment, a part of the plate electrode 18 for countermeasure against α-ray soft error is protruded in the p-well power supply region S so as to overlap the drawing region 3 in a planar manner. A pattern of a connection hole 23b serving as a passage for supplying a ground potential (for example, 0 V) to the plate electrode 18 is arranged in 18a.

The connection hole 23b and the connection hole 23a
Are arranged at predetermined intervals on a straight line in the extension direction on the extraction region 3. That is,
The pattern of the connection holes 23b for the plate electrode 18 is as follows.
When the plate electrode 18 is not provided, the extraction region 3
Is arranged so that it can be used as it is as a pattern of the connection holes 23a for use. Therefore, as will be described later, even if a change occurs between the case where the plate electrode 18 is provided and the case where the plate electrode 18 is not provided, the design change is easy.

The connection hole 23b for the plate electrode 18
Is provided on the lead-out area 3 and the connection holes 23a and 23b for two different components are provided for one area as compared with the case where the connection holes 23a and 23b are provided at different places. Since the use area of the connection holes 23a and 23b can be reduced, it is possible to promote downsizing of the SRAM chip.

In the cross section, as shown in FIG. 4, the connection hole 23b extends from the main surface of the interlayer insulating film 19a to the plate electrode 18a.
And the insulating film 8 under the plate electrode 18
It is perforated until it reaches the middle position of. The insulating film 8
Indicates an insulating film including the insulating films 8a to 8d described above.

The connection hole 23b is formed, for example, in the connection hole 2 described above.
Drilled at the same time as 0. In the present embodiment,
Since the plate electrode 18 is disposed on the extraction region 3 to which the same potential is supplied, no problem occurs even if the connection hole 23b reaches the extraction region 3 due to overetching. That is, the restriction on the depth at the time of drilling the connection hole 23b can be relaxed.
The formation process of b can be facilitated.

A buried conductor film 24 is buried in the connection hole 23a. The buried conductor film 24 is formed simultaneously with the formation of the buried conductor film 21 described above.
The electrode 3b is electrically connected to the plate electrode 18 through an exposed portion of the plate electrode 18 exposed from the inner wall surface.

The buried conductor film 24 has an upper part in contact with a ground wiring 25 on the interlayer insulating film 19a and is electrically connected thereto. The ground wiring 25 is patterned at the same time as the data line DL1, and is connected to the plate electrode 18 through the buried conductor film 24 at a ground potential (for example, 0 V).
V).

Further, since the same ground potential (for example, 0 V) is supplied to the extraction region 3 and the plate electrode 18 as described above, the connection hole 23b exposes the upper surface of the extraction region 3 as shown in FIG. It may be perforated at a depth up to In this case, the grounding wiring 25 is
4, it is electrically connected to both the plate electrode 18 and the extraction region 3.

Further, as shown in FIG. 7, the connection hole 23b may be formed at a depth until the upper surface of the protruding region 18a of the plate electrode 18 is exposed. In this case, the ground wiring 25 is electrically connected to the plate electrode 18 through the buried conductor film 24.

Next, a process of designing a pattern in such a p-well power supply region S will be described with reference to FIGS. 8 and 9, the X axis (coordinates x1 to x1) is used.
x6) and the Y axis (coordinates y1 to y9) indicate the position of the pattern.

FIG. 8 schematically shows a state in which the pattern of the p-well 2, the pattern of the extraction region 3, and the pattern of the connection hole 23a are arranged. This connection hole 23
The pattern a is a connection hole pattern for the lead-out area 3, which is arranged at equal intervals on a straight line along the extending direction of the draw-out area 3.

Here, when it is necessary to provide a pattern of a plate electrode for countermeasures against α-ray soft errors, as shown in FIG. Place a pattern.

At this time, in the present embodiment, the pattern of the connection holes 23a arranged in the protruding region 18a of the plate electrode 18 among the patterns of the connection holes 23a in FIG. It is used as a pattern of the holes 23b.

That is, in the present embodiment, when the pattern of the plate electrode 18 is required, only the pattern of the plate electrode 18 needs to be arranged on the layout plane, and the arrangement of the connection holes 23a needs to be corrected. There is no. Conversely, if the plate electrode 18 is not required, the plate electrode 18
All you have to do is remove the pattern and no other corrections are required. Therefore, even if a change occurs between the case where the plate electrode 18 is provided and the case where the plate electrode 18 is not provided, it is easy to change the design.

As described above, according to the present embodiment, the following effects can be obtained.

(1) By using the pattern of the connection holes 23a for the extraction region 3 as the pattern of the connection holes 23b for the plate electrode 18, the structure is changed between the case where the plate electrode 18 is provided and the case where the plate electrode 18 is not provided. Even if the above occurs, it is possible to respond to the change only by arranging or not arranging the plate electrode 18 in the design stage, so that the change operation can be facilitated and the change can be flexibly performed. It is possible to respond quickly.

(2) According to the above (1), the change design time of the SRAM chip 1 can be shortened.
Shorter delivery time of the M chip 1 can be promoted.

(3) The pattern of the connection holes 23a for the lead region 3 is used as the pattern of the connection holes 23b for the plate electrode 18, and the connection holes 23a for the two different components are used.
By providing the pattern of 23b also in one area, the use area of the connection holes 23a and 23b can be reduced as compared with the case where the respective connection holes 23a and 23b are provided in different places. It is possible to promote downsizing of the SRAM chip 1.

(4) The pattern of the connection hole 23b for the plate electrode 18 is changed to the extraction region 3 to which the same potential is supplied.
By arranging the connection hole 23b above, there is no problem even if the connection hole 23b reaches the draw-out area due to over-etching in the drilling process of the connection hole 23b. Can be eased. Therefore, the formation process of the connection hole 23b can be eased.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, in the above embodiment, the case where a p-type semiconductor substrate is used has been described. However, the present invention is not limited to this. For example, an n-type semiconductor substrate may be used. Further, the way of arranging the memory cell area in the SRAM chip is not limited to the above embodiment.

In the above embodiment, the driving transistor and the transfer transistor are MOSFETs.
However, the present invention is not limited to this. For example, the driving transistor and the transfer transistor may be formed by bipolar transistors.

In the above description, the invention made mainly by the present inventor is based on the SRA which
Although the description has been given of the case where the present invention is applied to M, the present invention is not limited thereto. For example, the present invention can be applied to a SRAM with logic having a logic circuit and an SRAM in the same semiconductor chip. The present invention is applicable to a semiconductor integrated circuit device having at least an SRAM.

[0086]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, a connection hole pattern for supplying a predetermined potential to a semiconductor region of a predetermined conductivity type is provided on an electrode pattern for soft error countermeasures. Is used as a connection hole pattern for supplying the electrode pattern, even if the structure changes between the case where the electrode pattern is provided and the case where the electrode pattern is not provided, whether the electrode pattern is arranged or not arranged in the change in the design stage Therefore, the change operation can be facilitated, and the change can be flexibly and promptly performed.

(2) According to the above (1), the change design time of the semiconductor integrated circuit device having the SRAM can be shortened, so that the short delivery time of the semiconductor integrated circuit device can be promoted.

(3) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, a connection hole pattern for supplying a predetermined potential to a semiconductor region of a predetermined conductivity type is provided with a predetermined potential on an electrode pattern for soft error countermeasures. By providing connection hole patterns for two different components in one region for use as a connection hole pattern for supplying the same, compared to the case where each connection hole pattern is provided at a separate place, Since the use area of the connection hole pattern can be reduced,
It is possible to promote downsizing of a semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an enlarged plan view of a main part of the semiconductor integrated circuit device of FIG. 1;

FIG. 3 is an equivalent circuit diagram of a main part of the semiconductor integrated circuit device of FIG. 1;

FIG. 4 is a cross-sectional view of a main part of a memory cell region and a well power supply region of the semiconductor integrated circuit device of FIG. 1;

FIG. 5 is a plan view of a main part of a well power supply region of the semiconductor integrated circuit device of FIG. 1;

FIG. 6 is a sectional view of a main part of a well power supply region of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 7 is a cross-sectional view of a main part of a well power supply region of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 8 is an explanatory diagram for describing a design process of the semiconductor integrated circuit device in FIG. 1;

FIG. 9 is an explanatory diagram for describing a design process of the semiconductor integrated circuit device in FIG. 1;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 SRAM chip (semiconductor integrated circuit device) 1 s semiconductor substrate 2 p-well (semiconductor region of predetermined conductivity type) 3 extraction region 4 deep n-well 5 field insulating film 6 gate insulating film 7 gate electrode 8 insulating film 8 a to 8 e insulating film 9 Side wall 10 an n ^{− type} semiconductor region 10 b n ^{+ type} semiconductor region 11 gate insulating film 12 gate electrode 12 a polysilicon film 12 b silicide film 13 side wall 14 n − type semiconductor region 15 ground wiring 15 a polysilicon film 15 b silicide film 16 data Line connection wiring 16a polysilicon film 16b silicide film 17 polysilicon film 18 plate electrode (electrode pattern) 18a projecting region 19a, 19b interlayer insulating film 20 connection hole 21 buried conductor film 22 second layer wiring 23a connection hole 23b connection hole 24 embedded guide Film 25 grounding wire M memory cell region Ms sub memory cell region MC memory cell DL1, DL2 data line WL the word line Qd1, Qd2 driver MOS · FET Qt1, Qt2 transfer MOS · FET R1, R2 load resistance A storage node

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Hoshino 5--20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Yuki Koide Kamimizuhoncho, Kodaira-shi, Tokyo 5-20-1 Nippon Cho Super LSI Engineering Co., Ltd. (72) Inventor Kazushi Fukuda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. (72 ) Inventor Yasuko Yoshida 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Koichi Toba 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Co., Ltd. In the semiconductor division of Hitachi, Ltd. (72) Inventor Shuji Ikeda In the semiconductor division of Hitachi Ltd. 5-chome's Satoshi Haga Tokyo Kodaira Josuihon-cho, No. 20 No. 1 Date standing ultra-El es Eye Engineering Co., Ltd. in

Claims (6)

[Claims] 1. A plurality of SRAM cells provided on a semiconductor region of a predetermined conductivity type on an upper portion of a semiconductor substrate, each of the plurality of SRAM cells being provided on the semiconductor region of the predetermined conductivity type and forming two storage elements. A transistor; two transfer transistors provided on the semiconductor region of the predetermined conductivity type to form a switching element; and a load resistance element formed by a conductor film provided on the drive transistor and the transfer transistor. A method for manufacturing a semiconductor integrated circuit device, comprising: providing an electrode pattern for soft error countermeasures so as to cover an SRAM cell on an upper layer of the load resistance element; Are arranged so that at least a part thereof overlaps a lead region for supplying a predetermined potential to the semiconductor region of the predetermined conductivity type. When a connection hole pattern serving as a passage for supplying a predetermined potential to the semiconductor region of the predetermined conductivity type is arranged in the lead-out region, the connection hole pattern is arranged in a part of the electrode pattern in the connection hole pattern. Using the connection hole pattern to be used as a connection hole pattern serving as a passage for supplying a predetermined potential to the electrode pattern. 2. A method according to claim 1, wherein each of a plurality of SRAM cells provided on a semiconductor region of a predetermined conductivity type on an upper portion of a semiconductor substrate comprises two driving cells for forming a storage element provided on the semiconductor region of the predetermined conductivity type. A transistor; two transfer transistors provided on the semiconductor region of the predetermined conductivity type to form a switching element; and a load resistance element formed by a conductor film provided on the drive transistor and the transfer transistor. A semiconductor integrated circuit device provided with an electrode pattern for soft error countermeasures so as to cover the SRAM cell above the load resistance element, wherein at least a part of the electrode pattern is The electrode pattern is arranged so as to overlap on a lead-out region for supplying a predetermined potential to the semiconductor region of the shape. The semiconductor integrated circuit device which is characterized by providing a connection hole for passage for supplying a predetermined potential to the emissions. 3. The semiconductor integrated circuit device according to claim 2, wherein said connection hole is perforated through an electrode pattern portion of said overlap region, and said conductor film embedded in said connection hole is A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is electrically connected to the electrode pattern through a contact portion with the electrode pattern exposed from an inner wall surface of the connection hole. 4. The semiconductor integrated circuit device according to claim 3, wherein said connection hole is drilled so that said lead-out region is exposed, and said conductor film embedded in said connection hole is formed in said connection hole. A semiconductor integrated circuit device electrically connected to the electrode pattern through a contact portion of the electrode pattern exposed from an inner wall surface, and electrically connected to the lead-out region. 5. The semiconductor integrated circuit device according to claim 2, wherein a plurality of the semiconductor regions of the predetermined conductivity type are provided on the semiconductor substrate in a state of being electrically separated from each other, and each of the semiconductor regions is provided separately. Wherein the lead-out region is provided along an outer periphery of the semiconductor integrated circuit device so as to surround the semiconductor region of the predetermined conductivity type. 6. The semiconductor integrated circuit device according to claim 2, wherein the driving transistor and the transfer transistor are MISFETs.