JPH1139876A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device which never destroy the internal data for irregular address noise. SOLUTION: A short pulse resulting from irregular noise is generated from an ATD circuit 13 in the fast route, but only one shot pulse is generated from an ATD circuit 15 in a slow route and the short pulse by irregular noise is not generated. Moreover, the one shot pulse from the ATD circuit 13 is generated in the earlier timing in comparison with the one shop pulse from the ATD circuit 15. Therefore, each pulse multiplex section 14 of the fast system is structured to generate pulse for the digit line precharger and internal node equalizer in the sense amplifier and each pulse multiplex section 16 of the slow system also generates the data reset pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an address transition detecting circuit for detecting a transition of an address signal.

[0002]

2. Description of the Related Art FIG. 10 is a block diagram showing an example of a conventional semiconductor memory device. The conventional semiconductor memory device shown in FIG. 1 includes an address buffer 61, a noise canceller 62, an address transition detection circuit (ATD: Address Transition Det).
ector) circuit 63 and each ATD pulse multiplex unit 64.

FIG. 1 shows a conventional semiconductor memory device.
1 will be described together with the time chart. In FIG.
The address input signal schematically shown in FIG.
The address signal is input to an address buffer 61 via buffer 0, is buffer-amplified, becomes an address signal shown in FIG. 11B, and is further supplied to a noise canceller 62. Noise canceller 6
2 has a configuration in which the input address signal is delayed for a predetermined period as shown in FIG. 11B, and irregular address noise during that period can be removed.
Is supplied to the ATD circuit 63.

The ATD circuit 63 has a configuration shown in FIG. 8 which will be described later, and generates an address transition detection signal as shown in FIG.
A one-shot pulse is generated as shown in
The pulse is supplied to the pulse multiplexing unit 64 to be synthesized into a desired pulse.

FIG. 12 is a block diagram showing another example of a conventional semiconductor memory device. The conventional semiconductor memory device shown in FIG. 1 is a semiconductor memory device described in Japanese Patent Application Laid-Open No. 8-55478, and includes an address buffer 71, a static ATD circuit 72, a dynamic ATD circuit 73, and a NOR circuit 74.
And each ATD pulse multiplex unit 75.

FIG. 1 shows the conventional semiconductor memory device.
3 will be described together with the time chart. In FIG.
The address input signal schematically shown in FIG.
After being input to an address buffer 71 via buffer 0 and buffer-amplified, it is supplied to a static ATD circuit 72 and a dynamic ATD circuit 73, respectively. The static ATD circuit 72 responds promptly to all address input transitions and outputs a one-shot pulse as shown in FIG. In addition, the dynamic ATD circuit 73 outputs a pulse as shown in FIG. 13C, for example, which goes high when there is an address input transition and goes low after a lapse of a predetermined time regardless of the input transition.

A NOR circuit 74 has a negation that becomes low when at least one of both pulses output from the static ATD circuit 72 and the dynamic ATD circuit 73 is high as shown in FIGS. 13B and 13C. The logical sum is calculated, and a pulse as shown in FIG. 13D is generated and supplied to each ATD pulse multiplexing unit 75 to synthesize a desired pulse.

In this conventional semiconductor memory device, when the address signal transitions at a short time interval due to noise or the like, the output pulse of the dynamic ATD circuit 73 is changed as shown in FIG.
Since the high level is maintained for a predetermined time as shown in FIG. 3 (C), a short cycle of the ATD pulse width at the time of normal address transition (FIG. 13 Since the extended ATD pulse (of (D)) is output to the NOR circuit 74, NO
The ATD pulse shown in FIG. 15D is output from the R circuit 74.

[0009]

However, in the conventional semiconductor memory device shown in FIG.
Has a circuit configuration capable of delaying all ATD pulse generation times (delay period indicated by in FIG. 11) and removing irregular address noise during that period, and
Since the start of activation of the internal circuit, that is, the access speed depends on the generation time of the above-mentioned ATD pulse, an access delay must be anticipated by the time during which the address input noise can be removed (delay period shown by in FIG. 11). There is a problem that it does not.

In the conventional semiconductor memory device shown in FIG. 10, the ATD circuit 63 has the circuit configuration shown in FIG. The ATD circuit 63 includes a cascade connection circuit 21 of four inverters, a two-input NAND circuit 22 and a two-input N circuit to which signals are respectively input from an input terminal and the cascade connection circuit 21.
OR circuit 23, inverter 24 for inverting the output signal of NOR circuit 23, NAND circuit 22 and inverter 2
It comprises a two-input NAND circuit 25 to which four output signals are supplied, respectively, and an inverter 26 for inverting the output signal of the NAND circuit 25.

In the ATD circuit 63, when an input signal ATDIN shown in FIG.
From (1), a positive-phase delay signal shown in FIG. 9B having the total delay time of the four inverters and the same phase as the input signal is extracted. As a result, the irregular noise a1 included in the input signal ATDIN naturally disappears as indicated by a2 in the in-phase delay signal due to the above-described delay.

The above-mentioned in-phase delay signal is the input signal ATDIN.
9C is supplied to the two-input NOR circuit 23, and is then logically inverted by the next-stage inverter 24 to become the signal shown in FIG. 9D. On the other hand, the above-mentioned positive-phase delay signal is the input signal ATDIN and the two-input NAND circuit 2.
2 and a signal having a short pulse width as shown in FIG. The output signal of the inverter 24 and the output signal of the NAND circuit 22 are output from the NAND circuit 25 and the inverter 2.
6 is output as a signal as shown in FIG.

As described above, in the conventional semiconductor memory device shown in FIG. 10, the ATD circuit 63 generates a one-shot pulse having a width corresponding to the normal phase delay time (the delay time in FIG. 9) every time the input address signal transitions. ATDOUT from inverter 26
Since the signal is output as a signal, a slip-through occurs in the ATD pulse generation start determination path (ATDIN input in FIG. 8), and when the irregular noise a1 is input, it responds to the irregular noise a1 and an erroneous pulse is generated. As a result, a short pulse a3 is output in the ATDOUT signal as shown in FIG. Therefore, when the generated pulse (ATDOUT signal) is used for digit line precharge or equalization in the sense amplifier,
Despite the insufficient read preparation state, an operation reset occurs and there is a risk of erroneous read.

On the other hand, the conventional semiconductor memory device shown in FIG. 12 has a configuration in which an ATD pulse is reliably generated for any address transition and an operation reset of an internal circuit is generated. Although the internal circuit does not malfunction due to the input noise, if the above-mentioned address input noise depends on the operation of the integrated circuit (IC) itself in terms of operation reset, that is, re-access, There is a problem that it appears as an access delay.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a semiconductor memory device that does not destroy internal data due to irregular address noise.

Another object of the present invention is to provide a semiconductor memory device capable of preventing an access delay due to address noise.

[0017]

In order to achieve the above object, the present invention provides a first address transition detection signal which receives an address signal as an input signal, and outputs a one-shot pulse first address transition detection signal every time the address signal transitions. 1 address transition detection circuit, and receives an address signal as an input signal, and outputs a one-shot pulse second address transition detection signal delayed by a predetermined time from the first address transition detection signal every time the address signal transitions. A second address transition detection circuit, and an activation sequence of an internal circuit that inputs a difference of a predetermined time between the first address transition detection signal and the second address transition detection signal as an activation signal. And a logic pulse generating means driven in accordance with the timing.

According to the present invention, an address transition detection circuit for detecting a transition of an address signal includes a first address transition detection circuit for outputting a fastest address transition detection signal at substantially the same time as a transition of an address signal, and a first address transition detection circuit. Since the system is divided into two systems of a second address transition detection circuit that outputs a second address transition detection signal delayed by a predetermined time from the signal, a logic pulse can be generated in accordance with the activation order of the internal circuit.

Further, the present invention has a noise canceller that receives an address signal as an input signal, performs noise cancellation with a predetermined delay time, and inputs the obtained address signal to a second address transition detection circuit. It is characterized by the following.

According to the present invention, noise can be prevented by the noise canceller. Therefore, even when internal address transition occurs due to power supply noise generated by the noise canceller, the noise canceller eliminates address noise to prevent operation reset. Can be. Further, the fastest first address transition detection signal can be obtained from the first address transition detection circuit.

The logic pulse generating means according to the present invention generates a pulse to a digit line precharge or a node equalizing inside the sense amplifier based on the first address transition detection signal, and generates a pulse to the second address transition detection signal. A data reset pulse is generated based on the data reset pulse.

In the present invention, the data latch period is obtained based on the output pulse of the logic pulse generating means after the precharging of the digit line and the equalizing of the internal node of the sense amplifier, and the data reset occurs. A circuit configuration in which no access occurs and no access delay occurs can be achieved.

[0023]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. In this embodiment, an address buffer 11, a noise canceller 12,
It comprises a fast ATD circuit 13, each ATD pulse multiplex unit 14, a slow ATD circuit 15 and each ATD pulse multiplex unit 16, and is characterized in that it has two systems, a slow route and a fast route. is there.

The noise canceller 12 has the same circuit configuration as the conventional one, and has a logic circuit type shown in FIG.
There is a CR delay type shown in FIG. The noise canceller of the logic circuit type shown in FIG.
, P-channel MOS transistors P1 to P4, and N-channel MOS transistors N1 to N4, and the delay time inherent to inverters 31 to 36 is used.

The CR delay type noise canceler shown in FIG.
And switching minimum units 42 to 44. The minimum switching units 42 to 44 are cascade-connected CR integrating circuits, each having a delay time according to the CR integration time constant. The ATD pulse generation circuits 13 and 15 have the same circuit configuration as in FIG.

Next, the operation of this embodiment will be described. First, an operation when no irregular noise is generated in the address input will be described. An address input signal schematically shown in FIG. 2A is supplied to an address buffer 11 via a terminal 10 and buffer-amplified, and then input to a noise canceller 12 on a slow path and an ATD circuit 13 on a fast path.

The noise canceller 12 receives the address signal schematically shown in FIG. 2B output from the address buffer 11, delays this by a predetermined delay time, and
The address signal shown in FIG.
Supply to circuit 15. This delay time is an address noise width that can be removed. The slow ATD circuit 15 generates the one-shot pulse shown in FIG. 2E based on the delay address signal from the noise canceller 12 and supplies it to each ATD pulse multiplex unit 16 by the circuit configuration of FIG. To synthesize a desired pulse.

On the other hand, the fast path ATD circuit 13
Receives the address signal output from the address buffer 11 and shown schematically in FIG.
The one-shot pulse shown in FIG. 2D is generated by the circuit configuration shown in FIG.
4 to synthesize a desired pulse. As shown in FIGS. 8 and 9, this one-shot pulse of the fast path is used for a system which leads to an increase in access speed as the activation of digit line precharge and the equalization of an internal node of the sense amplifier circuit is started earlier. Used as pulse synthesizer input.

The output one-shot pulse of the ATD circuit 15 on the slow path is compared with the output one-shot pulse of the ATD circuit 13 on the fast path.
, And even if the activation start time of the latch of the sense amplifier data or the like is delayed by the delay due to the one-shot pulse output from the ATD circuit 13 on the first path, the access is actually affected. There is no. This is because the one-shot pulse of the first path (FIG. 2D) may be ready to be read after the internal circuit is activated and activated later.

Next, the operation in the case where irregular noise occurs in the address input will be described with reference to the time chart of FIG. If the address input signal input via the terminal 10 has irregular noise as indicated by n1 as schematically shown in FIG. 3A, the address input signal is supplied to the address buffer 11. Irregular noise in the address signal is buffer-amplified as shown by n2 in FIG. 3 (B) and transmitted as it is to the noise canceller 12 on the slow path and the ATD circuit 13 on the fast path.

When the ATD circuit 13 receives the signal shown in FIG. 3B, as described with reference to FIGS.
As shown in (D), together with a one-shot pulse having a regular pulse width, a short pulse n4 shorter than the one-shot pulse width depending on the noise width of the irregular noise n2 is output.

On the other hand, in the slow path, the noise canceller 1
When receiving the signal shown in FIG. 3B, the signal 2 outputs a signal substantially removed as shown by n3 for the irregular noise n2 as shown in FIG. 3C. Therefore, ATD
When the circuit 15 receives the signal shown in FIG. 3C from the noise canceller 12, it outputs only a one-shot pulse having a regular pulse width as shown in FIG. 3E, and outputs a short pulse due to the irregular noise n3. do not do.

Therefore, in this embodiment, the ATD circuit 13 in the fast path generates a short pulse n4 due to the irregular noise n1 in addition to the one-shot pulse shown in FIG. ATD circuit 1
From FIG. 5, only the one-shot pulse shown in FIG. 3E is generated, and no short pulse due to irregular noise is generated.
The one-shot pulse from the ATD circuit 13 in the fast path is generated earlier in time than the one-shot pulse from the A circuit 15 in the slow path.

Therefore, as shown in FIG. 4, each pulse multiplex unit 14 and 16 in this embodiment is provided with a first-line pulse multiplex unit 14 to which an output signal of the ATD circuit 13 is input. Each pulse multiplex unit 16 of the slow system, which generates a pulse to charge or equalize the internal node of the sense amplifier, and receives the output signal of the ATD circuit 15, generates a pulse for data reset (= sense amplifier data latch). To be configured.

Thus, when the address signal shown in FIG. 5A is inputted, the one-shot pulse shown in FIG. 5B is inputted from the ATD circuit 13 to each pulse multiplexing section 14 of the fast system. 5 from the ATD circuit 15 to each pulse multiplex unit 16 of the slow system.
Since the one-shot pulse shown in FIG. 5C is input, the read preparation is performed based on the output pulse of each pulse multiplex unit 14 as shown in FIG. 5D. After the equalization of the internal node of the amplifier, a data latch period is obtained based on the output pulse of each pulse multiplex unit 16 as schematically shown in FIG. 5E, and a data reset occurs. Therefore, a circuit configuration can be provided in which no access occurs and no access delay occurs.

It should be noted that the present invention is not limited to the above-described embodiment. For example, the noise canceller 1 shown in FIG.
2 is not the one shown in FIG. 6 but a simple CR shown in FIG.
, A configuration using a noise canceller with a delay circuit as an alternative is conceivable. When the circuit configuration of FIG. 7 is used, the influence of the variation of the diffusion condition is larger than that of the circuit logic type noise canceller as shown in FIG. 6, but not only the circuit element scale of the noise canceller 12 itself is reduced but also the circuit configuration of FIG.
If the switch 41 as shown in (1) is prepared using an aluminum master slice, the advantage that the cancelable noise width due to the CR delay can be easily optimized can be obtained.

[0037]

As described above, according to the present invention,
An address transition detection circuit for detecting a transition of an address signal, a first address transition detection circuit for outputting a fastest address transition detection signal at substantially the same time as a transition of the address signal, and a delay of a predetermined time from the first address transition detection signal Since the system is divided into two systems of the second address transition detection circuit that outputs the second address transition detection signal, it is possible to generate a logic pulse in accordance with the activation order of the internal circuit.

According to the present invention, since noise can be prevented by the noise canceller, internal malfunction due to address input noise can be prevented, and a stable read operation can be obtained.

Furthermore, according to the present invention, even when an internal address transition occurs due to, for example, power supply noise generated by itself, the noise canceller can eliminate the address noise to prevent the operation reset from being generated. Since the fastest first address transition detection signal can always be obtained from the first address transition detection circuit for any address signal transition, an operation reset is not generated for an address noise input, and In addition, the normal address transition is not sacrificed, and no access delay occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a time chart for explaining the operation when a normal address is input in FIG. 1;

FIG. 3 is a time chart for explaining the operation at the time of inputting the address noise of FIG. 1;

FIG. 4 is an explanatory diagram of an ATD synthetic pulse application of a main part of the present invention.

FIG. 5 is a time chart for explaining the operation of FIG. 4;

FIG. 6 is a circuit diagram of an example of a noise canceller used in FIGS. 1 and 10;

FIG. 7 is a circuit diagram of another example of the noise canceller used in FIGS. 1 and 10;

FIG. 8 is a circuit diagram of an example of an ATD circuit used in FIGS. 1 and 10;

9 is a time chart for explaining the operation of the ATD circuit of FIG. 8;

FIG. 10 is a block diagram of an example of a conventional device.

FIG. 11 is a time chart for explaining the operation of FIG. 10;

FIG. 12 is a configuration diagram of another example of the conventional device.

FIG. 13 is a time chart for explaining the operation of FIG. 12;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Address signal input terminal 11 Address buffer 12 Noise canceller 13 Fast system address transition detection (ATD) circuit 14 Fast system ATD pulse multiplex unit 15 Slow system address transition detection (ATD) circuit 16 Slow system ATD pulse multiplex unit 31-31 36 Inverter 41 AI master slice switch 42 Minimum switching unit P1-P4 P-channel MOS transistor N1-N4 N-channel MOS transistor R1-R3 Resistance C1-C3 Capacitor

Claims (3)

[Claims] An address signal is received as an input signal.
A first address transition detection circuit that outputs an address transition detection signal, and a one-time delay circuit that receives the address signal as an input signal and that is delayed by a predetermined time from the first address transition detection signal every time the address signal transitions. A second address transition detection circuit that outputs a second address transition detection signal of a shot pulse; and a difference of the predetermined time between the first address transition detection signal and the second address transition detection signal; A semiconductor memory device comprising: logic pulse generating means for driving in accordance with an activation order of an internal circuit for inputting an address transition detection signal as an activation signal. 2. A noise canceller that receives the address signal as an input signal, performs noise cancellation with the predetermined delay time, and inputs the obtained address signal to the second address transition detection circuit. 2. The semiconductor memory device according to claim 1, wherein: 3. The logic pulse generation means generates a pulse to a digit line precharge or a node inside a sense amplifier based on the first address transition detection signal, and generates a pulse to the second address transition detection signal. 3. The semiconductor memory device according to claim 1, wherein a data reset pulse is generated based on the data reset pulse.