JPH1139867A - Internal voltage generating circuit and semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal voltage generating circuit which can generate a control voltage of a transistor depending on fluctuation of transistor characteristic due to fluctuation of process. SOLUTION: An internal voltage generating circuit is provided with a boosted voltage generating circuit 100 and a boosted voltage detecting circuit 101. The boosted voltage detecting circuit 101 is composed of a detecting section 102 and an activated voltage generating section 103. The boosted voltage generating circuit 100 outputs a boosted voltage Vpp obtained by raising the power supply voltage in the high potential side based on the input of the activating signal Vpp. The detecting section 102 outputs the power supply voltage in the low potential side as the detected voltage Vd until the boosted voltage Vpp reaches the predetermined value and also outputs, as the detected voltage Vd, the voltage which is lowered as much as the threshold value of the NMOS transistor from the boosted voltage Vpp. The activated voltage generating section 103 outputs the activated signal Vppen until the detected voltage Vd exceeds the predetermined value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an internal voltage generating circuit for generating a boosted voltage supplied to, for example, a word line of a semiconductor memory device.

In recent years, large-scale and high-integration semiconductor memory devices have been developed. In order to reduce power consumption, optimization of the boosted voltage supplied to the increased gate of the memory cell transistor is required.

[0003]

2. Description of the Related Art A back gate of an N-channel MOS (hereinafter referred to as NMOS) transistor constituting a cell transistor of a DRAM is used to stabilize the threshold value of the transistor or to prevent leakage of charged charges from a cell capacitor. , A substrate bias voltage is applied.

FIG. 5 shows a conventional substrate bias generation circuit. P-channel MOS whose source is connected to power supply VCC
The power supply VSS is connected to the gate of the transistor Tr50 (hereinafter referred to as PMOS). The transistor T
The drain of r50 is connected to the PM connected to the power supply VSS.
It is connected to the drain of the OS transistor Tr51.
The drains of the transistors Tr50 and Tr51, that is, the node N50, are connected to the input terminal of the step-down voltage generation circuit 50 via the two-stage inverters 51 and 52. The substrate bias voltage Vbb output from the step-down voltage generation circuit 50 is input to the gate of the transistor Tr51,
It is supplied to the back gate of the cell transistor.

The power supply VCC is supplied with, for example, 3 V, and the power supply VSS is supplied with, for example, 0 V. The transistor Tr50 is always on. The transistor Tr51 is turned on with a decrease in the substrate bias voltage Vbb output from the step-down voltage generation circuit 50, and its on-resistance decreases as the substrate bias voltage Vbb decreases. Therefore, as shown in FIG. 6, the detection potential Vda of the node N50 based on the ratio of the on-resistances of the transistors Tr50 and Tr51 decreases as the substrate bias voltage Vbb decreases.
The detection potential Vda is, for example, the substrate bias voltage Vbb minus-
In the case of 2v, it is set to be 1.5v.

The output potential of the inverter 51 is L level when the detection potential Vda is 1.5 V or more,
When da is less than 1.5 V, the output potential Vbben of the next-stage inverter 52 becomes H level (about 3 V) when the detection potential Vd is 1.5 V or more, and L level (about 3 V) when the detection potential Vda is less than 1.5 V. It is set to be about 0v).

The step-down voltage generation circuit 50 is activated when an H-level output potential Vbben is input, and lowers the substrate bias voltage Vbb. When the output potential Vbben becomes L level, it is inactivated.

In such a substrate bias generation circuit, when the substrate bias voltage Vbb becomes higher than -2 V, the detection potential Vda becomes higher than 1.5 V and the output potential Vbben becomes H level. Then, the step-down voltage generation circuit 50 is activated, and lowers the substrate bias voltage Vbb.

When the substrate bias voltage Vbb becomes lower than -2 V, the detection potential Vda becomes less than 1.5 V, and the output potential Vbben becomes L level. Then, the step-down voltage generation circuit 50 is inactivated, so that the substrate bias voltage Vbb increases toward 0v.

By such an operation, the substrate bias voltage Vbb output from the step-down voltage generation circuit 50 converges to -2v. The substrate bias voltage Vbb generated by the substrate bias generation circuit can be appropriately set by adjusting the threshold value of the inverter 51 or the size of the PMOS transistors Tr50 and Tr51.

FIG. 7 shows a word line of a DRAM, that is, an NMO.
5 shows a word line voltage generation circuit that generates a boosted voltage to be supplied to the gate of a cell transistor composed of S transistors.

PMOS having a gate and a drain connected to each other
The drain of the transistor Tr53 is connected to the source of the PMOS transistor Tr54. The gate of the transistor Tr54 is connected to a power supply VCC (for example, 3 V). The drain of the transistor Tr54 is connected to a power supply VSS (for example, 0 V) via a resistor R. The drain of the transistor Tr54 is connected to the input terminal of the boosted voltage generation circuit 54 via the inverter 53. The boosted voltage Vpp output from the boosted voltage generation circuit 54
Is supplied to the source of the transistor Tr53 and to a selected word line via a word line drive circuit. The amplitude of the output signal of the inverter 53 is from the power supply VCC (3v) to the power supply VSS (0v).

The transistors Tr53 and Tr54 are connected to a boosted voltage Vpp output from the boosted voltage generation circuit 54.
When it becomes higher than CC by the threshold value of the transistors Tr53 and Tr54, it is turned on. When the boosted voltage Vpp becomes, for example, 5 V, the detection potential V at the node N51 based on the resistance ratio between the on-resistance of the transistors Tr53 and Tr54 and the resistance R.
db is set to 3v.

When the boosted voltage Vpp becomes less than 5V, the transistor Tr54 is first turned off, and the detection potential Vdb decreases toward 0V. Therefore, the output potential Vppen of the inverter 53 is at the L level when the transistors Tr53 and Tr54 are turned on and the detection potential Vdb exceeds the threshold value of the inverter 53, and the transistors Tr53 and Tr54 are turned off and the detection potential Vdb is When it falls below the threshold value of 53, it goes to H level.

The boosted voltage generating circuit 54 is activated when an H level output potential Vppen is input, and the boosted voltage Vppen is activated.
To rise. When the output potential Vppen at L level is input, it is deactivated.

In this word line voltage generation circuit, when the boosted voltage Vpp becomes 5 V or more, the boosted voltage generation circuit 54 is inactivated. Then, the boosted voltage Vpp decreases. Then, when the boosted voltage Vpp becomes lower than 5 V, the boosted voltage generation circuit 54 is activated to increase the boosted voltage Vpp.

By such an operation, the boosted voltage Vpp output from the boosted voltage generation circuit 54 converges to 5V. The voltage value of the boosted voltage Vpp generated by the word line voltage generation circuit can be appropriately set by adjusting the number of PMOS transistors.

[0018]

As semiconductor memory devices become more highly integrated, the variation in cell transistor characteristics from chip to chip due to process variations tends to increase.

In the substrate bias generation circuit, however, the change in the substrate bias voltage Vbb is detected by a PMOS transistor, so that the optimum substrate bias voltage Vbb is obtained.
Has been generated. Therefore, it is not possible to detect variations in the NMOS transistors constituting the cell transistor, and a constant substrate bias voltage Vbb is generated regardless of the variations in the NMOS transistors.

Further, the boosted voltage Vpp is also detected by the PMOS transistor in the word line voltage generating circuit, so that the boosted voltage Vpp corresponding to the variation of the cell transistor cannot be generated as the word line voltage.

For this reason, it is necessary to set the boosted voltage Vpp so that a sufficient margin can be ensured even for variations in cell transistors. Then, depending on the chip, an unnecessarily high boosted voltage Vpp may be generated and supplied to the word line. In such a chip, the boosted voltage Vpp is repeatedly applied to the gate of the cell transistor, which causes deterioration of the cell transistor. Further, there is a problem that the higher the boosted voltage Vpp, the more the current consumption accompanying the selection and non-selection operation of the word line.

An object of the present invention is to provide an internal voltage generation circuit capable of generating a control voltage for a transistor in accordance with a variation in transistor characteristics due to a process variation.

[0023]

FIG. 1 is a diagram for explaining the principle of the first aspect of the present invention. That is, the internal voltage generation circuit includes the boosted voltage generation circuit 100 and the boosted voltage detection circuit 101
, And the boosted voltage detection circuit 101 includes a detection unit 102 and an activation signal generation unit 103. The boosted voltage generation circuit 100 outputs a boosted voltage Vpp obtained by boosting the high potential side power supply voltage based on the input of the activation signal Vppen. The detection unit 102 outputs the low-potential-side power supply voltage as a detection voltage Vd until the boosted voltage Vpp reaches a predetermined value.
Exceeds a predetermined value, a voltage obtained by stepping down the boosted voltage Vpp by the threshold value of the NMOS transistor is output as a detection voltage Vd. The activation signal generation unit 103 detects the detection voltage V
The activation signal Vppen is output until d exceeds a predetermined value.

According to a second aspect of the present invention, the detecting unit is configured such that the boosted voltage is input to a gate, the high-potential-side power supply is input to a drain, and a substrate bias voltage generated by a substrate bias generation circuit is input to a back gate. NMO supplied
An S transistor and a resistor connected between a source of the NMOS transistor and a low-potential-side power supply. The activation signal generator receives the detection voltage output from the source of the NMOS transistor. The threshold value of the inverter is shifted from an intermediate level between the high potential power supply and the low potential power supply to a high potential side.

According to a third aspect of the present invention, the substrate bias generation circuit outputs a step-down voltage obtained by stepping down a low-potential-side power supply voltage as the substrate bias voltage based on an input of an activation signal; An NMOS transistor having a bias voltage input to the back gate, a source connected to the low-potential power supply, and a gate and a drain connected to the high-potential power supply via a resistor;
And an inverter for outputting the activation signal when a drain voltage of the S transistor is inputted and the drain voltage becomes equal to or lower than a threshold value.

According to a fourth aspect of the present invention, the NM constituting the memory cell
A semiconductor memory device that performs a write operation and a read operation of cell information by applying a boosted voltage generated by an internal voltage generation circuit to a gate of an OS transistor through a word line, wherein the internal voltage generation circuit is A boosted voltage generation circuit that outputs a boosted voltage obtained by boosting the high potential side power supply voltage based on the input of the activation signal, and outputs the activation signal to the boosted voltage generation circuit until the boosted voltage reaches a predetermined value. A boosted voltage detection circuit for stopping the output of the activation signal when the boosted voltage exceeds a predetermined value, wherein the boosted voltage detection circuit receives the boosted voltage at a gate and outputs the high potential An NMOS transistor to which a power supply is supplied to a drain and a substrate bias voltage generated by a substrate bias generation circuit is supplied to a back gate; A resistor connected between the source of the S transistor and the low-potential side power supply and the detection voltage output from the source of the NMOS transistor are input, and when the detection voltage does not reach a threshold value, the activation signal And a threshold value of the inverter is shifted from an intermediate level between the high potential power supply and the low potential power supply to a high potential side.

(Operation) According to the first aspect of the present invention,
Until the detection voltage Vd reaches a predetermined value, the activation signal Vppen
Is output, the boosted voltage Vpp rises, and when the detection voltage Vd exceeds a predetermined value, the activation signal Vppen is not output, and the boosted voltage Vpp decreases. Since the detection voltage Vd is a voltage obtained by stepping down the boosted voltage Vpp by the threshold value of the NMOS transistor, the boosted voltage Vpp is NMO higher than a predetermined value.
It converges to a level higher by the threshold value of the S transistor.

According to the second aspect of the present invention, the detection voltage is output based on the boosted voltage input to the gate of the NMOS transistor. When a detection voltage lower than the threshold value is input, the inverter outputs H as an activation signal.
Output level signal. Since the threshold value of the inverter deviates from the intermediate level between the high potential side power supply and the low potential side power supply to the high potential side, the threshold value of the inverter + NM
The boosted voltage serving as the threshold value of the OS transistor is maintained at a higher level than the high potential side power supply.

According to the third aspect of the present invention, in the substrate bias generating circuit, the step-down voltage generating circuit outputs a step-down voltage obtained by stepping down the low potential side power supply voltage as the substrate bias voltage based on the input of the activation signal. I do. The substrate bias voltage is input to the back gate of the NMOS transistor. When the drain voltage falls below the threshold based on the substrate bias voltage, an activation signal is output from the inverter. Therefore, the drain voltage converges to the threshold level of the inverter, and the substrate bias voltage converges so that the threshold value of the NMOS transistor becomes a predetermined value.

According to the fourth aspect of the present invention, the boosted voltage generating circuit outputs a boosted voltage obtained by boosting the high potential power supply voltage based on the input of the activation signal. A detection voltage based on the boosted voltage input to the gate is output from the NMOS transistor. When a detection voltage lower than the threshold is input from the inverter, an H-level signal is output as an activation signal. Since the threshold value of the inverter is shifted from the intermediate level between the high-potential-side power supply and the low-potential-side power supply to the high-potential side, the threshold value of the inverter + N
The boosted voltage serving as the threshold value of the MOS transistor converges to a level higher than the high potential side power supply and is maintained.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG.
1 shows a substrate bias generation circuit 1 and a word line voltage generation circuit 2 mounted on M. In the present embodiment, the substrate bias generation circuit 1 and the word line voltage generation circuit 2 constitute an internal voltage generation circuit.

The substrate bias generation circuit 1 has a monitor transistor Tr1 as a second detection MOS transistor.
Is provided. This monitoring transistor Tr1 is
The electrical characteristics are the same as those of the NMOS transistor forming the cell transistor in the memory cell.

The source of the transistor Tr1 is connected to a power source VSS which is a low potential side power source, and the gate is connected to the drain. The drain of the transistor Tr1 is connected via a fixed resistor R1 to a power supply VCC which is a high-potential power supply. The drain of the transistor Tr1 is connected to the inverter 3
Is connected to the input terminal of the step-down voltage generation circuit 4 via The output voltage Vbb of the step-down voltage generation circuit 4 is supplied to the back gate of the transistor Tr1, and
It is supplied to the back gate of the cell transistor of AM.

In this embodiment, the power supply VCC is 3 V,
The power supply VSS is supplied with 0V. The transistor T
The threshold value of r1 changes according to the substrate bias voltage Vbb. More specifically, the threshold value decreases as the substrate bias voltage Vbb increases toward 0 V, and increases as the substrate bias voltage Vbb decreases. That is, the on-resistance of the transistor Tr1 is equal to the substrate bias voltage V
It increases as bb drops.

Accordingly, the detection potential V at the node N1 based on the resistance ratio between the on-resistance of the transistor Tr1 and the fixed resistance R1.
d1 increases as the substrate bias voltage Vbb decreases as shown in FIG.

The output potential Vbben of the inverter 3 is L level (about 0 V) when the detection potential Vd1 is 1.5 V or more,
H level (about 3 V) when the detection potential Vd1 is less than 1.5 V
It is set to be.

The step-down voltage generation circuit 4 is activated when an H-level output potential Vbben is input, and lowers the substrate bias voltage Vbb. Also, the L-level output potential Vbben
Is deactivated when is input.

In such a substrate bias generation circuit 1,
When the detection potential Vd1 becomes less than 1.5 V, the output potential V
bben becomes H level, the step-down voltage generation circuit 4 is activated, and the substrate bias voltage Vbb is lowered. Then
The on-resistance of the transistor Tr1 increases, and the detection potential Vd1 increases.

When the detection potential Vd1 becomes 1.5 V or more, the output potential Vbben becomes L level and the step-down voltage generation circuit 4 is inactivated, so that the substrate bias voltage Vbb increases toward 0V. . Then, the on-resistance of the transistor Tr1 decreases, and the detection potential Vd1 decreases.

By such an operation, the substrate bias voltage Vbb converges so that the detection potential Vd1 converges to 1.5 V, that is, the on-resistance of the transistor Tr1 with respect to the fixed resistance R1 becomes constant. Accordingly, the substrate bias generation circuit 1 generates the substrate bias voltage Vbb such that the threshold value of the transistor Tr1 becomes a predetermined value even if the electrical characteristics of the NMOS transistors of each chip are different due to process variations. .

The word line voltage generation circuit 2 includes a monitoring transistor Tr2. The monitoring transistor Tr2 has the same electrical characteristics as the NMOS transistor forming the cell transistor in the memory cell.

The drain of the transistor Tr2 is connected to a power supply V.
The source is connected to a power supply VSS (0v) via a fixed resistor R2 as a resistance element.
The source of the transistor Tr2 is connected to the input terminal of the boosted voltage generation circuit 5 via the inverter 6. The output voltage Vpp of the boosted voltage generation circuit 5 is the same as that of the transistor Tr2.
, And supplied to a selected word line via a word line drive circuit. The back gate of the transistor Tr2 has the substrate bias voltage V
bb has been supplied. The amplitude of the output signal of the inverter 6 is from the power supply VCC (3v) to the power supply VSS (0v), and the threshold value Vi is set to a level slightly lower than the power supply VCC, for example, about 2.7v. In the present embodiment, the fixed resistor R2 and the transistor Tr2 constitute a detection unit, and the inverter 6 constitutes an activation signal generation unit.

Since the back gate of the transistor Tr2 is supplied with the substrate bias voltage Vbb,
As with the cell transistors constituting the DRAM, the threshold value is constant irrespective of process variations.

The detection potential Vd2 as the detection voltage of the drain of the transistor Tr2, that is, the node N2, is one of the boosted voltage Vpp-threshold Vth and the power supply Vcc level, if the threshold of the transistor Tr2 is Vth. It will be lower. Then, as shown in FIG. 4, the detection potential Vd2 rises as the boosted voltage Vpp rises, and the power supply Vcc level becomes the upper limit.

Therefore, the detection potential Vd2 is equal to the threshold value Vi.
Until the output potential Vppen of the inverter 6 becomes H level, the boosted voltage Vpp rises. When the detection potential Vd2 exceeds the threshold value Vi, the output potential Vppen becomes L level, and the boosted voltage Vpp becomes descend. By such an operation, the boosted voltage Vpp becomes higher than the threshold value Vi by the transistor Tr2.
Converge to a higher level by the threshold value of.

The substrate bias generation circuit 1 and the word line voltage generation circuit 2 configured as described above have the following effects. (1) The threshold value Vth of the monitoring transistor Tr2 is equal to the threshold value of the NMOS transistor constituting the cell transistor in the memory cell. In the word line voltage generation circuit 2, the boosted voltage Vpp converges to a voltage level higher than the threshold value Vi of the inverter by the threshold value of the transistor Tr2. By setting the threshold value Vi to a value close to the power supply Vcc level, the boosted voltage Vpp can be maintained at a level higher than the power supply Vcc level by the threshold value of the cell transistor. Therefore, even if the threshold voltage of the cell transistor varies, the boosted voltage Vpp can always be maintained at the optimum level. (2) Since an unnecessarily high boosted voltage Vpp is not supplied to the gate of the cell transistor, deterioration of the cell transistor can be prevented. Further, since the amplitude of the word line potential is not unnecessarily increased, current consumption can be reduced. (3) In the substrate bias voltage generation circuit, a substrate bias voltage Vbb that keeps the threshold value of the transistor Tr1 having the same characteristics as the cell transistor constant regardless of the variation in the characteristics of the cell transistor is generated. The voltage Vbb is supplied to the back gate of the cell transistor. Therefore, the threshold value of the cell transistor can be kept constant regardless of process variations.

The above embodiment may be modified and implemented as follows. The fixed resistors R1 and R2 in the above embodiment may be any type of resistance element such as a MOS transistor.

Even if the substrate bias voltage Vbb generated by the conventional substrate bias generation circuit shown in FIG. 5 is supplied to the back gate of the transistor Tr2, the same operation and effect as the above (1) and (2) can be obtained. be able to.

[0049]

As described above in detail, according to the first aspect of the present invention, there is provided an internal voltage generating circuit capable of converging a boosted voltage to a level higher than a predetermined value by a threshold value of an NMOS transistor. be able to.

According to the second aspect of the present invention, the first aspect is provided.
In addition to the effects of the invention described in (1), it is possible to provide an internal voltage generation circuit that can maintain the boosted voltage at a higher level than the high potential side power supply.

According to the invention set forth in claim 3, according to claim 2
In addition to the effects of the invention described in the above, the substrate bias voltage is set to NMO
It is possible to provide an internal voltage generation circuit that can make the threshold value of the S transistor converge so as to be a predetermined value.

According to the fourth aspect of the present invention, there is provided a semiconductor memory device capable of maintaining a boosted voltage at a level higher than a predetermined value by a threshold value of an NMOS transistor and higher than a high potential side power supply. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram illustrating an internal voltage generation circuit according to the embodiment;

FIG. 3 is a waveform chart showing each potential of the substrate bias generation circuit of the embodiment.

FIG. 4 is a waveform chart showing each potential of the word line voltage generation circuit of the embodiment.

FIG. 5 is a circuit diagram showing a conventional substrate bias generation circuit.

FIG. 6 is a waveform chart showing each potential of a conventional substrate bias generation circuit.

FIG. 7 is a circuit diagram showing a conventional word line voltage generation circuit.

FIG. 8 is a waveform diagram showing each potential of a conventional word line voltage generation circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 boost voltage generation circuit 101 boost voltage detection circuit 102 detection section 103 activation signal generation section Vpp boost voltage Vd detection voltage Vbben activation signal

Claims (4)

[Claims] A boosting voltage generating circuit for outputting a boosted voltage obtained by boosting a high-potential-side power supply voltage based on an input of an activating signal; and generating a boosted voltage until the boosted voltage reaches a predetermined value. A boosted voltage detection circuit for outputting the activation signal when the boosted voltage exceeds a predetermined value, wherein the boosted voltage detection circuit is inactive. A detection unit that sometimes outputs a low-potential-side power supply voltage as a detection voltage and, when activated based on the input of the boosted voltage, outputs a voltage obtained by reducing the boosted voltage by a threshold value of an NMOS transistor as a detection voltage; An activation signal generation unit that outputs the activation signal until the detection voltage exceeds a predetermined value. 2. The detection section, wherein the boosted voltage is input to a gate, the high-potential-side power supply is input to a drain, and a substrate bias voltage generated by a substrate bias generation circuit is supplied to a back gate. An NMOS transistor; and a resistor connected between a source of the NMOS transistor and a low-potential-side power supply. The activation signal generator receives the detection voltage output from the source of the NMOS transistor. 2. The internal voltage generator according to claim 1, wherein a threshold value of the inverter is shifted from an intermediate level between the high potential side power supply and the low potential side power supply to a high potential side. circuit. A step-down voltage generating circuit that outputs a step-down voltage obtained by stepping down a low-potential-side power supply voltage as the substrate bias voltage based on an input of an activation signal; NMO is input to the back gate, the source is connected to the low potential power supply, and the gate and drain are connected to the high potential power supply via a resistor.
3. The semiconductor device according to claim 2, comprising: an S transistor; and an inverter that outputs the activation signal when a drain voltage of the NMOS transistor is input and the drain voltage becomes equal to or lower than a threshold value. Internal voltage generation circuit. 4. A semiconductor memory device that performs a write operation and a read operation of cell information by applying a boosted voltage generated by an internal voltage generation circuit to a gate of an NMOS transistor forming a memory cell via a word line. Wherein the internal voltage generation circuit outputs a boosted voltage obtained by boosting a high-potential-side power supply voltage based on an input of an activation signal; and the boosted voltage generation circuit outputs the boosted voltage until the boosted voltage reaches a predetermined value. A boosted voltage detection circuit that outputs an activation signal to a boosted voltage generation circuit and stops outputting the activation signal when the boosted voltage exceeds a predetermined value. Is input to the gate, the high-potential-side power is input to the drain, and the substrate bias voltage generated by the substrate bias generation circuit is supplied to the back gate. An NMOS transistor, a resistor connected between a source of the NMOS transistor and a low-potential-side power supply, and the detection voltage output from the source of the NMOS transistor, and the detection voltage reaches a threshold value. And an inverter that outputs the activation signal when not in operation, wherein the threshold value of the inverter is shifted from an intermediate level between the high potential power supply and the low potential power supply to a high potential side. Semiconductor storage device.