JPH1139069A - Bus module and arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus module of which data transmission is speeded up and power consumption is reduced, and to provide an arithmetic unit where connection is simplified by transmitting a signal transmitted between an arithmetic module and a memory module with a light signal. SOLUTION: The arithmetic module 30 and the memory module 40 are arranged for a supporting substrate 10 by sandwiching an optical bus module 20. Pulse-like light carrying the signal is emitted from a light.emitting element 21 incorporated into the arithmetic module 30-side of the optical bus module 20 and it is diffusively transmitted through the optical transmission layer of an optical bus 23. Then, it is detected by a light-receiving element 22b incorporated into a memory module 40-side. Thus, the signal emitted from the arithmetic module 30 is transmitted to the memory module 40. The multiplexing transmission circuit cart 32 of the arithmetic module 30 and the multiplexing transmission circuit part of the memory module 40 are provided with multiplexers 33 and 43 and demultiplexers 34 and 44.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus module for transmitting data between an operation module having a processor and a plurality of memory modules having a memory, and a bus module for transmitting data between the operation module, the plurality of memory modules, and the bus module. The present invention relates to an arithmetic device provided.

[0002]

2. Description of the Related Art Conventionally, data has been transmitted between an arithmetic module having a processor and a memory via a bus line composed of an address signal line, a data signal line, and a control signal line. FIG. 5 is a diagram showing a configuration of a conventional and most commonly used bus wiring.

An arithmetic module (hereinafter referred to as CPU) shown in FIG.
A transmission control circuit 52 and a transmission control circuit 52 are connected by a bus wiring 53, and the transmission control circuit 52 and a plurality of memories 54 are connected by a bus wiring 55. The transmission control circuit 52 transmits the address signal, the data signal, and the control signal output from the CPU module 51 to the bus wiring 53.
And generates a signal for designating any one of the plurality of memories 54 based on the input address signal. The generated signal is transmitted via the bus wiring 55. By transmitting the data, the memory 54 is specified, and further, the memory 5 is connected via the bus wiring 55.
4 or the data stored in its memory 54 is read and transmitted to the CPU module 51. In a personal computer employing such a bus wiring, there are generally about 100 bus wirings for connecting the CPU module and the transmission control circuit and about 100 bus wirings for connecting the transmission control circuit and the main memory (DRAM). 10 at the workstation
In some cases, the number exceeds 00.

FIG. 6 is a diagram showing a configuration of a bus wiring proposed in Japanese Patent Publication No. 5-507374. Signals between the CPU module 61 and the memory 62 are time-division multiplexed (parallel / serial conversion) by the transmission control circuit 63 arranged between the CPU module 61 and the memory 62, and the transmission control circuit 63 and the memory 62 The number of bus lines 64 to be connected is reduced. Further, all the bus lines 64 are linearly arranged, and a terminating resistor 65 is connected to all the ends of the bus lines 64, thereby achieving impedance matching of the bus lines 64. Further, the length of the bus wiring 64 is made shorter and equal, and two clock wirings 66 for transmitting clock signals in mutually different directions are provided.
By transmitting the data signal on the bus line 64 in synchronization with the clock signal in the same transmission direction as the data signal on the bus line 64, the transmission frequency per bus line 64 becomes 6
It has been raised to 00 MHz. In this configuration of the bus wiring, since the number of the bus wirings 64 is small, a compact wiring board can be obtained.

[0005]

However, as shown in FIG.
Conventionally, in the most commonly used bus wiring configuration,
In proportion to the number of bus wirings, power consumption for transmission increases and the area of the wiring board increases, resulting in a problem of increased cost. If the number of bus lines is large, it is difficult to make the lengths of the respective lines equal, so that there is a problem that a difference occurs in the wiring capacity, a transmission skew occurs, and a transmission error occurs. Further, when a large number of memories are connected to the bus wiring, the additional capacity of the bus wiring increases, and it is difficult to increase the transmission frequency due to the limitation by the CR time constant of the bus wiring. The state becomes small and is crushed with a delay, which causes a problem that a transmission error easily occurs. In the configuration of this bus wiring,
In order to cope with the ever-increasing speed of data transmission between the CPU module and the memory, it is conceivable to increase the number of bus lines to increase the bit width of the signal (increase the bandwidth). However, when the number of bus wirings is increased, as described above, problems such as an increase in power consumption for transmission, an increase in the area of the wiring board, and a transmission error occur.

On the other hand, in the configuration of the bus wiring proposed in Japanese Patent Application Laid-Open No. 5-507374, in which the number of bus wirings is reduced and impedance matching is achieved, a large number of memories are connected or the wiring length is increased. , The additional capacity increases, which causes a problem that it is difficult to increase the transmission frequency. In addition, the pattern width and space of the bus wiring arranged linearly are set to predetermined dimensions in order to match impedance, and there is a disadvantage that the degree of freedom in pattern design on the wiring board is small. Therefore, this configuration is not suitable for an image processing apparatus or a workstation that requires a large-capacity memory, and is considered to be limited to a case where a small-capacity memory is connected.

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a bus module that achieves high-speed and low-power data transmission between an arithmetic module having a processor and a memory module having a memory, and a simplified connection. It is an object of the invention to provide a designed computing device.

[0008]

According to the present invention, there is provided a bus module for transmitting data between an arithmetic module having a processor and a plurality of memory modules having a memory accessed by the arithmetic module. In the module, a signal transmitted between the arithmetic module and the memory module is transmitted as an optical signal.

According to another aspect of the present invention, there is provided an arithmetic unit including an arithmetic module having a processor, a plurality of memory modules having a memory accessed by the arithmetic module, and a memory module between the arithmetic module and the memory module. A bus module for transmitting a signal to be transmitted as an optical signal, the bus module having a plurality of transmitting units having a light emitting element for converting an input electric signal into an optical signal, and a sheet-shaped optical signal; An optical transmission unit that forms a common transmission path for optical signals that diffuses and propagates, and a reception unit that has a light receiving element that receives an optical signal transmitted through the optical transmission unit and converts the optical signal into an electric signal. Wherein each of the arithmetic module and the memory module converts a parallel signal into a serial signal and converts the serial signal. And parallel-to-serial conversion unit for transmitting the serial bus module, characterized by comprising a serial-to-parallel converter for converting a serial signal transmitted from the bus module into a parallel signal.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a basic configuration diagram of an arithmetic unit according to an embodiment of the present invention. The operation module 30 and the memory module 40 are arranged on the support substrate 10 shown in FIG. 1 with the optical bus module 20 interposed therebetween. Note that the memory module 40 is
Although a plurality are arranged at 0, one is exemplarily shown in FIG.

The optical bus module 20 includes light emitting elements 21a and 22a for converting an input electric signal into an optical signal,
An optical bus 23 that diffuses and propagates the optical signals output from the light emitting elements 21a and 22a, and a light receiving element 21b and 22b that receives the optical signal propagated through the optical bus 23, converts the optical signal into an electric signal, and outputs the electric signal. And are provided. In this embodiment, a pair of the light emitting element 21a and the light receiving element 21b is incorporated in the arithmetic module 30 as the optical element 21, and a pair of the light emitting element 22a and the light receiving element 22b is the optical element 22 in the memory module 40. Built in.

The operation module 30 includes a CPU 31 and a multiplex transmission circuit section 32. The CPU 31
It outputs a control signal including a parallel address signal and inputs and outputs a parallel data signal. The multiplex transmission circuit unit 32 includes a multiplexer 33 that converts a parallel control signal and a parallel data signal output from the CPU 31 into a serial signal, and converts a serial signal input from the optical bus module 20 into a parallel signal. CPU
31 is provided.

The memory module 40 includes a plurality of memories 41 and a multiplex transmission circuit section 42. Each of the plurality of memories 41 receives a control signal and a data signal output from the CPU 31, and writes a data represented by the data signal at an address specified by an address signal included in the control signal.
A read operation is performed in which an address signal included in the control signal output from 1 is received and data consisting of a plurality of bits stored in an address specified by the address signal is read in parallel.

The multiplex transmission circuit section 42 includes a demultiplexer 44 that converts a serial signal input from the optical bus module 20 into a parallel signal and transmits the parallel signal to the memory 41.
A multiplexer 43 is provided for converting a parallel data signal read from the memory 41 into a serial signal and transmitting the serial signal to the optical bus module 20. FIG. 2 is a perspective view of the arithmetic device shown in FIG.

On the supporting substrate 10 shown in FIG.
A sheet optical bus 23 in which the layers 4 and the cladding layers 25 are alternately stacked is fixed. Further, module connectors 50,..., 50 are fixed on the support substrate 10,
The arithmetic module 30 and the memory modules 40,..., 40 are detachably mounted on the module connectors 50,.

A power supply line and electric wires 11 for transmitting electric signals are provided on the support substrate 10, and the electric wires 11 are connected to the module connectors 50,.
., 40 and the memory 31 on each of the memory modules 40,..., 40 attached to the module connectors 50,.

When the arithmetic module 30 and each of the memory modules 40,..., 40 are mounted on the module connector 50, the arithmetic module 30 is located at a position facing each optical transmission layer 24 of the signal light input / output unit 26 of the optical bus 23. The signal light emitted from the light emitting element 21a in the arranged optical element 21 (see FIG. 1) enters the optical transmission layer 24 of the optical bus 23,
An optical element that propagates in the optical transmission layer 24, is transmitted to the signal light input / output unit 27 of the optical bus 23, and is arranged at a position of the memory module 40 that is optically coupled to the signal light input / output unit 27. The light is received by the light receiving element 22b of the reference numeral 22.

FIG. 3 is an enlarged view showing a part of the arithmetic unit shown in FIG. However, in FIG. 3, the number of layers of the sheet-shaped optical bus 23 is generalized, and a light-shielding layer is further added. The optical bus 23 is fixed on the support substrate 10, and has an optical transmission layer 24, a cladding layer 25 formed so as to sandwich the optical transmission layer 24 from above and below, and a light shielding layer sandwiched between the cladding layers 25. 28 has a structure in which a plurality of layers are stacked as shown.

The light transmission layer 24 is a layer for transmitting signal light, and in this embodiment, polymethyl methacrylate (PMMA) having a high light transmittance and a thickness of 0.5 mm per layer is used. The cladding layer 25 is a layer that functions to suppress light in the light transmission layer 24 from leaking in the thickness direction of the layer, and a material having a lower refractive index than the light transmission layer 24 is selected. . In the present embodiment, since polymethyl methacrylate (PMMA) is used for the light transmission layer 24, a fluorine-containing polymer is suitably used for the cladding layer 25. In the present embodiment, the signal light is applied to the cladding layer 2.
In order to prevent the light from being incident on the light transmission layer 24 adjacent beyond the light transmission layer 5, a light-shielding layer 28 that absorbs light is provided so as to be interposed between the cladding layers 25. The thickness of the two cladding layers 25 sandwiching the light shielding layer 28 is 0.5 mm, which is the same as the thickness of the light transmission layer 24. The optical bus 23 having the illustrated laminated structure is formed by preparing and stacking these sheet materials and then pressing them.

On the other hand, at the lateral end of the arithmetic module 30,
As shown in FIG. 3, a plurality of optical elements 21 arranged at the same pitch as the optical transmission layers 24 in the thickness direction of the optical bus 23 are arranged. A signal input / output terminal 36 is provided. still,
Although not shown, in each of the memory modules 40,..., A plurality of optical elements are arranged at the lateral end and electric signal input / output terminals are arranged at the lower end, similarly to the arithmetic module 30 shown in FIG. Have been.

Light emitting element 21 used in this embodiment
a and 22a are laser diodes that emit red visible light having a wavelength of 650 mm, and the light receiving elements 21b and 22b are
650 mm wavelength emitted from the light emitting elements 21a and 22a
The photodiode is sensitive to red visible light, and is disposed in contact with the signal light input / output unit on the side surface of the optical transmission layer 24 of the optical bus 23.

The light emitting element 21 a of the optical bus module 20 which is incorporated on the operation module 30 side emits pulsed light carrying a signal, and enters the optical transmission layer 24 of the optical bus 23. The incident light diffuses and propagates in polymethyl methacrylate (PMMA) constituting the light transmission layer 24, is incorporated in each of the memory modules 40,..., 40, and is disposed on the end face side of the light transmission layer 24. Is detected by Thus, the signal emitted from the arithmetic module 30 is transmitted to each of the memory modules 40,.

Returning to FIG. 1, the description will be continued. When writing data from the operation module 30 to the memory module 40, the CPU 31 provided in the operation module 30
Output a control signal including a parallel address signal and a parallel data signal. The output control signal and data signal are input to a multiplexer 33, which performs parallel / serial conversion into a time-series signal by the multiplexer 33, and further generates a light control signal by a light emitting element 21 a arranged at a lateral end of the operation module 30. , And is converted into an optical data signal, and is incident on the optical transmission layer 24 (see FIG. 2) of the optical bus 23 in time series. The first optical address control signal in time series among the incident optical control signals is used to select a desired one of the plurality of memory modules 40.
Is specified. In the specified memory module 40,
The incident light control signal and optical data signal are converted into an electrical control signal and data signal by the light receiving element 22b arranged at the lateral end of the memory module 40, and further subjected to serial / parallel conversion by the demultiplexer 44. Thus, the multiplexed (parallel / serial converted) control signal and data signal are restored. An address of the memory 41 is designated by the restored parallel control signal, and a parallel data signal is input to the memory 41. In this way, the operation module 30 to the memory module 4
A plurality of bits of data are written in 0.

On the other hand, when data is read from the memory module 40 to the arithmetic module 30, a control signal is output from the CPU 31, and the data is read from the memory module 40 in the same manner as when writing data from the arithmetic module 30 to the memory module 40. Desired memory 4 of
Address 1 is designated, and a parallel data signal is output from the memory 41. The output data signal is input to the multiplexer 43, and the multiplexer 43
Is converted into parallel / serial data, and is further input as an optical data signal into the optical transmission layer 24 of the optical bus 23 via the light emitting elements 22a arranged at the lateral ends of the memory module 40. The input optical data signal is output to the arithmetic module 3
The signal is converted into an electric data signal via the light receiving element 21b arranged at the horizontal end of the line 0, and is converted into a serial / parallel signal by the demultiplexer 34 of the multiplex transmission circuit 32, and is taken into the CPU 31. In this manner, a plurality of bits of data are read from the memory module 40 to the arithmetic module 30.

Each of the memory modules 40,..., 40 is controlled by a control signal from the arithmetic module 30, and transmits and receives optical signals via the optical transmission layer 24 of the optical bus 23 as necessary. Such transmission and reception of optical signals are performed in parallel in each of the stacked optical transmission layers 24. here,
By synchronizing the transmission and reception timing of the optical signal via each optical transmission layer 24 with the optical clock signal given to one layer of the plurality of optical transmission path layers 24 stacked,
Optical signals transmitted and received via each optical transmission layer 24 are uniformly defined as parallel signals. In the present embodiment, the data bus width is 16 bits, and each layer of the stacked optical transmission layers is configured to correspond to 1 bit. Therefore, presentation of an address and transmission / reception of data are performed via 16 optical transmission layers. When the bus width is further increased, for example, when the data bus width is 64 bits, the optical transmission layer may be 64 layers. However, a configuration in which two or more bits correspond to one of the stacked optical transmission layers,
It is also possible to adopt a configuration in which two or more of the stacked optical transmission layers correspond to one bit.

In the bus module 20 of the present embodiment, since the signal transmitted between the arithmetic module 30 and the memory module 40 is transmitted as an optical signal, the transmission speed can be increased and a large number of memories can be connected. However, the increase in power consumption for transmission and the limitation on the transmission frequency are small, as in the configuration of the conventional bus wiring for transmitting electric signals. Therefore, high-speed data transmission and low power consumption are achieved. In the arithmetic device according to the present embodiment, since signals transmitted between the arithmetic module 30 and the plurality of memory modules 40 are serial signals, the bus between the arithmetic module 30 and the plurality of memory modules 40 is The connection across the module 20 is simplified.

FIG. 4 shows an arithmetic unit shown in FIG.
FIG. 6 is a diagram showing a comparison with characteristics of the configuration using the bus wiring shown in FIG. The items compared were the skew, transmission delay time, rise delay time due to rounding of the transmission waveform, power consumption, and bus width with respect to the number of mounted memories. Transmission bandwidth of 2 GByte /
sec. As is clear from FIG. 4, in the arithmetic device of the present embodiment, the power consumption and the bus width are very small as compared with the conventional bus wiring configuration, so that a low power consumption and compact connection can be realized. . If the number of memories is 4
When the number is as small as eight or eight, the skew, the transmission delay time, and the rising delay time due to the rounding of the transmission waveform in the conventional bus wiring are the rising due to the skew, the transmission delay time, and the rounding of the transmission waveform in the arithmetic unit of this embodiment. As compared with the delay time, the memory is small or equivalent, but as the number of memories increases to 40 or 160, the present embodiment is overwhelmingly small in any item, and therefore the number of memories increases. High-speed transmission can be performed.

In this embodiment, polymethyl methacrylate (PMMA) is used as the light transmission layer, but instead, polystyrene (PS), polycarbonate (PC)
It is also possible to use a plastic material having similar optical characteristics, such as. Even when polystyrene (PS) or polycarbonate (PC) is used as the light transmission layer, a fluorine-containing polymer can be used for the cladding layer.

In the present embodiment, the sheet thickness of each of the optical transmission layer and the cladding layer including the light shielding layer is set to 0.5 mm. However, as long as their optical characteristics are not impaired.
There is no problem if it is thicker or thinner. By forming each layer thin, an optical data bus having an extremely wide bus width is formed in a small space, and therefore, a data transmission rate can be dramatically improved.

Further, in this embodiment, the plastic material is used for the light transmission layer and the cladding layer. However, a quartz glass material can be used instead. When a quartz glass material is used, a sheet having a specific refractive index control is prepared using P ₂ O ₅ , Al ₂ O ₃ , B ₂ O ₃ or the like as a refractive index adjusting material, and a difference in refractive index difference is produced. A large combination is preferred.

Further, in the present embodiment, the optical elements 21 and 22 provided in the optical bus module 20 are optically directly coupled to the optical bus 23. However, an optical waveguide is formed in the optical bus module 20 to directly More specifically, a light emitting element or a light receiving element may be provided at the other end of the optical waveguide.

[0032]

As described above, according to the present invention,
Since the signal transmitted between the arithmetic module and the memory module is transmitted as an optical signal, compared to the configuration of the bus wiring for transmitting the electric signal, the power consumption for transmission is reduced and the data transmission speed is increased. Is achieved. Further, since the signal transmitted between the arithmetic module and the memory module is a serial signal, the connection between the arithmetic module and the memory module across the bus module is simplified.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of an arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a perspective view of the arithmetic unit shown in FIG.

FIG. 3 is an enlarged view showing a part of the arithmetic device shown in FIG. 2;

4 is a diagram showing a comparison between characteristics of the arithmetic device shown in FIG. 1 and a conventional bus wiring configuration shown in FIG. 5;

FIG. 5 is a diagram showing a configuration of a conventional bus line most commonly used.

FIG. 6 is a diagram showing a configuration of a bus wiring proposed in Japanese Patent Publication No. 5-507374.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Support substrate 11 Electric wiring 20 Optical bus module 21, 22 Optical element 21a, 22a Light emitting element 21b, 22b Light receiving element 23 Sheet optical bus 24 Optical transmission layer 25 Cladding layer 26, 27 Signal light input / output part 28 Light shielding layer 30 Arithmetic module 31 CPU 32, 42 Multiplexing transmission circuit section 33, 43 Multiplexer 34, 44 Demultiplexer 40 Memory module 41 Memory 50 Connector for module

Claims (3)

[Claims] An arithmetic module having a processor;
A bus module for performing data transmission between a plurality of memory modules having a memory accessed by the operation module, wherein a signal transmitted between the operation module and the memory module is transmitted as an optical signal. The bus module that features it. 2. A common transmission of an optical signal, wherein the bus module has a plurality of transmitting units each having a light emitting element for converting an input electric signal into an optical signal, and a sheet-shaped optical signal which diffuses and propagates the optical signal. The optical transmission unit according to claim 1, further comprising: an optical transmission unit that forms a path; and a reception unit that has a light receiving element that receives an optical signal transmitted through the optical transmission unit and converts the optical signal into an electric signal. Bus module. 3. An arithmetic module having a processor, a plurality of memory modules having a memory accessed by the arithmetic module, and a bus for transmitting a signal transmitted between the arithmetic module and the memory module as an optical signal. A plurality of transmission units each having a light emitting element for converting an input electric signal into an optical signal; and a common transmission of an optical signal, which is formed in a sheet shape and diffuses and propagates the optical signal. An optical transmission unit that forms a path, and a reception unit that has a light receiving element that receives an optical signal that has propagated through the optical transmission unit and converts the optical signal into an electric signal. Each of the memory modules converts a parallel signal into a serial signal and transmits the serial signal to the bus module. And Le conversion unit, the arithmetic apparatus characterized by comprising a serial-to-parallel converter for converting a serial signal transmitted from the bus module to a parallel signal.