JPH113859A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for efficiently processing a plurality of wafers by forming films, materials and so on of a semiconductor device on the wafers with reactive gas and then annealing. SOLUTION: A lower low-temperature portion, a high-temperature portion and an upper low-temperature portion are formed in a vertical furnace, and the lower low-temperature portion has a gain introducing means for flowing a reactive gas. And films, materials and so on are formed on a semiconductor wafer with the reactive gas at the lower low-temperature portion, the semiconductor wafer is then moved to the high-temperature portion and annealed, and a plurality of the semiconductor wafers are taken out of the furnace by lowering them after once transferring them to the above upper low-temperature portion. A separator with a face shape and dimension nearly equal to or greater than the semiconductor wafer is provided above the top of the semiconductor wafer so as to rise and fall following up a plurality of the semiconductor wafers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.
Using a reaction gas, a film, substance, etc. are formed on the wafer,
The present invention relates to a method of manufacturing a semiconductor device by annealing thereafter. The reactive gas refers to a gas which reacts to form a film or the like by itself or reacts with a semiconductor substrate to form a film or the like. The above method includes, for example, S
iH ₄ is pyrolyzed at 500 to 600 ° C. to 10 ⁻² to 10 ⁻³
After forming amorphous silicon or polysilicon by LP-CVD (low pressure vapor phase epitaxy) of torr, 600
There is a method of reforming into a larger polycrystalline film by annealing at ~ 800 ° C. When the vapor phase growth temperature and the annealing temperature are equal, the modification time becomes longer. In addition, after forming a SiO ₂ film by LP-CVD at about 700 ° C. using TEOS in the lower furnace, RTA (Rapid Thing) is performed in the upper furnace.
There is also a method of performing high-temperature heat treatment at 900 to 950 ° C. to densify the SiO ₂ film by thermal annealing.

2. Description of the Related Art HSG (hemispherical grain) polysilicon, which is an example of a material constituting a semiconductor device, has recently been attracting attention as an element of a highly integrated DRAM because it can increase the surface area of a DRAM stacked capacitor. (J. Appl. Phys. Lett. 58, 251 (19
91)). In this case, hemispherical grain polysilicon is formed on the amorphous silicon (a-Si) layer of the semiconductor substrate and annealing is performed.

[0003]

BACKGROUND ART HSG is one process SiH ₄ or Si ₂ H ₆ 100 to 300 Angstroms poly-Si nuclear storage polysilicon (530 ° C. of D-RAM for using on a-Si in the case of In the following, a process of selectively forming an amorphous silicon film for a capacitor by CVD and patterning the amorphous silicon film into a mushroom shape) is performed.
This is performed at a temperature of about 0 to 630 ° C., and then annealed in a high vacuum at 10 ⁻⁸ torr while increasing the temperature to about 750 ° C. to grow hemispherical crystals of a-Si around the nucleus to reduce the surface area. It can be enlarged 1.5 to 2.0 times. Conventionally, a series of these processes has been performed using a heater heating furnace from the back of the wafer. On the other hand, generally 5
Batch processing of 0 to 100 sheets / batch is also performed, and in this case, a series of processing is performed by heating in a vertical furnace.

[0004]

In the conventional batch processing, since the temperature change during a series of processes is constant,
In particular, the nucleus growth step takes time. That is, since the temperature cannot be increased in a wide range as in the case of one-sheet processing, the process window is narrow. Specifically, since the temperature cannot be set within a certain range, it is necessary to keep the temperature constant and extend the processing time.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and comprises forming a film, a substance, and the like constituting a semiconductor device on a plurality of wafers by using a reaction gas. In the method of manufacturing a semiconductor device by annealing the same, the same processing as the one-sheet processing is performed,
Using a vertical furnace equipped with gas introduction means for flowing a reaction gas to a lower low-temperature section of a vertical furnace having a low-temperature section, a high-temperature section, and a low-temperature section in an upward direction from the bottom, the lower-temperature section uses the reaction gas. The film, material, etc. are formed on a plurality of semiconductor wafers, and then the semiconductor wafer is moved to a high-temperature portion to perform annealing, and once the plurality of semiconductor wafers are moved to the upper low-temperature portion, the wafer is lowered. It is characterized by being taken out of the furnace. Further, instead of the vertical furnace having the low temperature section, the high temperature section, and the low temperature section from above to below, a horizontal furnace having the low temperature section, the high temperature section, and the low temperature section from one end to the other end is used. Process can be performed. One embodiment of the process window expansion will be described below.

[0006]

[Table 1] Constant temperature heat treatment Temperature profile Heat treatment specific heat amount Low temperature part High temperature part temperature Qp / Qc (° C) (° C) (° C) 600 600 650 About 5 600 600 700 About 25 600 600 750 About 125

In Table 1, the temperature profile heat treatment corresponds to the method of the present invention. In Table 1, the heat treatment is performed while moving the wafer from the low-temperature part to the high-temperature part for the same amount of time as the heat quantity (Qc) when the heat treatment is performed at 600 ° C. for a predetermined time. Is performed, the amount of heat (Qp) received by the wafer is shown as a ratio (Qp / Qc). In order to achieve the same heat amount in both heat treatments and achieve the same heat treatment effect, the heat treatment time corresponding to the reciprocal (Qc / Qp) of the specific heat amount can be shortened. Therefore, the effect of greatly shortening the processing time can be brought about by including an element for heating the wafer in a short time.

Further, as described with reference to FIG.
Various heat treatments are possible by changing the temperature and width of the high temperature part and the moving speed of the wafer. FIG. 1 shows an example in which the high temperature portion temperature width (AB) is narrow, the high temperature portion temperature width (AC) is wide, the high temperature portion temperature is high, and the temperature width is narrow. , AB corresponds to a high-temperature portion, BC corresponds to an upper low-temperature portion, in, AC corresponds to an upper low-temperature portion,, AB corresponds to a lower low-temperature portion, and DE corresponds to a high-temperature portion. An example in which the moving speed is doubled when a wafer is moved at a constant speed in a heating furnace having the above temperature profile will be described. First, a case where the temperature profile is moved at a constant speed (V) and a case where the temperature profile
Comparing the case of moving at double speed, the amount of heat applied to the wafer is equal. Therefore, the length of the high-temperature portion can be reduced by adjusting the moving speed of the wafer. next,
FIG. 2 shows a heat treatment pattern applied to the wafer when the speed is set to a constant speed (V), a double speed (2 V), and a triple speed (3 V) in the temperature profile. 3x speed (3
Although it is difficult to set such a steep temperature distribution as in V) by adjusting the heat insulating material of the furnace, the present invention easily and effectively adjusts the wafer movement speed to such a steep temperature distribution. To adjust the amount of heat applied to the wafer.

The upper low-temperature portion has a low temperature, preferably approximately the same temperature as the lower low-temperature portion or a lower temperature, in order to suppress impurity diffusion after annealing. By advancing the wafer from the high-temperature portion to the upper low-temperature portion, the progress of crystallization is accelerated, and the same amount of heat can be applied to the wafer in each batch. Thereafter, the wafer is rapidly drawn out of the furnace through the high temperature part and the lower low temperature part.
When the reaction gas is a CVD gas, it is preferable to exhaust the reaction gas from the lower part of the high temperature part or the upper part of the lower low temperature part because particles generated by the reaction between the gases contaminate the upper furnace. Further, instead of a vertical furnace having a low-temperature part, a high-temperature part and a low-temperature part from below to above, a horizontal furnace having a low-temperature part, a high-temperature part and a low-temperature part from one end to the other end is similarly used. The method of the present invention can be performed. In a horizontal furnace, the wafer moves laterally,
Of course, the exhaust port is preferably located at the other end of the furnace at the ground contact position. Hereinafter, an embodiment of an apparatus for performing the method of the present invention will be described.

[0010]

FIG. 3 shows a vertical furnace and a temperature profile in a furnace according to an example of an apparatus for carrying out the method of the present invention. This apparatus basically includes a lower furnace 10 for producing a low temperature part and an upper furnace 2 for producing a high temperature part.
0, a vacuum evacuation system 30 and a wafer elevating device 40. The high temperature part is located above the lower furnace 10 and / or the upper furnace 2.
Created at the bottom of 0. Hereinafter, these components will be described in order.

The lower furnace 10 is common to the upper furnace 20 and uses a heat insulating material to heat a heater 2 provided to surround the outer periphery of a normal 10 to 11 inch quartz reaction tube 1 (for processing an 8 inch wafer). Is fixed to the furnace body 10a
The wafers 3 stacked in multiple stages and with a distance of 15 to 35 mm therebetween are heated to a predetermined temperature. The quartz reaction tube 1 is fixed to a support base 4 via a bracket 5 at a lower end portion bent in an L shape. Si ₂
A reaction gas introduction pipe 7 such as H ₆ is fixed to the lower furnace 10 below the lower end of the quartz reaction pipe 1. The reaction gas introduction pipe 7 is provided with a heater (not shown) immediately before the lower furnace 10 to heat the gas to about 300 ° C. 6
Is an inner tube provided for forming a reaction gas introduction path.

The reaction gas blown out from the reaction gas introduction pipe 7 passes between the wafers 3 and precipitates nuclei on a-Si when SiH ₄ is used, and SiO ₂ when TEOS is used. A film is formed, and then the air is exhausted. This reaction gas is preferably discharged from the high temperature section 25 or the upper part of the lower furnace 10 so as not to flow into the upper furnace 20 and become particles. In FIG. 3, the reaction gas is exhausted from the upper part of the lower furnace 10. A reaction gas exhaust pipe 8 provided for evacuation has an opening in an annular space between the inner tubular upright tube wall 6 and the quartz reaction tube 1. Reference numeral 9 denotes a separator which prevents a reactive gas for nucleation (seeding) or other film formation from blowing up to cause particles, and has a surface shape almost equal to or larger than that of a wafer. It has dimensions.

The upper furnace 20 comprises a quartz reaction tube 1, a furnace body 20a made of a heat insulating material, and a heater 21, similarly to the lower furnace 10, and the upper ceiling of the quartz reaction tube 1 has a vacuum exhaust system. The suction port 1a is connected to the suction port 1a.
In order to increase the efficiency of reducing the pressure inside the reaction tube to a desired degree of vacuum and to increase the evacuation speed, in a vacuum evacuation system including pipes having dimensions substantially the same as the diameter of a ready-made flange, the space to be evacuated (upper furnace) It is preferable that the distance between the vacuum pump and a high vacuum pump such as a molecular pump is as short as possible. Since the space between the upper furnaces 20 has no wafer in the state shown in the figure and the gas flows upward, the position of the suction port 1a shown in the figure greatly enhances the exhaust efficiency. Further, the upper exhaust and the heat radiation from the thick exhaust pipe at the upper part of the reaction tube make it possible to sharply lower the temperature of the upper low-temperature portion to a desired temperature.

[0014] In the case of HSG production, the evacuation system 20 moves the inside of the furnace at 10 ^-2 to 10 ^-3 ton at the time of seeding.
evacuated to rr, 10 of the furnace at the time of annealing ^-7 to 1
This is a mechanism including a pipe, a check valve, a vacuum pump, and the like provided for evacuating to 0 ^-8 torr. 10 above
^{At -7} to 10 ^-8 torr, the gas flow becomes a molecular flow. Therefore, in order to shorten the piping and increase the pumping speed, a vacuum exhaust port is provided at the top of the furnace, and the inner diameter of the piping is set to 150 mm.
Advantageously it is ~ 200 mm. Numeral 36 denotes a valve for introducing a carrier gas or a reaction gas into the reaction tube, which is used, for example, for introducing NO, NH ₃ or the like for modifying the film quality at the time of annealing after the formation of the SiO ₂ film. Reference numeral 37 denotes a purge gas introduction valve. Reference numerals 31 and 32 denote flanges for fixing the tubes, respectively, and reference numeral 33 denotes a length adjusting buffer portion.
In the pipe 34, a main valve 35 generally using a gate valve, a check valve (not shown), a turbo molecular pump, a control valve, a dry pump, and the like are sequentially provided in order from the side near the furnace.

As described above, by providing the low-temperature portion, the high-temperature portion, and the low-temperature portion in order from the bottom, all the wafers are heated under the same condition while the wafers of the batch pass these portions in one direction at a constant speed. Since the high-temperature portion is not a region for heat-treating a stopped wafer but a region for heat-treating a wafer moving at a low speed, the configuration may be such that there is almost no constant-temperature portion as shown in the figure. However, if the entire height of the heat treatment furnace can be large to some extent, it is of course better to provide a long flat zone at a constant temperature for better accuracy and stability.

Subsequently, the wafer elevating device 40 mounts the wafer 3 on a T-shaped jig 41 on which a separator 42 is fixed.
Are supported by shelves arranged vertically above and below, and are known, for example, from Japanese Patent Application Laid-Open No. Hei 9-17739 (FIGS. 8 and 9) of the present applicant. A magnet or a coil 44 is attached to the lower end of the T-shaped jig 40, and another magnet or a coil 45 that exerts an attractive magnetic force on the magnet 44 is provided so as to be movable up and down. It is moved into the furnace 20 and, conversely, lowered. In order to enable such ascent and descent, a base 46 supporting a magnet 45 and the like is screwed with a rod 47 rotated by a driving device (not shown). Reference numeral 43 denotes a furnace bottom structure which constitutes a bottom portion 43a of the heating furnace and also serves as a tube for guiding the elevation of the T-shaped jig 41. The furnace bottom structure 43 is air-tightly fixed at the position shown in the drawing during the heat treatment of the wafer, and is raised and lowered by rotating a rod 48 screwed to the support 49 before and after the heat treatment. The support 4
Numeral 9 is fixed to the upper horizontal portion 43a of the furnace bottom structure 43, and rotatably fits the upper end of the rod 47.

FIG. 3 shows a temperature profile in the furnace on the left side. This maximum temperature is generated in the lower part of the upper furnace 20, which can be achieved by making the heat generated in the upper part of the heater 21 smaller than that in the lower part. However, as described above, the effect of correcting the temperature distribution by the exhaust action is large.

Next, the method of the present invention will be described with reference to FIG. 3 by taking an example of forming an SiO ₂ film by TEOS. First, the valves attached to the pipes 7 and 8 are shut off, the main valve 35 attached to the pipe 34 is opened, and the inside of the furnace is evacuated by operating the turbo molecular pump and the drain pump. Thereafter, the main valve 35 is shut off, and a N ₂ carrier gas flows at a flow rate of 5 to 20 L / min from the reaction gas introduction pipe 7 and is exhausted from the reaction gas exhaust pipe 8. At the same time as the exhaust, the heaters 2 and 21 are energized to create the temperature profile shown in FIG. Subsequently, as shown in FIG. 3, an 8-inch Si wafer 3 is placed in a furnace, and when the wafer 3 is heated to 690 ° C., N
_{(2) The} gas is exhausted such that the flow rate of the gas is reduced to 100 mL / min and the pressure in the reaction tube is maintained at 0.5 Torr.

While maintaining the flow rate of the N ₂ gas, TEOS is supplied from the reaction gas introduction pipe 7 and the SiO ₂ growth rate is set to 100 to 100%.
The flow is performed at a flow rate of 150 angstroms / min, and when a desired film thickness is grown, the gas source is switched so that only N ₂ gas flows, and the reaction is stopped. Enough T
After purging the EOS, the wafer 3 is moved to the upper furnace 20 at a desired speed, passed through a region of 920 ° C., annealed, and further raised to a lower temperature region. Then, it is moved to the lower furnace 10 quickly. Thereafter, the wafer 3 is taken out of the reaction furnace.

Next, the difference between the example of the HSG and the formation of the SiO ₂ film will be described. (1) lower furnace temperature -550 ° C. (2) the upper furnace temperature -720 ° C. (3) treatment conditions N ₂ gas in the lower furnace 200 mL / min, then N _2, the He or A
r (preferably adding about 2% H ₂ ) to 100 mL / m
Exhaust to 10 ⁻³ Torr while flowing in. afterwards,
Polysilicon having a thickness of 100 to 300 Å is deposited on the surface of the storage amorphous silicon while evacuating SiH ₄ + 30% He at a flow rate of 80 to 180 mL / min to 10 ⁻³ Torr. (3) Processing Conditions in Upper Furnace The piping 34 is evacuated so that a furnace pressure of 10 ^-8 Torr is achieved.

[0021]

As described above, according to the method of the present invention, a film can be formed on a large number of wafers with high efficiency.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of heat treatment in a heat treatment furnace having a temperature profile of the present invention.

FIG. 2 is a view showing a heat treatment history when a wafer moving speed is changed to a constant, twice, and three times in the furnace having the temperature distribution of FIG.

FIG. 3 is a sectional view of a vertical furnace for carrying out the method of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Quartz reaction tube 2 Heater 3 Wafer 4 Support base 6 Inner tube upright tube wall 7 Reaction gas introduction tube 8 Reaction gas exhaust tube 9 Separator 10 Lower furnace 20 Upper furnace 21 Heater 30 Vacuum exhaust system 31, 32 Flange 33 Buffer unit 34 Piping 35 Main valve 40 Wafer elevating device 41 T-shaped jig 42 Separator 43 Furnace bottom structure 44 Magnet or coil 45 Magnet or coil 46 Support base

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device by forming a film, a material, and the like constituting a semiconductor device on a wafer using a reaction gas and performing subsequent annealing, wherein a low-temperature portion, a high-temperature portion, Using a vertical furnace equipped with gas introduction means for flowing a reaction gas to a lower low temperature section of a vertical furnace having a low temperature section, the film, the substance, and the like are formed on a plurality of semiconductor wafers by the reaction gas in the lower low temperature section. Forming, then moving the semiconductor wafer to a high-temperature portion to perform annealing, once moving the plurality of semiconductor wafers to the upper low-temperature portion, and then lowering the semiconductor wafer and taking it out of the furnace. Production method. 2. A method according to claim 1, wherein a separator having substantially the same or larger surface shape and size as the semiconductor wafer is provided above the uppermost semiconductor wafer so as to move up and down following the plurality of semiconductor wafers. Item 2. A method for manufacturing a semiconductor device according to Item 1. 3. The temperature of the upper low-temperature part is substantially the same as or lower than the temperature of the lower low-temperature part.
The manufacturing method of the semiconductor device described in the above. 4. The method of manufacturing a semiconductor device according to claim 1, wherein annealing is performed while exhausting air from an exhaust system provided at an upper part of the vertical furnace. 5. The furnace according to claim 1, wherein a purge gas is supplied into the furnace from an air supply system provided at an upper part of the vertical furnace.
4. The method for manufacturing a semiconductor device according to claim 1, wherein 6. The method according to claim 1, wherein a reaction gas is supplied from an air supply system provided at an upper portion of the vertical furnace during the annealing to perform a reaction simultaneously with the annealing. 13. The method for manufacturing a semiconductor device according to claim 1. 7. The method according to claim 1, wherein the reaction gas is a CVD gas, and the reaction gas is exhausted from a lower part of the high temperature part or an upper part of the lower low temperature part. Of manufacturing a semiconductor device. 8. The reaction gas is a gas that reacts with a semiconductor substrate to form the film, the substance, and the like, and the reaction gas is exhausted from a lower part of the high temperature part or an upper part of the lower low temperature part, or 7. The method for manufacturing a semiconductor device according to claim 1, wherein exhaust is performed from an exhaust system provided at an upper part of the vertical furnace, or both exhausts are performed simultaneously. 9. A horizontal furnace having a low temperature section, a high temperature section, and a low temperature section from one end to the other end is used instead of a vertical furnace having a low temperature section, a high temperature section, and a low temperature section from below. A method for manufacturing a semiconductor device, comprising performing the method according to any one of claims 1 to 8.