JPH11355130A - Bit synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To bit-synchronize an input data signal with an external clock signal. SOLUTION: A signal delayed by a variable delay circuit 1 is branched into plural delay signals having different delay times by a fixed delay circuit 2, the respective delay signals obtained in the fixed delay circuit 2 are latched in a data latch circuit 3 by an external input clock signal CK, the respective latched signals are compared in phase by a phase comparing circuit 4, a control circuit 11 generates a signal which indicates the phase relation of an output data signal with the external input clock signal CK from the phase comparison result, a counter 12 executes counting-up or down by the output signal of the control circuit 11 and the delay time of the variable delay circuit 1 is changed- over. The output data signal is obtained from the output of the data latch circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization circuit for receiving a burst signal.

[0002]

2. Description of the Related Art As a conventional bit synchronization circuit of this kind,
There is a circuit shown in FIG. In FIG. 4, reference numeral 1 denotes a variable delay circuit which converts an input data signal into n types of delay times T1.
... Tn. Reference numeral 2 denotes a fixed delay circuit, which receives the data signal delayed by the variable delay circuit 1 and delays k different data signals by a predetermined different delay time within a bit period (the delay amount is Qi < Q (i + 1)). Reference numeral 3 denotes a data latch circuit, which simultaneously latches and outputs k data signals input from the fixed delay circuit 2 in response to an external input clock signal CK. One of the plurality of latched data signals becomes an output data signal. Reference numeral 4 denotes a phase comparison circuit that compares the phases of k data signals output from the data latch circuit 3 and outputs m phase comparison signals indicating the comparison result. Reference numeral 5 denotes an m-input OR circuit, which takes a logical sum of m phase comparison signals output from the phase comparison circuit 4. Reference numeral 6 denotes a counter for counting the output “1” pulse of the m-input OR circuit 5. The counter outputs the count signal in n bits and sends it to the variable delay circuit 1 as a delay time selection control signal. 7, a data input terminal; 8, an external clock input terminal; and 9, a data output terminal.

In this circuit, k delayed data signals output from a fixed delay circuit 2 are latched by a data latch circuit 3 by a clock signal CK. When this is detected, a "1" pulse is generated from the m-input OR circuit 5, and the counter 6 performs a counting operation by the pulse to switch the delay time of the variable delay circuit 1 to another delay time. This operation is performed until the count contents of the counter 6 are continuously updated until each of the latch signals coincides with "1" or "0". Each time, the delay time of the variable delay circuit 1 is changed by another time. Is switched to. When each latch signal matches “1” or “0”, that is, all of the delayed data signals output from the fixed delay circuit 2 are clock signals CK.
, The phase comparison result of the phase comparison circuit 4 indicates the same phase, and no pulse is generated from the m-input OR circuit 5. As a result, the counter 6 does not operate, the variable delay circuit 1 maintains the delay time at that time, and a data signal synchronized with the clock signal CK can be obtained from the terminal Qj of the data latch circuit 3.

[0004]

However, in this bit synchronization circuit, the "jitter +
When the time of “setup time + hold time” is long, the counter 6 operates in the same direction, and there is a problem that the counter 6 easily malfunctions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit synchronization circuit which can realize more stable bit synchronization.

[0006]

According to a first aspect of the present invention, there is provided a variable delay circuit for delaying an input data signal by one delay time selected from a plurality of delay times, A fixed delay circuit for branching the signal delayed by the delay circuit into a plurality of delay signals having different delay times within a bit period, and a data latch circuit for latching each delay signal obtained by the fixed delay circuit with an external input clock A phase comparison circuit that compares phases of respective output signals of the data latch circuit, and a control circuit that generates a signal indicating a phase relationship between the data output signal and the external input clock based on the output signal of the phase comparison circuit. An up-down counter that counts up or down according to an output signal of the control circuit and outputs a signal that selects a delay time of the variable delay circuit. It was configured to use one output signal of the data latch circuit as the signal.

According to a second aspect, in the first aspect, the control circuit includes means for shaping a waveform of a signal output to the up / down counter by the external input clock.

[0008]

[First Embodiment] FIG. 1 is a diagram showing a bit synchronization circuit according to a first embodiment of the present invention. A variable delay circuit 1 for delaying input data by a specific delay time selected from n kinds of delay times T1 to Tn, and a data signal delayed by the variable delay circuit 1 K delayed data signals (delayed by Qi <Q (i +
A) a fixed delay circuit 2 for generating 1)), a data latch circuit 3 for simultaneously latching and outputting k data signals input from the fixed delay circuit 2 by an external input clock signal CK,
The phase comparison circuit 4 that compares the phases of k data signals output from the data latch circuit 3 and outputs m phase comparison signals indicating the comparison result is the same as that shown in FIG. Is the same.

In this embodiment, the control circuit 11 and the n-bit up / down counter 1
2 is connected, and the delay time of the variable delay circuit 1 is selected by the n-bit output of the up / down counter 12.

The phase comparison circuit 4 compares any two of the inputs I1 to Ik, and outputs the result of the comparison as m signals. The control circuit 11 determines Ii ≠ Ij (i ≦ m, j) by the combination of the m output signals.
≦ m, i ≠ j), QUP = “1”, QDW = “0”, or QUP = “0”, QDW = “1”. The up / down counter 12 adds 1 to n-bit binary data when IUP = "1" and IDW = "0", and n-bit binary data when IUP = "0" and IDW = "1". Subtract 1 from the data.

First, when the data output signal Qj output to the data output terminal 9 does not coincide with a signal (for example, Q (j-1)) having a smaller delay amount by the fixed delay circuit 2, the output signal Qj Output from the control circuit 11 is QUP = “1” and QDW =
It becomes "0" and the counter 12 counts up. Conversely, the data output signal Qj output to the data output terminal 9 is
When the output signal Qj does not coincide with a signal (for example, Q (j + 1)) having a larger delay amount due to the fixed delay circuit 2, it is determined that the phase of the output signal Qj is behind the clock signal CK. The output becomes QUP = "0", QDW = "1",
The counter 12 counts down. Variable delay circuit 1
Increases the delay amount when the counter 12 counts up and decreases the delay amount when the counter 12 counts down.
The signal obtained at the data output terminal 9 is a clock signal
The phase relationship with CK changes to a good state.

FIG. 2 is a diagram showing a specific circuit configuration when k = 3, m = 2, and n = 2 in the bit synchronization circuit shown in FIG. The variable delay circuit 1 includes a delay element 101,
102, 103, and 2-1. In this circuit, the selectors 104 and 105 form a delay time T3 in which all three delay elements 101 to 103 are connected in series, a delay time T2 in which two of them are connected, and one of them. Is connected to the delay time T
One form is selected from the four forms of the form 1 and the form of the delay time 0 in which no delay element is connected. T3> T2
>T1> 0. Note that the maximum delay time T3 is not limited to within a bit period.

The fixed delay circuit 2 includes two delay elements 20
1, 202, the individual delay elements 201, 20 of which
The delay time of 2 is substantially equal to Tc when the bit period is Tc.
/ 3.

The data latch circuit 3 comprises three master-slave type DFF circuits 301 to 303. The DFF circuit 301 latches an output signal of the variable delay circuit 1 with a clock signal CK, and the DFF circuit 302 is a fixed delay circuit 2 The signal delayed by the delay element 201 is latched with the clock signal CK, and the DFF circuit 303
The signal delayed at 1202 is latched by the clock signal CK.

The phase comparison circuit 4 comprises EXOR (exclusive OR) circuits 401 and 402. One EXOR circuit 401 outputs "1" only when the outputs of the DFF circuits 301 and 302 do not match, and the other EXOR circuit 401 outputs the "1". The circuit 402 is D
"1" is output only when the outputs of the FF circuits 302 and 303 do not match.

The control circuit 11 is a circuit that outputs an input signal as it is. The counter 12 is a 2-bit counter, and its outputs Q1 and Q2 are output from the selector 10 of the variable delay circuit 1.
4 and 105 as control signals.

Next, the operation will be described. First, "1000100010001000100
It is assumed that data having a preamble pattern of “0100010001000” at the beginning is input.

The variable delay circuit 1 switches its delay time according to the 2-bit count value (Q1, Q2) of the counter 6. That is, when Q1, Q2 = "1", "1", the delay element 1
01 to 403 are not selected and the delay time is set to 0. When Q1 and Q2 are “1” and “0”, only the delay element 101 is selected and the delay time is set to T1, and Q1 and Q2 =
In “0” and “1”, the delay elements 102 and 103 are selected and the delay time is set to T2, and Q1, Q2 = “0”, “0”
Then, the delay elements 101 to 103 are selected and the delay time T
Set to 3.

The output of the variable delay circuit 1 is
, Three types of signals having different delay times (a delay amount of 0,
(Approximately Tc / 3, approximately 2Tc / 3), of which the signal with delay time 0 is latched by the DFF circuit 301,
A signal having a delay time of approximately Tc / 3 is latched by the DFF circuit 302, and a signal having a delay time of approximately 2Tc / 3 is latched by the DFF circuit 303. The output signals of the DFF circuits 301 and 302 are compared by the EXOR circuit 401. If the two signals are different, “1” is output.
The EXOR circuit 402 compares the output signals of the signals 303 and 303. If the two signals are different, "1" is output. That is, the data output to the output terminal 9 among the three of the fixed delay circuit 2 at the timing of the cycle of the clock signal CK is compared with data having a smaller delay amount and data having a larger delay amount.

When the output of the EXOR circuit 401 is "1" and E
The output of the XOR circuit 402 is “0” when the output data obtained at the output terminal 9 is advanced with respect to the clock signal CK. At this time, the counter 12 counts up by one, and the delay amount in the variable delay circuit 1 increases by one stage. In this way, the delay amount increases step by step, and when the output signals of the EXOR circuits 401 and 402 both become “0”, the delay becomes stable.

On the other hand, when the output of the EXOR circuit 401 is 0,
When the output of the EXOR circuit 402 is “1”, the output data obtained at the output terminal 9 is behind the clock signal CK. At this time, the counter 12 counts down by one, and the delay amount in the variable delay circuit 1 becomes one.
It becomes smaller only by the step. In this way, when the delay amount decreases by one stage and the output signals of the EXOR circuits 401 and 402 both become “0”, the delay becomes stable.

As described above, finally, the counter 12 stops and the bit synchronization is established.

[Second Embodiment] FIG. 3 shows a control circuit 11 shown in FIG.
It is replaced with a control circuit 11 'constituted by 1102. The DFF circuits 1101 and 1102 are EXOR
A signal output from the circuits 401 and 402 is a clock signal CK.
And then input to the counter 12. As a result, the output signals of the EXOR circuits 401 and 402 are held for one cycle of the clock signal CK, and after the output signals are shaped and phase-matched, the counter 1
2, the operation becomes stable. Others are the same as the circuit of FIG.

[0024]

As described above, according to the first aspect, the counter is counted up or down based on the phase comparison result between the external input clock signal and the delayed data signal.
Since the delay amount of the delay data signal is adjusted, the input data can be bit-synchronized with the clock accurately and at high speed. Further, according to the second aspect, the output signal of the phase comparison circuit is input to the counter in a state where the waveform is shaped and the phase is matched, so that the operation is stabilized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bit synchronization circuit according to a first embodiment.

FIG. 2 is a specific circuit diagram of the bit synchronization circuit of FIG.

FIG. 3 is a block diagram of a bit synchronization circuit according to a second embodiment.

FIG. 4 is a block diagram of a conventional bit synchronization circuit.

[Explanation of symbols]

1: variable delay circuit, 2: fixed delay circuit, 3: data latch circuit, 4: phase comparison circuit, 5: m input OR circuit, 6:
n-bit counter, 7: data input terminal, 8: external clock input terminal, 9: data output terminal, 11, 11 ': control circuit, 12: n-bit up / down counter.

Claims (2)

[Claims] A variable delay circuit for delaying an input data signal by one delay time selected from a plurality of delay times, and a signal delayed by the variable delay circuit having a different delay time within a bit period. A fixed delay circuit for branching into a plurality of delay signals; a data latch circuit for latching each delay signal obtained by the fixed delay circuit with an external input clock; and a phase comparison circuit for comparing the phase of each output signal of the data latch circuit A control circuit for generating a signal indicating a phase relationship between a data output signal and the external input clock based on an output signal of the phase comparison circuit; An up / down counter for outputting a signal for selecting a delay time of a circuit, wherein one output signal of the data latch circuit is used as the data output signal. Bit synchronization circuit according to claim Rukoto. 2. The bit synchronization circuit according to claim 1, wherein said control circuit comprises means for shaping the waveform of a signal output to said up / down counter by said external input clock.