JPH11354665A - Package substrate and semiconductor device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount a multiple kinds of semiconductor chip with respect to a kind of package substrate, by a method wherein a plurality of external electrode pads are disposed surrounding a center part of a package base, and a plurality of power source pads and a grounding pad are arranged in each side in a periphery of the external electrode pad. SOLUTION: A plurality of external electrode pads 4 are disposed surrounding a center part of a surface of a square package base 2 on a package substrate 1, and a plurality of power source pads 5 disposed physically apart on the surface and a plurality of grounding pads 6 disposed physically apart on the surface are disposed in each side in a periphery of the external electrode pad 4. For this reason, even in semiconductor chips 11 of various modes, the same package substrate 1 is applicable and a multiple species of semiconductor chip 11 can be mounted with respect to a kind of package substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package substrate and a semiconductor device using the same, and more particularly, to a package substrate on which a variety of semiconductor chips can be mounted on one kind of package substrate and a semiconductor device using the same. Things.

[0002]

2. Description of the Related Art The present inventors have studied a package substrate and a semiconductor device using the same. The following is a technique studied by the present inventors, and the outline is as follows.

That is, a recent LSI (Large Scale In)
In a semiconductor integrated circuit device such as an integrated circuit, when used in a workstation or a personal computer, it is necessary to improve the performance and increase the number of pins, so that a BGA (Ball Grid Array) or a CSP (Chip Size) is required.
Package).

In this case, in a BGA (Ball Grid Array) substrate, an LSI is provided at the center of a square BGA substrate.
(Large Scale Integrated Circuit) and other semiconductor chips are mounted, and the bonding pads of the semiconductor chips (electrical terminals on the chip) are bonded to the pads of the BGA board (pads set at the ends of each side of the BGA board) They are electrically connected by wires.

As a document describing a BGA type package as an LSI package, for example, see “Nikkei Electronics August 2, 1993,” p.
04.

[0006]

However, the aforementioned B
When using a conventional package substrate such as a GA substrate,
If the arrangement structure of the power supply bonding pads and the ground bonding pads of the semiconductor chip is different because the package substrate corresponding to the arrangement structure of the power supply bonding pads and the ground bonding pads of the semiconductor chip can only be used. It is necessary to use a package substrate corresponding to the arrangement structure of the power supply bonding pads and the ground bonding pads.

Therefore, various semiconductor chips have various modes of arrangement of power supply bonding pads and ground bonding pads, so that power supply bonding pads and ground bonding pads of various semiconductor chips are provided. Since it is necessary to prepare a package substrate corresponding to the arrangement structure, it is necessary to prepare many package substrates having different arrangements of the power supply pad and the ground pad.

[0008] Therefore, since the semiconductor chip and the package substrate correspond one-to-one, it is necessary to use a package substrate corresponding to the type of the semiconductor chip for each type of semiconductor chip. However, there is a problem that the package substrate is expensive.

It is an object of the present invention to provide a package substrate on which a variety of semiconductor chips can be mounted on one type of package substrate, and a semiconductor device using the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, (1) In the package substrate of the present invention, a plurality of external electrode pads are arranged around the center of the surface of the rectangular package base, and each side around the external electrode pad is provided on each side. A plurality of power supply pads and a plurality of ground pads are arranged.

(2) The semiconductor device of the present invention is characterized in that (1)
A semiconductor chip having bonding pads as external electrodes or a semiconductor chip having bumps as external electrodes is mounted on the surface of the package substrate using the package substrate described above.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIG. 1 is a schematic plan view showing a package substrate according to a first embodiment of the present invention in a see-through manner. FIG. 2 is a schematic sectional view showing a section taken along the line AA in FIG.

As shown in FIGS. 1 and 2, the package substrate 1 of the present embodiment is a BGA substrate, and solder balls (balls) 3 as external terminals are arranged on the back surface of a rectangular package base 2. Is what it is. In addition,
As another aspect of the package substrate 1 of the present embodiment, the present invention can be applied to package substrates having various structures such as those having a package substrate structure in which the solder balls 3 are converted into pin wires in an electric wire state.

In the package substrate 1 of this embodiment, a plurality of external electrode pads 4 are arranged around a central portion (chip mounting area) of the surface of a rectangular package base 2. A plurality of power supply pads (hereinafter, also referred to as island-like power supply pads) 5 which are physically separated from each other on each side in the periphery of the surface, and a plurality of power supply pads which are physically separated from each other on the surface. It is characterized in that a plurality of ground pads (hereinafter also referred to as island-shaped ground pads) 6 are arranged. The spacing between the power supply pads 5 may be uniform or non-uniform. In FIG. 1, in the power supply pad 5, the dimension in the circumferential direction of the package base 2 is longer than the dimension in the direction perpendicular thereto, but the relationship between the dimensions may be reversed. That is, the dimension along the extending direction of the plating wiring 7 is shorter than the dimension in the vertical direction. Thus, the plating wiring 7 arranged between the adjacent power supply pads 5 can be arranged with a margin, and
It does not impair the wire bonding properties described below. Further, the power supply pad 5 may be formed in a square shape or another shape. The same can be said for the ground pad 6. The power supply pads 5 and the ground pads 6 are alternately arranged. However, it is not limited to being alternately arranged.

The method for manufacturing the power supply pad 5 and the ground pad 6 is based on a manufacturing process (for example, aluminum) in which the main body of the external electrode pad 4 (the pad before forming the plating film) is formed on the surface of the package base 2. After the layers are deposited, a manufacturing step of forming a patterned pad using lithography and selective etching techniques) and a patterned island-like power supply pad 5 and an island-like ground A pad 6 is formed.

Further, in the package substrate 1 of the present embodiment, the plating wiring 7 electrically connected to the external electrode pad 4 is formed in a region between the adjacent power supply pad 5 and ground pad 6. It is characterized in that it is also arranged.

The wiring 7 for plating electrically connects the plug 8 embedded in a through hole (connection hole) provided in the center of the package base 2 and the pad 4 for external electrodes. It is also arranged from the electrode pad 4 to the end of each side of the package base 2.

In this case, the plating wiring 7 and the plug 8 at the center of the package base 2 are shown only on the left side in FIG. 1 and are not shown on the right side, upper side, and lower side in FIG. Although not shown in the figure for simplicity), plating wirings 7 and plugs 8 are also arranged on the right side, upper side, and lower side in FIG.

In the manufacturing process of the external electrode pad 4, for example, a metal film made of, for example, a gold film or a copper film is formed on the surface of the pad formed by patterning an aluminum layer by an electrolytic plating method. This is a wiring used when applying a voltage to the pad when forming by.

In the package substrate 1 of the present embodiment, the ground wiring layer 10
Are formed. The ground wiring layer 10 is
It is electrically connected to the plug 8 embedded in the through hole. In this case, the solder ball 3 is also electrically connected to the central portion of the package base 2, that is, the region where the semiconductor chip is mounted, in order to improve the heat transfer property and stabilize the ground wiring layer 10 having the inner layer structure. The ground wiring layer 10 is provided. The method of manufacturing the ground wiring layer 10 is similar to the manufacturing process of forming a signal wiring layer made of, for example, a copper layer below or above an insulating film in the process of manufacturing the package base 2. A patterned ground wiring layer is formed.

In this case, the upper part of the plug 8 is electrically connected to the ground pad 6, and the lower part of the plug 8 is connected to the solder ball via the wiring layer 9 formed on the back surface of the package base 2. 3 is electrically connected. Note that a signal wiring layer is formed on the package base 2 and is insulated from the ground wiring layer 10 by an insulating film. In FIG. The illustration of the insulating film is omitted.

According to the package substrate 1 of the present embodiment, a plurality of external electrode pads 4 are arranged around the center of the surface of the rectangular package base 2, Since the package substrate 1 has a plurality of power supply pads 5 and a plurality of ground pads 6 on each side, as described later,
Since the same package substrate 1 can be applied to various (various aspects) semiconductor chips 11, the package substrate 1 on which various kinds of semiconductor chips 11 can be mounted on one type of package substrate 1 can be obtained. .

According to the package substrate 1 of the present embodiment, the plating wiring 7 electrically connected to the external electrode pad 4 is formed in the area between the adjacent power supply pad 5 and ground pad 6. In the manufacturing process of the external electrode pad 4, for example, a metal film made of, for example, a gold film or a copper film is coated on the surface of the pad formed by patterning an aluminum layer by an electrolytic plating method. In this case, a predetermined voltage can be applied to the pad through the plating wiring 7, so that the external electrode pad 4 made of various materials can be applied, and the high performance and high reliability external electrode pad 4 can be obtained. be able to.

According to the package substrate 1 of the present embodiment, the power supply pad 5, the plurality of ground pads 6, the plating wiring 7, and the ground wiring layer 10 are provided. Since it can be formed by the same manufacturing process as the manufacturing process of the other components, the package substrate can be manufactured with high manufacturing yield and reduced cost.

Next, a semiconductor device using the package substrate 1 of the present embodiment and a method for manufacturing the same will be described.

FIG. 3 shows a package substrate 1 according to this embodiment.
FIG. 3 is a schematic plan view showing a semiconductor device using the present invention in a see-through manner.
FIG. 4 is a schematic sectional view showing a section taken along the arrow BB in FIG. In FIG. 3, illustration of the plating wiring 7 formed on the surface of the package base 2 is omitted to simplify the illustration.

As shown in FIGS. 3 and 4, a semiconductor element of a semiconductor device such as an LSI is provided at the center of the package base 2 of the package substrate 1 of this embodiment with an insulating adhesive interposed therebetween. The semiconductor chip 11 is mounted, and the semiconductor chip 11 is mounted at the center of the package base 2.

Next, using a wire bonding apparatus, bonding pads 12 as external electrodes disposed on the surface of the semiconductor chip 11 and external electrode pads 4 on the package substrate 1 are bonded to bonding wires 13.
To make electrical connection.

Thereafter, the power bonding pad 12 of the semiconductor chip 11 is
The external electrode pads 4 electrically connected to the power supply pads 5 on the package substrate 1 are electrically connected using the bonding wires 13.

Further, using a wire bonding apparatus, the external electrode pad 4 electrically connected to the ground bonding pad 12 of the semiconductor chip 11 and the bonding wire 13 and the ground pad 6 of the package substrate 1 are connected. Electrical connection is made using a bonding wire 13.

Also, using a wire bonding apparatus, the external electrode pads 4 not electrically connected to the bonding pads 12 of the semiconductor chip 11 and the bonding wires 13 and the power supply pads 5 or the ground pads on the package substrate 1. 6 are electrically connected using bonding wires 13. In addition, this manufacturing process can be applied or unnecessary according to the design specification.

Thereafter, a sealing resin 14 is applied on the package base 2 of the package substrate 1 using a resin sealing device.

According to the semiconductor device using the package substrate 1 of this embodiment and the method of manufacturing the same, the plurality of external electrode pads 4 are arranged around the center of the surface of the rectangular package base 2. Package substrate 1 on which a plurality of power supply pads 5 and a plurality of ground pads 6 are arranged on each side around external electrode pads 4
After mounting the semiconductor chip 11 at the center of the package base 2 by using the bonding wire 13, the bonding pads 12 of the semiconductor chip 11 and the external electrode pads 4 on the package substrate 1 are electrically connected using bonding wires 13. ing. Thereafter, the external electrode pads 4 electrically connected to the power supply bonding pads 12 of the semiconductor chip 11 by the bonding wires 13 and the power supply pads 5 on the package substrate 1 are connected to the bonding wires 1.
3, the external electrode pad 4 electrically connected by the bonding wire 13 to the ground bonding pad 12 of the semiconductor chip 11 and the ground pad 6 of the package substrate 1 are connected to the bonding wire 13 Are electrically connected.

Therefore, according to the semiconductor device using the package substrate 1 of the present embodiment, even if the arrangement of the power supply bonding pads 12 and the ground bonding pads 12 of the semiconductor chip 11 is different, the same package substrate 1 is used. Can be used, the same package substrate 1 can be applied to the semiconductor chip 11 of various aspects.

As a result, according to the semiconductor device using the package substrate 1 of the present embodiment, the same package substrate 1 can be applied to the semiconductor chips 11 of various types (various modes). A package substrate 1 on which various kinds of semiconductor chips 11 can be mounted on the package substrate 1, and a semiconductor device using the same. Therefore, cost reduction of the semiconductor device can be realized.

According to the semiconductor device using the package substrate 1 of the present embodiment, the package base 1 having the ground wiring layer 10 formed in the inner layer of the package base 2 is used. Since the line capacitance of each signal wiring layer formed in the inner layer 2 can be reduced, noise such as crosstalk noise in each signal wiring layer can be reduced. Therefore, a semiconductor device with high performance and high reliability can be obtained.

(Embodiment 2) FIG. 5 is a schematic sectional view showing a package substrate according to Embodiment 2 of the present invention.

As shown in FIG. 5, in the package substrate 1 of the present embodiment, a power supply wiring layer 15 is formed in an inner layer of the package base 2. The power supply wiring layer 15 is electrically connected to the plug 8 embedded in the through hole, and the upper part of the plug 8 is electrically connected to the power supply pad 5. The lower part is electrically connected to the solder balls 3 via a wiring layer 9 formed on the back surface of the package base 2. In this case, the power supply wiring layer 15 electrically connected to the solder balls 3 is also arranged at the center of the package base 2 in order to improve the heat conductivity and stabilize the power supply wiring layer 15 having the inner layer structure. Have been. In addition, the power supply wiring layer 115
Is a method for manufacturing a package base 2 in which a signal wiring layer formed of, for example, a copper layer is formed below or above an insulating film in the same manufacturing step as a power wiring layer patterned for a power supply. Is formed.
Note that a signal wiring layer is formed on the package base 2 and is insulated from the power wiring layer 15 by an insulating film. In FIG. 5, for simplicity of illustration,
Illustration of the signal wiring layer and the insulating film is omitted.

The package substrate 1 of the present embodiment
Is characterized in that the power supply wiring layer 15 is formed in the inner layer of the package base 2, and the other structure is the same as that of the package substrate 1 of the first embodiment.

Therefore, also in the package substrate 1 of the present embodiment, the ground wiring layer 10 is formed in the inner layer of the package base 2 similarly to the package substrate 1 of the above-described first embodiment. The ground wiring layer 10 is electrically connected to the plug 8 embedded in the through hole, and the upper portion of the plug 8 is electrically connected to the ground pad 6. The lower part is electrically connected to the solder balls 3 via a wiring layer 9 formed on the back surface of the package base 2. Note that a signal wiring layer is formed on the package base 2, and the ground wiring layer 10 is formed by an insulating film.
And insulated.

As shown in FIG. 6, the semiconductor device using the package substrate 1 of the present embodiment and the method of manufacturing the same are the same as the semiconductor device using the package substrate 1 of the first embodiment and the method of manufacturing the same. Therefore, the description is omitted.

Further, according to the semiconductor device using the package substrate 1 of the present embodiment, the package substrate 1 in which the ground wiring layer 10 and the power supply wiring layer 15 are formed in the inner layer of the package base 2 is used. By having
Since the line capacitance of each signal wiring layer formed in the inner layer of the package base 2 can be reduced, noise such as crosstalk noise in each signal wiring layer can be reduced. Therefore, a semiconductor device with high performance and high reliability can be obtained.

(Embodiment 3) FIG. 7 is a schematic plan view perspectively showing a semiconductor device using a package substrate according to Embodiment 3 of the present invention. FIG. 8 shows C-
It is a schematic sectional drawing which shows the C arrow cross section. In FIG. 7, illustration of the plating wiring 7 formed on the surface of the package base 2 is omitted to simplify the illustration.

As shown in FIGS. 7 and 8, the semiconductor device according to the third embodiment uses a semiconductor chip 16 having a bump (eg, a bump made of solder, copper, or the like) 17 as an external electrode. The bump 17 as an external electrode of the semiconductor chip 16 is electrically connected to the external electrode pad 6 of the package substrate 1.

Next, a semiconductor device using the package substrate 1 of the present embodiment and a method of manufacturing the same will be described.

The package substrate 1 according to the first embodiment described above.
By using the package substrate 1 of the first embodiment described above.
A semiconductor chip 16 having a semiconductor element of a semiconductor device such as an LSI is mounted on a central portion of the package base 2, and a heat treatment is performed to partially liquefy the bump 17. Then, the semiconductor chip 16 is mounted on the central portion of the package base 2.

Next, the bonding wire 13 is connected to the external electrode pad 4 electrically connected to the power supply bump 17 of the semiconductor chip 16 and the power supply pad 5 on the package substrate 1 by using a wire bonding apparatus. To make electrical connection.

Using a wire bonding apparatus, the external electrode pads 4 electrically connected to the ground bumps 17 of the semiconductor chip 16 and the ground pads 6 on the package substrate 1 are bonded using the bonding wires 13. Electrical connection.

Using a wire bonding apparatus, the external electrode pads 4 not electrically connected to the bumps 17 of the semiconductor chip 16 and the power supply pads 5 or the ground pads 6 on the package substrate 1 are bonded with wire bonding wires. 13 for electrical connection. In addition, this manufacturing process can be applied or unnecessary according to the design specification.

In this case, as another aspect of the present embodiment, a method of performing wire bonding before setting the semiconductor chip 16 at the center of the package base 2 can be applied according to design specifications.

Thereafter, a sealing resin 14 is applied onto the package base 2 of the package substrate 1 using a resin sealing device.

According to the semiconductor device of the present embodiment, using the package substrate 1 of the above-described first embodiment, an external electrode is provided at the center of the package base 2 of the above-described package substrate 1 of the first embodiment. (For example, a bump made of solder, copper, or the like) 17 as a semiconductor device mounted with a semiconductor chip 16.

Therefore, according to the semiconductor device of the present embodiment, the same package substrate 1 can be used even if the arrangement of the power supply bump 17 and the ground bump 17 of the semiconductor chip 11 is different. The same package substrate 1 can be applied to various types of semiconductor chips 16.

As a result, according to the semiconductor device of the present embodiment, the same package substrate 1 can be applied to various (various aspects) semiconductor chips 16. It is a package substrate 1 on which various types of semiconductor chips 16 can be mounted, and is a semiconductor device using the same. Therefore, cost reduction of the semiconductor device can be realized.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the semiconductor device of the present invention, various semiconductor integrated circuit device chips other than the LSI chip can be applied as the semiconductor chip, and as the semiconductor element formed on the chip, a MOSFET, a CMOSFET, a bipolar transistor, or a , A MOS element, a CMOS type,
The present invention can be applied to a BiMOS type or BiCMOS type semiconductor integrated circuit device.

Further, the semiconductor device of the present invention has a MOSFE
DRAM (Dynamic Random Access Memory) having T, CMOSFET, BiCMOSFET, etc. as constituent elements,
The present invention can be applied to various semiconductor integrated circuit devices having a memory system such as an SRAM (Static Random Access Memory) or a logic system.

[0061]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the package substrate of the present invention, a plurality of external electrode pads are arranged around the center of the surface of the rectangular package base, and each side around the external electrode pads is physically located on the surface. A plurality of power supply pads (island-shaped electrode pads) spaced apart and a plurality of ground pads (island-shaped ground pads) physically spaced apart on the surface are arranged. Package substrate, the same package substrate can be applied to various (various aspects) semiconductor chips, and a package substrate on which a variety of semiconductor chips can be mounted on one type of package substrate. can do.

(2). According to the package substrate of the present invention, the plating wiring electrically connected to the external electrode pad can be arranged also in the region between the adjacent power supply pad and ground pad, so that the external In the manufacturing process of the electrode pad, for example, when a metal film made of, for example, a gold film or a copper film is formed by a plating method on the surface of the pad formed by patterning an aluminum layer, a wiring for plating , A predetermined voltage can be applied to the external electrode pad made of various materials, and a high-performance and highly reliable external electrode pad can be obtained.

(3). According to the package substrate of the present invention, the power supply pad, the plurality of ground pads, the plating wiring, and the ground wiring layer are provided. In this manner, the package substrate can be manufactured at a low manufacturing cost while maintaining a high manufacturing yield. Therefore, the cost of a semiconductor device manufactured using the same can be reduced.

(4). According to the semiconductor device of the present invention, the same package substrate is applied to various (various aspects) semiconductor chips such as a semiconductor chip having bonding pads as external electrodes or a semiconductor chip having bumps as external electrodes. This is a package substrate on which various kinds of semiconductor chips can be mounted on one type of package substrate, and a semiconductor device using the same. Therefore, the cost of the semiconductor device can be reduced.

(5). According to the semiconductor device of the present invention, since the ground wiring layer or the package substrate in which the ground wiring layer and the power supply wiring layer are formed in the inner layer of the package base, the semiconductor device is formed in the inner layer of the package base. Since the line capacitance of each signal wiring layer can be reduced, noise such as crosstalk noise in each signal wiring layer can be reduced. Therefore, a semiconductor device with high performance and high reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic plan view perspectively showing a package substrate according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a section taken along the line AA in FIG. 1;

FIG. 3 is a schematic plan view perspectively showing a semiconductor device using the package substrate according to the first embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view showing a cross section taken along line BB in FIG.

FIG. 5 is a schematic sectional view showing a package substrate according to a second embodiment of the present invention.

FIG. 6 is a schematic sectional view showing a semiconductor device using the package substrate according to the second embodiment of the present invention.

FIG. 7 is a schematic plan view perspectively showing a semiconductor device using a package substrate according to a third embodiment of the present invention;

FIG. 8 is a schematic cross-sectional view showing a cross section taken along the line CC in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Package board 2 Package base 3 Solder ball 4 Pad for external electrodes 5 Power supply pad 6 Ground pad 7 Plating wiring 8 Plug 9 Wiring layer 10 Ground wiring layer 11 Semiconductor chip 12 Bonding pad 13 Bonding wire 14 Sealing resin 15 Wiring layer for power supply 16 Semiconductor chip 17 Bump

Claims (9)

[Claims] 1. A plurality of external electrode pads are arranged around a chip mounting area on a surface of a rectangular package base, and are physically separated on each side around the external electrode pads on the surface. A plurality of power supply pads arranged at a predetermined distance and a plurality of ground pads physically separated from each other on the surface. 2. The package substrate according to claim 1, wherein the plating wiring electrically connected to the external electrode pad is a region between the adjacent power supply pad and the ground pad. Wherein the plating wiring is also disposed at an end of each side of the package base. 3. The package substrate according to claim 1, wherein a ground wiring layer is formed on an inner layer of the package base. 4. The package substrate according to claim 1, wherein a ground wiring layer and a power wiring layer are formed in an inner layer of the package base. 5. The package substrate according to claim 3, wherein a ground wiring layer, a ground wiring layer, and a power supply wiring layer are formed in an inner layer of the package base, and the ground wiring layer is formed of the package. The power supply wiring layer is electrically connected to a plug embedded in a through hole formed in an inner layer of the base, and the power supply wiring layer is electrically connected to a plug embedded in a through hole formed in an inner layer of the package base. A package substrate, which is electrically connected. 6. A semiconductor device using the package substrate according to claim 1, wherein a semiconductor chip is mounted on a surface of the package base. 7. The semiconductor device according to claim 6, wherein a bonding pad as an external electrode disposed on a surface of the semiconductor chip and an external electrode pad on the package substrate are electrically connected by a bonding wire. A semiconductor device characterized by being performed. 8. The semiconductor device according to claim 6, wherein a bump as an external electrode disposed on a back surface of the semiconductor chip is electrically connected to an external electrode pad on the package substrate. A semiconductor device characterized by the above-mentioned. 9. The semiconductor device according to claim 6, wherein an external electrode pad on the package substrate electrically connected to a ground external electrode of the semiconductor chip, An external electrode pad on the package substrate electrically connected to a ground pad on the package substrate using a bonding wire and electrically connected to a power supply external electrode of the semiconductor chip is provided on the package substrate. A semiconductor device, wherein the semiconductor device is electrically connected to a power supply pad of the first embodiment by using a bonding wire.