JPH11353789A - Optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent previously out-of-servo and erroneous reading by discriminating quality of an optical disk and reducing revolving speed of a disk motor holding in a PLL(phase locked loop) lock range at the time of retry-request. SOLUTION: The frequency of a PLL clock of an optical disk controller 3 is reduced responding to a retry-request signal indicating rereading of an optical disk 1, and the revolving speed of a disk motor 6 is reduced. Before occurrence of out-of-servo or deterioration of an error rate, a CPU 4 controls directly the revolving speed of the disk motor 6 by receiving retry-request, and disk rotation speed with which rereading can be performed for a short time can be obtained. Also, the frequency of a PLL clock is reduced corresponding to the change of the revolving speed of the motor, operation in a PLL lock range is guaranteed, and the playability of a bad disk can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention determines the quality of an optical disk, reduces the rotational speed of a disk motor while maintaining a PLL lock range when a retry request is made, and prevents servo disconnection and reading errors. The invention relates to an optical disk device that has been used.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional optical disk device. An optical disk device 50 shown in FIG. 1 is a device for reading a signal from an optical disk 1 such as a CD-ROM which spirally records a signal on a signal recording surface of a disk-shaped recording medium by an optical pickup 7 and reproducing the signal.
The optical pickup 7 irradiates the laser beam emitted from the semiconductor laser to the signal recording surface of the optical disk 1 via the objective lens, and refracts the laser beam to irradiate the laser beam onto the optical disk 1 with the irradiation beam. And a photodetector that takes in the reflected beam as a signal. The signal read by the optical pickup 7 is sent to an RF amplifier 5 serving as a preamplifier. The RF amplifier 5 separates the signal into an RF signal, which is a high-frequency signal, a tracking error signal, and a focusing error signal. Supplied. The tracking error signal indicates the horizontal focus shift of the optical pickup 7 with respect to the optical disc 1, and the focusing error signal indicates the vertical focus shift of the optical pickup 7 with respect to the optical disc 1.

[0003] The optical disk controller 3 converts the input RF signal into a binary EFM signal by slicing the RF signal with a value obtained by integrating the RF signal, outputs the binary EFM signal to an error correction circuit 8, and outputs a tracking error signal and a focusing error signal. , A tracking actuator control signal for driving the optical pickup 7 in the vertical / horizontal directions and a focusing actuator control signal are supplied to the actuator driver 9. The actuator driver 9 converts the actuator control signal into a tracking actuator driving signal and a focusing actuator driving signal, respectively, and supplies them to the tracking and focusing actuators 10 and 11, respectively. Thus, the tracking servo by the tracking actuator 10 and the focusing actuator 1
0, and the optical disc 1
, The reading attitude of the optical pickup 7 with respect to is controlled stably.

[0004] The optical disk controller 3 has an RF
A signal having a predetermined data length is extracted from the RF signal supplied from the amplifier 5, and the signal is compared with a PLL clock that provides a target speed as a synchronization signal, and the comparison error signal is gain- and phase-compensated by a disk servo equalizer. It is supplied to the motor driver 2 as a disk motor control signal. That is, a PLL in which a synchronization signal included in a read signal is divided by a phase comparator (not shown) from a reference oscillation signal supplied from a reference oscillator (not shown)
Since the optical disk controller 3 supplies a required motor control signal to the motor driver 2 so that the phase matches the clock, the motor driver 2 that converts the disk motor control signal into a motor drive signal drives the disk motor 6 at the required rotational speed. Drive rotationally. Thus, the phase locked loop (PLL) formed by the closed loop connecting the optical pickup 7, the RF amplifier 5, the optical disk controller 3, the motor driver 2, and the disk motor 6 enables the optical disk 1 regardless of the load on the disk motor 6 and the disk weight.
Can be rotated at a constant speed.

The EFM signal output from the optical disk controller 3 undergoes error correction processing in an error correction circuit 8, and is further transferred to a host computer as reproduction data via an interface circuit (not shown). However, in the case of the optical disc 1 in which the signal recording surface is distorted or warped when accessing at a high transfer speed, the servo tracking performance is likely to be deteriorated, and a defective disc or signal recording whose pit accuracy does not reach a predetermined standard is obtained. A bad disk with a scratch on the surface tends to cause a situation where the error rate deteriorates and the error cannot be corrected. In such a case, a retry request signal is output from the error correction circuit 8 to the CPU 4, and the CPU 4 having received the retry request signal has issued a command to the optical disc controller 3 to lower the transfer speed.

[0006]

However, even if the CPU 4 issues a command to lower the transfer speed to the optical disc controller 3 in the conventional optical disc device 50, the motor rotation speed actually reaches the target rotation speed after the command is issued. A time lag is unavoidable before the arrival, and during this time lag, it temporarily goes out of the PLL lock range and becomes unreadable, which may lead to a system error of the host computer or a dropped frame of the reproduced moving image. Also, once a retry occurs and the disk rotation speed is reduced, it takes a considerable amount of time before the phase locked loop is locked again and becomes readable, and moreover, time is proportional to the number of retry operations repeated. Since the loss also increases, there is a problem that the access at a higher transfer speed cannot be performed as a poor disk, and the playability is significantly reduced.

[0007] The present invention has solved the above problems,
Judge the quality of the optical disk and use PLL
It is an object of the present invention to reduce the rotation speed of a disk motor while keeping the rotation within a lock range, thereby preventing a servo disconnection or a reading error.

[0008]

In order to achieve the above object, an optical disk apparatus according to the present invention comprises a variable speed disk motor for driving an optical disk to rotate, and a synchronizing signal included in a read signal of the optical disk being a PLL clock. A phase locked loop type optical disk controller that controls the rotation speed of the disk motor so that the phases match, retry request means for generating a retry request signal for instructing rereading of the optical disk, and a retry request signal from the retry request signal. And a motor rotation speed control means for reducing the frequency of the PLL clock of the optical disk controller in response and reducing the rotation speed of the disk motor.

Further, the retry request means generates the retry request signal in response to a deviation of a tracking error signal or a focusing error signal from a normal range or an error correction of the read signal.

Further, the motor rotation speed control means samples a speed pulse output from the disk motor at a predetermined frequency to detect a motor rotation speed, and the motor rotation speed detection unit detects the motor rotation speed. The determined motor rotation speed is determined based on a predetermined PLL clock switching threshold as a reference, and when the motor rotation speed falls below the PLL clock switching threshold, a target rotation speed is designated to reduce the rotation speed. A threshold discriminating unit for commanding the motor, and a motor driving unit for driving the disk motor in response to the rotation speed reduction command issued by the threshold discriminating unit. A voltage amplifier for converting a speed into a kick / brake signal applied to the disk motor;
A switching switch that switches in response to the retry request signal and supplies the output of the voltage amplifier instead of the output of the optical disk controller; and a motor driver that receives the output of the switching switch and drives the disk motor. And the like.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described with reference to FIG. FIG. 1 is a block diagram showing an embodiment of the optical disk device of the present invention, and FIG. 2 is a signal waveform diagram of each circuit of the optical disk device shown in FIG.

An optical disk device 100 shown in FIG. 1 is based on a conventional optical disk device 50 and generates a retry request signal for instructing rereading of an optical disk, or responds to a retry request signal from the retry request signal. In addition, a motor rotation speed control means for lowering the frequency of the PLL clock of the optical disk controller 3 and lowering the rotation speed of the disk motor 6 is added.

The retry request means generates a retry request signal in response to a deviation of a tracking error signal or a focusing error signal from a normal range or an error correction of the read signal. The distortion disk detection circuit 18 branched and connected to the focusing error signal line corresponds to this. The distortion disk detection circuit 18 individually detects deviations of the tracking error signal or the focusing error signal from the steady range. For example, for the tracking error signal, the tracking actuator 10 is driven in the horizontal direction with the tracking servo open, and a tracking error signal is generated within a limit range (traverse level) that the tracking servo can follow. Is converted to digital data by A / D conversion. Further, a threshold value of the traverse level converted into digital data is determined based on a preset retry request slice level, and a retry request signal is supplied to the CPU 4 when the traverse level exceeds the retry request slice level.

Similarly, for the focusing error signal, the focusing actuator 11 is driven up and down with the focus servo open, and a focusing error signal is generated within a limit range (S-shaped level) that the focusing servo can follow. Then, the S-shaped level at that time is converted into digital data by analog / digital conversion (A / D conversion). Further, the S-shaped level converted into the digital data is discriminated as a threshold value based on a preset retry request slice level, and a retry request signal is supplied to the CPU 4 when the retry request slice level is exceeded. Thus, the distortion disk detection circuit 18 detects in advance the danger that the servo tracking performance will deteriorate, and generates a retry request signal for decreasing the disk rotation speed.

The motor rotation speed control means has a three-part configuration including a motor rotation speed detection unit, a threshold value discrimination unit, and a motor drive unit. The motor rotation speed detector detects the motor rotation speed by sampling a speed pulse output from the disk motor 6 at a predetermined frequency. Here, a pulse width measurement circuit 12, a timing pulse generation circuit 16, a flip-flop circuit 13 It consists of: In the present embodiment, a disk motor 6 having a hall element for outputting a speed pulse is used as the disk motor 6, and this speed pulse is transmitted from the motor driver 2 to the pulse width measurement circuit 12 and the timing pulse generation circuit 16 as an FG pulse. As supplied. The pulse width measurement circuit 12 samples the FG signal supplied from the motor driver 3 in synchronization with a sampling clock of a predetermined frequency, and counts the number of data “1” among “0” and “1” data obtained by sampling. Is counted and the pulse width is measured. A flip-flop circuit 13 is connected to the pulse width measurement circuit 12, and the flip-flop circuit 13 temporarily stores pulse width data as a buffer. The timing pulse generation circuit 16 functions to generate a timing pulse for the flip-flop circuit 13 to extract the measurement data of the pulse width measurement circuit 12.

The threshold value discriminating section is constituted by the CPU 4, and discriminates the motor rotation speed detected by the motor rotation speed detecting section on the basis of a predetermined PLL clock switching threshold value. When the value falls below the switching threshold value, a target rotation speed is designated and the rotation speed is reduced. The CPU 4 has a built-in double speed register 4a.
Double speed data indicating how many times the rotation speed of the CD corresponds to the CD reproduction speed can be stored. Also, CPU
4, a timer 17 is externally connected.
7 generates an interrupt pulse for periodically reading the pulse width data temporarily stored in the flip-flop circuit 13 at preset time intervals.

The motor drive unit drives the disk motor 6 in response to a rotation speed reduction command issued by the CPU 4 as the threshold value discrimination unit, and sets a target rotation speed consisting of binary data output by the CPU 4. A voltage amplifier 14 for converting to a kick / brake signal for applying a voltage to the disk motor 6, and a two-input one-output which switches in response to the retry request signal and switches and selects the output of the voltage amplifier 14 instead of the output of the optical disk controller 3. It comprises a type changeover switch 15 and a motor driver 2 that drives the disk motor 6 in response to the output of the changeover switch 15. The changeover switch 15 supplies a disk motor servo control signal to the motor driver 2 in a normal state other than the time of retry, and switches in response to a changeover command from the CPU 4 at the time of retry,
The output of the voltage amplifier 14 is supplied to the motor driver 2.

Next, the optical disk device 10 having the above configuration
The operation of 0 will be described. First, in order to check the quality of the optical disk 1 to be reproduced, the distortion disk detection circuit 18 drives the focusing actuator 11 in the vertical direction with the focus servo open, and the limit range (S-shaped level) where the focusing servo can follow ), A focusing error signal is generated, and S
The character level is converted from analog to digital (A / D conversion) to digital data. Next, after the focus servo is closed, the tracking actuator 10 is driven in the horizontal direction with the tracking servo open, and a tracking error signal is generated within a limit range (traverse level) that the tracking servo can follow. The traverse level is A / D converted and converted into digital data.

Further, the distortion disk detecting circuit 18
The digital data of the S-curve level and the traverse level, which have been subjected to the D / D conversion, are discriminated as threshold values with reference to a preset retry request slice level, and when digital data exceeding the retry request slice level is detected, the CPU 4 Supplies a retry request signal. That is, the distortion disk detection circuit 18 detects that the servo following performance is deteriorated due to distortion or warpage of the disk surface of the optical disk 1 at the time of accessing at a high transfer speed, before causing servo departure, and detects the disk rotation speed. Generate a retry request signal for dropping. On the other hand, the error correction circuit 8, like the distorted disk detection circuit 18, also has an error exceeding the error correction capability when reproducing a defective disk whose pit accuracy does not reach a predetermined standard or a coarse disk having a scratch on a signal recording surface. When the error occurs, a retry request signal is supplied to the CPU 4 upon recognition that the error cannot be corrected.

When the distorted disk detection circuit 18 or the error correction circuit 8 supplies a retry request signal to the CPU 4, the CPU 4 outputs a disk motor brake signal to the voltage amplifier 14 in order to reduce the rotation speed of the disk motor 6. At the same time, a switching command for switching from the normal disk servo operation to the operation at the time of retry is supplied to the changeover switch 15. The disk motor brake signal voltage-amplified by the voltage amplifier 14 is applied to the motor driver 2 via the changeover switch 15 switched to the retry operation side, and brakes the disk motor 6. In the rotation speed control of the disk motor by the brake operation during the retry operation, the lower limit speed and the upper limit speed can be set to limit the speed range. Also, braking by the disc motor brake signal
It may be continuous full braking or intermittent braking.

During the retry operation, when no retry request is issued for a certain period, the CPU 4 outputs a disk motor kick signal to the voltage amplifier 14. As a result, the disk motor kick signal that has been voltage-amplified by the voltage amplifier 14 is transmitted to the motor driver 2 via the switch 15.
To kick the disk motor 6. Also in the disk motor rotation speed control by the kick operation during the retry operation, the speed range can be limited by setting a lower limit speed and an upper limit speed. In addition, the kick control may be a continuous kick that continuously gives a full kick, or an intermittent kick that performs an intermittent kick.

When the retry operation is started by the retry request from the CPU 4 as described above, the pulse width measurement circuit 12 changes the pulse width of the FG signal during the high level period shown in FIG. The measurement is started at the rising edge of the sampling clock of the preset frequency shown in B). That is, the pulse width measurement circuit 12
The pulse width of the high level period of the G signal is counted as the number of sampling clock pulses included in the pulse width. Therefore, the counter data (count value) shown in FIG. 9C increases in proportion to the pulse width. When the FG signal switches from the high level to the low level, the measurement of the pulse width temporarily stops, and the counter data up to that time is held. The counter data held here is
At the falling edge of the next sampling clock pulse, it is synchronized with the timing pulse from the timing pulse generation circuit 16 and temporarily stored in the flip-flop circuit 13 as shown in FIG.

On the other hand, the CPU 4 synchronizes with the falling edge of the speed detection interrupt timing pulse shown in FIG. 3E output from the timer 17, and every time this timing pulse falls, the data temporarily stored in the flip-flop circuit 13 is output. Read. The read rotation speed data is PL
The threshold is determined based on the switching threshold of the L clock. During this time, the rotation speed of the disk motor 6 is gradually reduced, and reaches an overlap area where the lower limit area of the n-times PLL lock range and the upper area of the m-times PLL lock range shown in FIG. , N> m).

When the rotation speed of the disk motor 6 becomes equal to or less than the switching threshold value of the PLL clock, at the falling edge of the first speed detection interrupt timing pulse, as shown in FIG. The data held in the register 4a is rewritten from n times speed to m times speed.
The CPU 4 that has rewritten the content held in the double speed register 4a
A PLL clock switching command is issued to the optical disk controller 3. In this case, switching of the PLL clock is performed by switching the frequency division ratio of a frequency divider provided between the reference oscillator and the phase comparator. However, since both the frequency divider and the phase comparator are included in the optical disk controller 3, they are not shown. Thus, the optical disk controller 3 does not deviate from the PLL lock range,
The speed of the disk motor 6 is controlled according to the double speed specified by the command.

As described above, the optical disk device 100
Responds to a retry request signal instructing re-reading of the optical disk 1 so that the frequency of the PLL clock of the optical disk controller 3 is reduced and the rotational speed of the disk motor 6 is reduced.
In response to a retry request, the CPU 4 directly controls the rotation speed of the disk motor 6 before re-reading can be performed in a short period of time before the servo deviates or the error rate deteriorates due to poor pit accuracy or scratches. The disk rotation speed can be used. Further, the frequency of the PLL clock is also reduced in accordance with the change in the motor rotation speed, and the operation within the PLL lock range is guaranteed. Therefore, it is possible to prevent the PLL from being unlocked and to improve the playability of a bad disk. Furthermore, in the area where the pit accuracy is good, the data is returned to the normal high transfer rate, so that the data can be always reproduced at the maximum reproducible speed.

In addition, since a retry request signal is generated in response to a deviation of the tracking error signal or the focusing error signal from the normal range or an error correction of the read signal, the disk surface of the optical disk 1 may be distorted when accessing at a high transfer rate. Before the servo follow-up property is degraded due to warping or warpage, which leads to servo departure, capture a tracking error signal or focusing error signal and generate a retry request signal to reduce the disk rotation speed, or perform pit precision failure or damage. When error correction becomes impossible due to deterioration of the error rate caused by the
The retry request signal is generated based on the output from the optical disk 1, and it is possible to appropriately cope with the abnormality of the optical disc 1.

Further, a speed pulse output from the disk motor 6 is sampled at a predetermined frequency to detect a motor rotation speed, and the detected motor rotation speed is discriminated as a threshold value based on a predetermined PLL clock switching threshold value. When the rotation speed falls below the PLL clock switching threshold, a target rotation speed is designated and the rotation speed is reduced, and the disk motor 6 is driven in response to this command. By directly controlling the rotation speed of the disk motor 6 by the motor rotation speed control means, a disk rotation speed that can be re-read in a short time can be obtained, and the frequency of the PLL clock changes according to the change in the motor rotation speed. The disk rotation speed can be varied. PL generated by Gosuru
By preventing loss of the L lock and transferring the data at the highest readable transfer speed, the playability of a bad disk can be improved.

Further, the motor drive unit converts the target rotation speed into a kick / brake signal applied to the disk motor, and outputs the kick / brake signal from the changeover switch 15 which responds to the retry request signal to the output of the optical disk controller 3. Instead, the output of the voltage amplifier 14 is supplied to the motor driver 2 to drive the disk motor 6, so that the rotation speed control of the disk motor 6 normally performed by the phase locked loop type optical disk controller 3 is
The rotation speed of the disk motor 6 can be reliably reduced by substituting the kick / brake signal according to the target rotation speed by the action of the changeover switch 15 that switches in response to the retry request signal. When the state returns to the non-receiving state, the changeover switch 15 is returned to the original state, and the state can be promptly and reliably returned to the normal rotation control state.

In the above embodiment, the frequency division ratio of the frequency divider in the optical disk controller 3 is switched by the PLL clock switching command. However, a PLL clock having a desired frequency is selected from a plurality of finite number of PLL clocks. It is also possible to provide an optical disk controller configured to be able to select any of the above, and switch the PLL clock directly by a PLL clock switching command.

[0030]

As described above, according to the present invention,
In response to a retry request signal instructing rereading of the optical disk, the frequency of the PLL clock of the optical disk controller is reduced to reduce the rotation speed of the disk motor. The motor rotation speed control means directly controls the rotation speed of the disk motor in response to a retry request before the deterioration of the error rate due to defects or scratches, so that the disk rotation speed can be re-read in a short time. At the same time, the frequency of the PLL clock is also reduced according to the change in the motor rotation speed, and the PLL
In order to guarantee operation within the lock range, it is possible to prevent the PLL from being unlocked and to improve the playability of a bad disk. In addition, by returning to the normal high transfer speed in the area with good pit accuracy, it is always possible to An excellent effect is obtained such that data can be reproduced at the maximum reproducible speed.

Further, the retry request means generates a retry request signal in response to deviation of the tracking error signal or the focusing error signal from the normal range or error correction of the read signal. Before the servo following performance deteriorates due to disk surface distortion or warpage, etc., leading to servo deviation, capture a tracking error signal or focusing error signal and generate a retry request signal to reduce the disk rotation speed, or generate a pit When the error rate cannot be corrected due to the deterioration of the error rate due to poor accuracy or scratches, etc., a retry request signal is generated based on the output from the error correction circuit, and it is possible to appropriately cope with the optical disk abnormality. And so on.

Further, the motor rotation speed control means detects the motor rotation speed by sampling the speed pulse output from the disk motor at a predetermined frequency, and determines the detected motor rotation speed with reference to a predetermined PLL clock switching threshold value. The threshold value is determined, and when the motor rotation speed falls below the PLL clock switching threshold value, the target rotation speed is specified and the rotation speed is reduced, and the disk motor is driven in response to this command. By directly controlling the rotation speed of the disk motor by the motor rotation speed control unit that receives the retry request, a disk rotation speed that can be read again in a short time can be obtained. Since the frequency of the clock is also changed, the clock can always be operated within the PLL lock range. The disk rotational speed to prevent the PLL unlocking generated by variably controlling, by transferring the data in a readable fastest transfer speeds, the effect of such can improve the playability bad disk.

Further, the motor drive unit converts the target rotational speed into a kick / brake signal applied to the disk motor, and switches from a switch that switches in response to a retry request signal to an output from the optical disk controller. Since the output of the voltage amplifier is supplied to the motor driver to drive the disk motor, the operation of the changeover switch that switches the rotation speed control of the disk motor normally performed by the phase locked loop type optical disk controller according to the retry request signal is performed. By using the kick / brake signal in accordance with the target rotation speed, the rotation speed of the disk motor can be surely reduced. To return to the state of
There are effects such as being able to quickly and reliably return to the normal rotation control state.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an optical disk device according to the present invention.

FIG. 2 is a signal waveform diagram of each section of the circuit of the optical disk device shown in FIG.

FIG. 3 is a block diagram showing an example of a conventional optical disk device.

[Explanation of symbols]

 Reference Signs List 1 optical disk 2 motor driver 3 optical disk controller 4 CPU 5 RF amplifier 6 disk motor 7 optical pickup 8 error correction circuit 9 actuator driver 10 tracking actuator 11 focusing actuator 12 pulse width measurement circuit 13 flip-flop circuit 14 voltage amplifier 15 switching switch 16 timing pulse Generation circuit 17 Timer 18 Distortion disk detection circuit

Claims (4)

[Claims] 1. A variable speed type disk motor for rotating and driving an optical disk, and a phase locked loop system for controlling a rotation speed of the disk motor so that a synchronization signal included in a read signal of the optical disk coincides in phase with a PLL clock. An optical disk controller, retry request means for generating a retry request signal for instructing rereading of the optical disk, and in response to a retry request signal from the retry request means, reducing the frequency of the PLL clock of the optical disk controller; An optical disc device comprising: a motor rotation speed control means for reducing a rotation speed. 2. The retry request means according to claim 1, wherein said retry request means generates the retry request signal in response to a deviation of a tracking error signal or a focusing error signal from a normal range or an error correction of the read signal.
An optical disk device as described in the above. 3. The motor rotation speed control unit samples a speed pulse output from the disk motor at a predetermined frequency to detect a motor rotation speed, and the motor rotation speed detection unit detects the motor rotation speed. A threshold value of the motor rotation speed is determined based on a predetermined PLL clock switching threshold value, and when the motor rotation speed falls below the PLL clock switching threshold value, a target rotation speed is designated to command a reduction in the rotation speed. 2. The optical disc apparatus according to claim 1, further comprising a threshold value discriminator, and a motor drive unit that drives the disc motor in response to the rotation speed reduction command issued by the threshold value discriminator. 4. The motor drive section switches a voltage amplifier that converts the target rotation speed into a kick / brake signal applied to the disk motor, and switches in response to the retry request signal, and outputs the output of the optical disk controller. 4. The optical disk device according to claim 3, further comprising: a switch for supplying an output of the voltage amplifier; and a motor driver for receiving the output of the switch and driving the disk motor.