JPH11346332A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken the circuit operation of a CMOS image sensor by reducing a parasitic capacitance of a horizontal signal line depending on the number of horizontal selection transistors(TRs), to reduce intruded noise amount of the parasitic capacitance and to suppress image noise. SOLUTION: The solid-state image pickup device has an image pickup area 1 formed by arranging unit cells 13 each including a photoelectric conversion element are placed on a semiconductor substrate as a two-dimensional matrix, a plurality of vertical signal lines 18-i that read a signal from a unit cell on a same line in the image pickup area, a plurality of horizontal selection transistors(TRs) 23-i to sequentially select the signal read by vertical signal lines, and a horizontal signal line 26 through which the signal selected by the horizontal selection TR is transferred. Two horizontal selection TRs adjacent to each other among the horizontal selection TRs are used for a pair and one- side ends of the horizontal selection TRs of each pair are connected together.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and, more particularly, to a horizontal readout gate of a solid-state image sensor having a readout circuit capable of reading out pixel signals for each pixel. Used for electronic still cameras.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional equivalent circuit of a CMOS solid-state image sensor (CMOS image sensor) having a readout circuit capable of reading out pixel signals for each pixel.

In FIG. 5, unit cells 13 of one pixel / one unit (one pixel) are arranged in a two-dimensional matrix in a cell area (imaging area) 1. Each unit cell 13 includes a photodiode 8 having a ground potential applied to the anode side, a read transistor (shutter gate transistor) 14 having one end connected to the cathode side of the photodiode 8, and a read transistor 14
Transistor 1 having a gate connected to the other end of the transistor
5, a vertical selection transistor 16 having one end connected to one end of the amplification transistor 15, and a reset transistor 17 having one end connected to the gate of the amplification transistor 15.

In the cell area 1, a read line 4 commonly connected to the gates of the read transistors 14 of the unit cells in the same row and a gate of the vertical select transistors 16 in the unit cells of the same row are shared. , The reset line 7 commonly connected to the gates of the reset transistors 17 of the unit cells in the same row, and the other end of each amplifying transistor 15 of the unit cells in the same column. A connected vertical signal line 18-i (i = 1 to n) and a power supply line commonly connected to the other end of each reset transistor 17 and the other end of each vertical select transistor 16 of the unit cell in the same column. 9 are formed.

Further, outside the cell region 1, a plurality of load transistors 12 respectively connected between one end of the vertical signal line 18-i and a ground node, and each of the vertical signal lines 18-i A horizontal selection transistor 23-i having one end connected via a noise canceller circuit 25-i corresponding to the other end, respectively, and a plurality of horizontal selection transistors 23-i commonly connected to the other end. Horizontal signal line 26
And an output amplifier circuit 27 connected to the horizontal signal line 26.
A horizontal reset transistor 28 connected to the horizontal signal line 26; and a vertical selection line 6 in each row of the cell region 1.
A vertical shift register 2 for scanningly driving the vertical selection transistors 16 in each row by scanningly supplying a selection signal to each row, and a horizontal shift register 3 for scanningly driving the horizontal selection transistors 23-i. And a timing generation circuit 10 for generating various timing signals.

[0006] Each of the noise canceller circuits 25-i includes:
A sample and hold transistor 19 having one end connected to the other end of the vertical signal line 18-i, a coupling capacitor 20 having one end connected to the other end of the sample and hold transistor 19, and a coupling capacitor 20. For temporarily storing signal charges connected between the other end of the capacitor and the ground node, and a potential clamping transistor 2 connected to a connection node between the capacitors 20 and 21.
2 and the capacitors 20 and 21
Is connected to one end of the horizontal selection transistor 23-i.

Note that each horizontal selection transistor 23-i is
It comprises an NMOS transistor having an activation region (SDG region) formed in a P-well selectively formed in a surface layer portion of a semiconductor substrate. The P well is connected to the ground potential.

FIG. 6 is a timing waveform chart showing an example of the operation of the solid-state image sensor shown in FIG. Next, the operation of the solid-state image sensor of FIG. 5 will be described with reference to FIG.

Signal charges generated by photoelectrically converting incident light of each photodiode 8 are accumulated in the photodiode 8. Before the operation of reading out the signal charge, first, in order to reset the gate potential of the amplification transistor 15,
An “H” level reset signal is applied to the reset line 7 for a certain period, the reset transistor 17 is turned on for a certain period, and the gate potential of the amplification transistor 15 is reset to a desired potential.

At the same time, when an "H" level selection signal is applied to a vertical selection line (address line) 6 which is selected by scanning by the vertical shift register 2, the selection signal is applied from the vertical selection line 6. Vertical select transistor 1
6 is turned on, and the vertical selection transistor 1 is turned on.
6, the voltage of the power supply line 9 is supplied to the amplification transistor 15. Thus, the source-follower-connected amplifier transistor 15 outputs a potential corresponding to the gate potential to the corresponding vertical signal line 18-i.

However, there is a variation in the gate potential of the amplifying transistor 15 reset as described above, and a variation also appears in the reset potential of the vertical signal line 18-i on the drain side.

Therefore, in order to reset the variation of the reset potential of each vertical signal line 18-i, the sample hold transistor 19 is controlled to be turned on simultaneously with the reset transistor 17, and the reset of the vertical signal line 18-i is performed. The potential is transmitted to the capacitor 21 via the capacitor 20. Thereafter, the potential clamping transistor 22
Are controlled to be on for a certain period of time, and the capacitors 20 and 21
Are fixed uniformly.

Next, when the read line 4 of a predetermined row is selected (a read signal of "H" level is supplied) and the read transistor 14 is turned on, the charge stored in the photodiode 8 is transferred through the read transistor. The signal is transferred to the gate of the amplification transistor 15 and changes the gate potential. The amplification transistor 15 outputs a voltage signal corresponding to the change amount of the gate potential to the corresponding vertical signal line 18-i.

As a result, a change in the voltage signal of the vertical signal line 18-i due to the read operation after the reset is transmitted to the capacitor 21 via the capacitor 20, so that each vertical signal caused by the cell region 1 is generated. Noise such as a variation in the reset potential of the signal line 18-i, which is mixed in a stage preceding the noise canceller circuit 25-i, is removed.

After a series of noise removing operations as described above is completed, the sample-and-hold transistor 19 is turned off, the vertical selection transistor 16 is turned off, and the unit cell 13 is turned off. As a result, the cell region 1 and each noise canceller circuit 25-i are electrically separated.

After the horizontal reset transistor 28 is controlled to be turned on and the potential of the horizontal signal line 26 is reset, the horizontal selection transistors 23-i are sequentially controlled to be turned on, and the connection nodes of the capacitors 20 and 21 ( The voltage of the signal storage node SN) is sequentially read, amplified by the output amplifier circuit 27, and output.

A series of noise removing operations as described above are performed at the time of reading operation for each horizontal line. FIG. 7 shows a part of the pattern of the horizontal readout gate of the conventional CMOS image sensor shown in FIG.

In FIG. 7, reference numeral 23a-i denotes an activation region (SDG region) of the horizontal selection transistor 23-i formed in a P-well selectively formed in the surface layer of the semiconductor substrate.
The element isolation region 24 exists between the individual SDG regions 23a-i.

Reference numeral 23b-i denotes the horizontal selection transistor 23.
-i gate electrode (polysilicon wiring), the SD
It is formed on each channel of the G region 23a-i via an insulating gate film (not shown) formed on the surface of the P well.

Metal wires (normally, aluminum wires) corresponding to the vertical signal lines 18-i are connected to the n-type diffusion regions (drain) at one end of the SDG regions 23a-i, respectively. A metal wiring (normally, an aluminum wiring) corresponding to the horizontal signal line 26 is connected to the n-type diffusion region (source) at each other end.

Incidentally, the horizontal selection transistor 23
Since the junction capacitance with the P well exists in the n-type diffusion region serving as the drain / source of -i, the horizontal selection transistor 2
The parasitic capacitance 29 of the horizontal signal line 26 increases in proportion to the number of 31-i.

The parasitic capacitance 29 of such a horizontal signal line 26
Increases the operating speed of the circuit. Further, the switching noise generated due to the switching operation of the horizontal selection transistor 23-i jumps into the parasitic capacitance 29 without being removed by the noise canceller circuit 25-i, and the parasitic noise 29 increases in the jump noise amount. When the output signal of the solid-state image sensor is displayed on the screen of the image display device, it causes image noise such as vertical stripes.

[0023]

As described above, in the conventional solid-state image sensor, the parasitic capacitance of the horizontal signal line increases in proportion to the number of horizontal selection transistors. There has been a problem that the noise of the capacitance causes image noise such as vertical stripes on the display screen of the output signal of the image sensor.

The present invention has been made in order to solve the above-mentioned problems. The present invention has been made to reduce the parasitic capacitance of a horizontal signal line depending on the number of horizontal selection transistors, to increase the speed of circuit operation, and to reduce the parasitic capacitance. An object of the present invention is to provide a solid-state imaging device capable of reducing the amount of diving noise and suppressing image noise such as vertical stripes generated on a display screen of an output signal of an image sensor due to diving noise.

[0025]

According to the present invention, there is provided a solid-state imaging device comprising: an imaging region formed by arranging a plurality of unit cells each including a photoelectric conversion element in a two-dimensional matrix on a semiconductor substrate; A row selection unit for selecting a unit cell on the same row in a region; a plurality of vertical signal lines from which signals are read from unit cells on the same row in the imaging region selected by the unit cell selection unit; A horizontal read gate unit having a plurality of horizontal selection transistors for sequentially selecting signals read to the signal lines, and a horizontal signal line to which a signal selected by the horizontal read gate unit is transferred; A pair of adjacent two of the plurality of horizontal selection transistors,
One end of each set of horizontal selection transistors is connected collectively.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings. The configuration of the CMOS image sensor according to the first embodiment of the solid-state imaging device of the present invention is different from that of the above-described conventional CMOS image sensor.
Most of the configuration is the same, but the connection relationship between the horizontal selection transistor and the horizontal signal line in the horizontal readout gate portion and the pattern configuration in which two adjacent horizontal selection transistors form one set have been changed. The connection relationship (pattern) between the horizontal selection transistor and the vertical signal line, which form one set of two, is also changed.

FIG. 1 shows an equivalent circuit of the CMOS image sensor of the first embodiment. The CMOS image sensor shown in FIG. 1 is different from the conventional CMOS image sensor shown in FIG.
Of the two horizontal selection transistors in each group are connected collectively and connected to the horizontal signal line 26, and the others are the same. The same reference numerals are given as in FIG.

FIG. 2 shows the horizontal selection transistor 2 in FIG.
An example of the SDG pattern and the connection pattern with the vertical signal line 18-i is shown for a part of 3-i. Each horizontal select transistor 23-i in FIG. 1 is an NMOS transistor having an active region (SDG region) formed in a P-well selectively formed in a surface layer portion of a semiconductor substrate. The P well is connected to the ground potential.

In FIG. 2, the horizontal selection transistor 23
-i, the two sets of adjacent SDG areas 30-j (j = 1 to n / 2) are arranged in the horizontal direction, and the SDG areas 30-j of each set are formed. An element isolation region 31 exists between j.

23b-i is the horizontal selection transistor 23
-i gate electrode (polysilicon wiring), the SD
It is formed on each channel of the G region 30-j via an insulating gate film (not shown) formed on the surface of the P well.

A metal wiring (normally, an aluminum wiring) corresponding to the horizontal signal line 26 is connected to the n-type diffusion region at the center of the SDG region 30-j. In the present embodiment, the SDG regions 30-j of each pair are connected to the horizontal signal line 26 with the central n-type diffusion region serving as the common drain region D, and the n-type diffusion regions at both ends with the common drain region D interposed therebetween. The diffusion region is the source region S.

In this case, the shared drain region D in each set of SDG regions 30-j is formed to be narrower than the two source regions S, and is smaller than the two drain regions in the conventional SDG region. In the present example, it is formed so as to be equal to one rain area of the conventional example.

Therefore, the horizontal selection transistor 2
Focusing on the pair of 3-i sharing the drain region D, the junction capacitance between the drain region and the P-well is smaller than that of the two horizontal selection transistors 23-i of the conventional example (in this example, The parasitic capacitance 32 of the horizontal signal line 26, which depends on the number of horizontal selection transistors 23-i, is reduced (halved in this example) from the parasitic capacitance 29 of the conventional example.

Further, since each pair of SDG regions 30-j is connected to the horizontal signal line 26, the number of contacts between the horizontal selection transistor 23-i and the horizontal signal line 26 is smaller than in the conventional example. Therefore, the contact capacitance is also smaller than the conventional example.

Furthermore, since the size of each set of SDG areas 30-j is shorter in the horizontal direction than the two SDG areas of the conventional example, the SDG areas 30-j of each set are accordingly accompanied.
Signal line 18 connected to each source region S
The -i pattern has been changed from the conventional example.

That is, in FIG. 2, each set of SDG areas 3
Metal wirings (usually aluminum wirings) corresponding to the vertical signal lines 18-i are respectively connected to the source regions S at both ends of 0-j.

Here, in this embodiment, the vertical signal lines 18-i
Are set as a pair, and the mutual interval between the tips of the vertical signal lines 18-i on the horizontal read gate side is equal to the two source regions S of the SDG region 30-j of each set. In this embodiment, the pattern is formed so as to coincide with the mutual interval. In the present embodiment, two adjacent vertical signal lines 18-i are formed as a set, and the horizontal read gate side tips are bent stepwise in a direction in which they approach each other. It has a bent pattern.

The operation of the CMOS image sensor having the configuration shown in FIGS. 1 and 2 as described above is basically the same as the operation of the conventional example described above, but as described above, the horizontal selection transistor 23-i is used. Since the parasitic capacitance 32 of the horizontal signal line 26, which depends on the number, is reduced (halved in this example), the operation speed of the circuit is increased.

Incidentally, the arrangement relationship between the source region S and the shared drain region D of one transistor and the arrangement relationship between the source region S and the shared drain region D of the other transistor in each set of the SDG regions 30-j are symmetric. It is.
In other words, the pattern of the source region S of the one transistor and the pattern of the source region S of the other transistor are symmetrical, and the junction capacitances of the source regions may be different.

Due to this, the horizontal shift register 3 causes one of the plurality of horizontal selection transistors 23-i to operate.
When the elements are sequentially selected and driven, the junction capacitance of the source region changes for each selection transistor 23-i, which may cause image noise.

A second embodiment for solving such a problem will be described below. FIG. 3 shows the CM of the second embodiment.
3 shows an equivalent circuit of the OS image sensor. FIG.
2 shows an example of an SDG pattern and a connection pattern with a vertical signal line 18-i for a part of the horizontal selection transistor in FIG.

The CMOS image sensor shown in FIGS. 3 and 4 is the CMOS image sensor of the first embodiment shown in FIGS. 1 and 2.
As compared with the S image sensor, when one of the plurality of horizontal selection transistors 23-i is sequentially selected and driven as described above, a change in the junction capacitance of the source region for each selection transistor is corrected. And two correction transistors (a first correction transistor 23n + 1 and a second correction transistor 23n + 2).

The two correction transistors 23n + 1,
The 23n + 2 SDG region 40 shares the drain region D similarly to the SDG regions 30-j of each set of the horizontal selection transistors 23-i, and the source region S formed with the shared drain region D interposed therebetween. They are connected to each other and in a floating state, and are formed, for example, in the same row as the SDG areas 30-j of the respective sets.

Here, the two correction transistors 2
3n + 1 and 23n + 2 are symmetrical to one horizontal selection transistor when any one of the plurality of horizontal selection transistors 23-i is selected and driven by the horizontal shift register 3. One of the correction transistors having the proper arrangement relationship between the source region and the shared drain region is selected and driven by the correction transistor driving circuit 41.

The correction transistor drive circuit 41 includes:
When one of the horizontal odd-numbered transistors of the plurality of horizontal selection transistors 23-i is selected, the second correction transistor 23n + 2 is selected, and when one of the even-numbered transistors is selected. A gate control signal is supplied so as to select the first correction transistor 23n + 1, and a flip-flop circuit is used as an example. In this case, a pair of complementary output nodes of the flip-flop circuit 41 are connected to a pair of gates of the two correction transistors 23n + 1 and 23n + 2, and this flip-flop circuit 41 is connected to the horizontal shift register 3. What is necessary is just to make it perform an inversion operation | movement with a shift operation | movement.

The correction transistor driving circuit 4
Normally, the two correction transistors 23-n
+1 and 23-n + 2 are supplied with an "H" level gate control signal so as to turn on the respective gates, and the odd-numbered horizontal transistors of the plurality of horizontal selection transistors 23-i are supplied. When one transistor is selected, the first correction transistor 23-n + 1 is selected and an "L" level gate control signal is supplied to its gate. When one even-numbered transistor is selected, the first correction transistor 23-n + 1 is selected. It is preferable to select the second correction transistor 23-n + 2 and supply an "L" level gate control signal to its gate.

In this manner, the two correction transistors 23-n + 1 and 23-n + 2 may be any one of the plurality of horizontal selection transistors 23-i. When this is selected and driven to the ON state, this one select transistor is in the same source region.
Since one correction transistor having the arrangement relation of the shared drain region is selected and turned off by the correction transistor drive circuit 41, the switching noise generated due to the ON operation of the one arbitrary horizontal selection transistor Can be canceled out by switching noise generated due to the off operation of the one correction transistor.

In the above-described embodiment, the solid-state image sensor having the one-pixel unit cell array having the equivalent circuit as described above with reference to FIG. 5 has been described. However, the solid-state image sensor has the two-pixel unit cell array. The present invention is applicable to a solid-state image sensor.

In the above embodiment, a CMOS image sensor has been described. However, the present invention is also applicable to a CCD image sensor having a horizontal read gate according to the above embodiment.

The present invention is also applicable to a pixel structure in which a reset transistor, an address transistor, and an amplification transistor of two or more pixels are shared, and a readout transistor and a photodiode are provided.

[0051]

As described above, according to the solid-state imaging device of the present invention, the parasitic capacitance of the horizontal signal line depending on the number of horizontal selection transistors is reduced, and the speed of the circuit operation is increased.
It is possible to reduce the amount of stray noise of the parasitic capacitance, suppress image noise such as vertical stripes generated on the display screen of the output signal of the solid-state image sensor due to the stray noise, and obtain a clear image.

[Brief description of the drawings]

FIG. 1 is a diagram showing an equivalent circuit of a CMOS image sensor according to a first embodiment of the present invention.

2 is a diagram showing an example of a connection pattern between a pattern SDG and a vertical signal line for a part of a horizontal selection transistor in FIG. 1;

FIG. 3 is a diagram showing an equivalent circuit of a CMOS image sensor according to a second embodiment of the present invention.

4 is a diagram showing an example of an SDG pattern and a connection pattern with a vertical signal line for a part of a horizontal selection transistor in FIG. 2;

FIG. 5 is an equivalent circuit diagram showing a conventional example of a CMOS image sensor including a readout circuit capable of reading out a pixel signal for each pixel.

FIG. 6 is a timing waveform chart showing an example of the operation of the solid-state image sensor of FIG.

FIG. 7 is a diagram showing a pattern of a part of a horizontal read gate unit of the CMOS image sensor in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Cell area (imaging area), 2 ... Vertical shift register, 3 ... Horizontal shift register, 4 ... Reading line, 6 ... Vertical selection line, 7 ... Reset line, 8 ... Photodiode 9 ... Power supply line, 10 ... Timing generation Circuit 12 load transistor 13 unit cell of one pixel 15 amplifier transistor 16 vertical selection transistor 17 reset transistor 18-i vertical signal line 19 transistor for sample and hold 20 coupling Capacitor, 21: Capacitor for temporarily storing signal charge, SN: Signal storage node, 22: Transistor for potential clamp, 23-i: Horizontal selection transistor, 25-i: Noise canceller circuit, 26: Horizontal signal line, 27 ... Output amplification circuit, 28: Horizontal reset transistor.

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Hiromi Kusakabe 580-1 Horikawacho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Semiconductor System Technology Center Co., Ltd.

Claims (7)

[Claims] 1. An imaging area formed by arranging a plurality of unit cells including photoelectric conversion elements on a semiconductor substrate in a two-dimensional matrix, and a row selection unit for selecting a unit cell in the same row in the imaging area. Means, a plurality of vertical signal lines from which signals are respectively read from unit cells on the same row selected by the row selecting means, and a plurality of vertical signal lines from which signals are read from unit cells on the same row in the imaging region. A horizontal read gate unit having a plurality of horizontal selection transistors for sequentially selecting signals read to the plurality of vertical signal lines, respectively, and a horizontal signal line to which a signal selected by the horizontal read gate unit is transferred And two adjacent horizontal selection transistors are set as one set, and one end of each of the horizontal selection transistors in each set is collectively connected to each other. A solid-state imaging device characterized by being connected. 2. The solid-state imaging device according to claim 1, wherein each of the horizontal selection transistors comprises an NMOS transistor having an SDG region formed in a P well formed selectively in a surface layer portion of a semiconductor substrate. The SDG areas of the horizontal select transistors of the set are arranged in the horizontal direction, and an element isolation area exists between the SDG areas of each set. Each SDG area of each set has one end connected to the horizontal signal line. A solid-state imaging device, wherein the drain region is shared, and two source regions are formed with the one shared drain region interposed therebetween. 3. The solid-state imaging device according to claim 2, wherein a shared drain region in each set of SDG regions is formed narrower than two source regions. 4. The solid-state imaging device according to claim 2, wherein two adjacent ones of the plurality of vertical signal lines are set as one set, and the end portions of the vertical signal lines of each set on the horizontal read gate side are mutually connected. The pattern is formed such that the interval matches the mutual interval between the source regions of the SDG regions of each set, and the tips of the two vertical signal lines of each set adjacent to the horizontal read gate approach each other. A solid-state imaging device characterized by being bent stepwise in a direction. 5. The solid-state imaging device according to claim 2, wherein a drain region having the same size as the SDG region of each set is shared, and the one common drain region is formed therebetween. Further comprising two correction transistors having an SDG region in which the two source regions connected to each other are selected, and the two correction transistors are selected from any one of the plurality of horizontal selection transistors. A solid-state imaging device characterized in that, when driven, one correction transistor having the same arrangement relationship of source region and shared drain region as this one horizontal selection transistor is selected and turned off. 6. The solid-state imaging device according to claim 1, wherein each of the unit cells has a photodiode to which a ground potential is applied to an anode side, one end connected to a cathode side of the photodiode, and a read line connected to a gate. A connected read transistor, an amplification transistor having a gate connected to the other end of the read transistor, and a vertical signal line connected to one end; one end connected to the other end of the amplification transistor; A vertical selection transistor connected to a vertical selection line and a power supply line connected to the other end; a reset transistor connected between the gate of the amplification transistor and the power supply line, a gate connected to a reset line A solid-state imaging device comprising: 7. The solid-state imaging device according to claim 1, further comprising a plurality of vertical signal lines connected between one end of each of the plurality of vertical signal lines and a predetermined power supply node. A load transistor, a noise canceller circuit connected between each of the other ends of the plurality of vertical signal lines and the horizontal readout gate unit, an output amplifier circuit connected to the horizontal signal line, and the horizontal signal. A solid-state imaging device comprising a horizontal reset transistor connected between a line and a ground node.