JPH11340940A - Data transmission/reception system and data transmission /reception method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily increase the number of input output sections by enhancing a channel utility efficiency of a controller. SOLUTION: A switch matrix 30 freely sets a channel assigned to each port 21 under the control of a sever core 10. That is, the switch matrix 30 sets paths for a request signal and an acknowledge signal sent/received between each address counter 11 and each port 21. Thus, number of ports 21 is increased independently of number of channels of the server core 10 (number of address counters 11).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data transmission / reception system and a data transmission / reception method suitable for use in a so-called AV server system.

[0002]

2. Description of the Related Art Conventionally, there has been provided an AV server system which encodes video data and audio data to generate compressed data, stores the compressed data on a hard disk, decodes the compressed data and outputs the decoded data to the outside. I have. The AV server system includes a terminal board (port) such as a decoder and a server core for controlling each port.

In an AV server system using an existing device such as a so-called personal computer, data transfer is performed in a burst manner (burst transfer) because the amount of compressed data when encoded depends on the movement of the screen. method). At this time, since each port cannot predict the data amount of the compressed data, it is necessary to provide a FIFO (First-in First-out) memory or a buffer memory before the decoder. However, this is the cause of the high cost of the AV server system of the burst transfer system.

On the other hand, there is an AV server system of a time slot system in which a server core transmits compressed data to each port in a time-sharing manner instead of in a burst manner. For example, as shown in FIG. 3, in the time slot type AV server system 100, the server core 101 transmits a synchronization signal to each port 102 via a control bus, and compresses the synchronization signal to each port 102 via a data bus. Send data.
At this time, each port 102 counts a predetermined number of clocks from the synchronization signal, determines whether the compressed data transmitted when the predetermined number has been counted is transmitted to itself, and transmits the data to itself. When it is determined that the compressed data is the compressed data, the compressed data is taken.

[0005]

In the AV server system 100, it is necessary to provide a demultiplexing circuit 103 on the bus for counting a predetermined number of clocks and taking in compressed data on each port 102 side. Therefore, there is a problem that the circuit configuration becomes large and the cost increases. Therefore, an AV server system has been considered in which an output channel is provided in a core server and a port is assigned to each of the output channels.

For example, as shown in FIG. 4, the AV server system 200 mainly includes a server core 2 for storing compressed data obtained by compressing video data and audio data.
10 and a port 221 (221a to 221a)
221d).

The server core 210 has an address counter 211 (21) for generating a predetermined address or a request signal.
1a to 211d) and an address multiplexer 21 that outputs the addresses from each address counter 211 collectively.
2, a controller 213 for controlling writing and reading of compressed data, a hard disk 214 for storing compressed data, and a buffer memory 215 for temporarily storing compressed data read from the hard disk 214.

The address counter 211 is provided for each port 22
1, respectively. Each address counter 211 generates an address signal indicating a predetermined address corresponding to each port 221 and supplies it to the address multiplexer 212 in order to read predetermined compressed data from the buffer memory 215. The address multiplexer 212 supplies the address from each address counter 211 to the controller 213 in a time sharing manner.

The controller 213 has a predetermined port 22
Control of writing compressed data supplied from 1 through the time slot bus 216 to the hard disk 214 or reading of compressed data stored in the hard disk 214 is performed. The time slot bus 216 has a time slot width of, for example, 16 bits or 32 bits. Further, the controller 213 is a hard disk 2
14 is transmitted to a predetermined port 221.
To supply the compressed data to the buffer memory 215, the compressed data stored in the buffer memory 215 is read out based on the address from the address multiplexer 212,
16 to a predetermined port 221.

The port 221 is a terminal board including a decoder or an encoder. The ports 221 are provided according to the number of channels. Here, for example, if the port 221a is an encoder, the port 221a
Encodes video data supplied from the outside,
The compressed data at this time is supplied to the hard disk 214 via the time slot bus 216 and the controller 213. As a result, the compressed data is stored in the hard disk 214. When the port 221b is a decoder, the port 221b decodes compressed data supplied from the buffer memory 215 via the controller 213, and outputs decoded video data and audio data to the outside. In addition, each port 221 has:
A control line for transmitting / receiving a predetermined signal to / from the server core 210 is provided.

Next, a case where compressed data stored in the hard disk 214 is supplied to a predetermined port 221 will be described. Here, a case where compressed data is supplied to the port 221b as a decoder will be described as an example.

First, the address counter 211b corresponding to the port 221b generates a predetermined address on the buffer memory 215 corresponding to the port 221b, and supplies this address to the controller 213 via the address multiplexer 212.

The controller 213 reads compressed data to be supplied to the port 221b from the hard disk 214 in advance, and stores the compressed data in the buffer memory 21.
5 Then, the controller 213
The compressed data indicated by the address from the address counter 211b is read and supplied to the time slot bus 216.

On the other hand, the address counter 211b transmits a request signal to the port 221b when the compressed data read from the buffer memory 215 appears at the port 221b via the time slot bus 216. Here, the request signal is a request signal that requests the server core 210 to collect predetermined compressed data on the time slot bus 216 from each port 221.

When receiving the request signal, the port 221b receives the compressed data on the time slot bus 216, and transmits an acknowledgment signal to the server core 210 when the reception of the compressed data is completed. Here, the acknowledgment signal refers to each port 2
Reference numeral 21 denotes a response signal indicating a response to the server core 210 that the compressed data has been received.

The address counter 211b increments upon receiving the acknowledge signal,
The next address is generated to supply other compressed data to 21b. Conversely, the address counter 211b does not generate the next address for supplying other compressed data to the port 221b until receiving the acknowledge signal. As a result, the address counter 211b generates the next address signal after the port 221b is ready to receive another compressed data, and supplies the next address signal to the controller 213 via the address multiplexer 212.

The controller 213 includes a buffer memory 2
15 and reads out the compressed data indicated by the next address and supplies it to the time slot bus 216.

Then, each circuit repeatedly performs the above-described processing, so that compressed data necessary for decoding is read out from the hard disk 214 to the port 221b and supplied to the port 221b.

However, the AV server system 2
00, the address counter 211 and the port 22
1 is configured correspondingly, the number of ports 221 cannot be increased beyond the substantial capacity of the server core 210 as the control device. That is, even if there is a port 221 that is not used very frequently, it is necessary to always assign the address counter 11, and the channel use efficiency of the server core 210 is low.

The present invention has been proposed in view of such circumstances, and a data transmission / reception system and a data transmission / reception method capable of easily increasing the number of input / output units by improving the channel use efficiency of a control device. The purpose is to provide.

[0021]

In order to solve the above-mentioned problems, a data transmission / reception system according to the present invention includes a plurality of input / output units for receiving data from outside and / or transmitting data to outside; A plurality of channels for transmitting control signals to the plurality of input / output units; and a storage unit for storing data, wherein the storage unit stores data transmitted / received to / from each of the input / output units via a time slot bus. A control unit for performing writing or reading control on the control device, and a connection unit for connecting a control line for transmitting and receiving a control signal between each channel of the control device and any of the input / output units; And the predetermined input / output unit transmits and receives a control signal via a control line of the connection unit, and transmits and receives the data in synchronization with a timing of transmitting and receiving the control signal. That.

In the data transmission / reception system, the control device and the predetermined input / output unit transmit / receive a control signal via a control line of the connection means, and synchronize the data transmission / reception timing with the transmission / reception timing of the control signal. Can be transmitted and received, while effectively utilizing the above multiple channels,
The number of the input / output units can be increased.

In the data transmission / reception method according to the present invention, control lines are respectively connected between the plurality of input / output units and the control unit,
Each input / output unit receives input data from the outside and stores it in the storage unit of the control unit via the time slot bus and / or stores the data stored in the storage unit of the control unit via the time slot bus. In a data transmitting / receiving method for transmitting data output from each input / output unit to the outside, a control line for transmitting / receiving a control signal between each channel of the control device and any of the input / output units is connected, The control device and the predetermined input / output unit transmit and receive a control signal via a control line of the connection unit, and transmit and receive the data in synchronization with a timing of transmitting and receiving the control signal.

In the data transmission / reception method, the control device and the predetermined input / output unit transmit / receive a control signal via a control line of the connection unit, and synchronize the data transmission / reception timing with the control signal transmission / reception timing. Can be transmitted and received, and the number of the input / output units can be increased while effectively utilizing the plurality of channels.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

The present invention is applied to, for example, an AV server system 1 having the configuration shown in FIG. The AV server system 1 includes a server core 10 that mainly stores compressed data obtained by compressing video data and audio data, ports 21 (21a to 21g) including a decoder and the like, and a switch matrix 30.

In the AV server system 1, the server core 10 has three address counters 11a, 11b, 11
c, while eight ports 21a, 21b,.
・, 21f, 21g. That is, the number of ports 21 is larger than the number of address counters 11. At this time, the address counter 11 and the port 21
Are connected via a switch matrix 30.

Here, the server core 10 is provided with an address counter 11 for generating a predetermined address or a request signal.
(11a to 11c) and an address multiplexer 12 which outputs the addresses from each address counter 11 collectively.
A controller 13 for controlling writing and reading of compressed data; a hard disk 14 for storing compressed data; and a buffer memory 15 for temporarily storing compressed data read from the hard disk 14.

Each address counter 11 generates an address signal indicating a predetermined address and supplies it to the address multiplexer 12 in order to read predetermined compressed data from the buffer memory 15. Address multiplexer 12
Supplies the address from each address counter 11 to the controller 13 in a time-division manner.

The controller 13 controls the writing of compressed data supplied from a predetermined port 21 via the time slot bus 16 to the hard disk 14 or the reading of compressed data stored in the hard disk 14. The time slot bus 16 has a time slot width of, for example, 16 bits or 32 bits. Also,
When supplying the compressed data stored in the hard disk 14 to the predetermined port 21, the controller 13 once expands the compressed data in the buffer memory 15 and, based on the address from the address multiplexer 12,
The compressed data stored in the buffer memory 15 is read and supplied to a predetermined port 21 via the time slot bus 16.

The port 21 is a terminal board including a decoder or an encoder. Here, for example, if the port 21a is an encoder, the port 21a encodes video data supplied from the outside, and compresses the compressed data at this time into the time slot bus 16, the controller 1
3 to the hard disk 14. As a result, the compressed data is stored on the hard disk 14. When the port 21b is a decoder, the port 21b
Decodes the compressed data supplied from the buffer memory 15 via the controller 13, and outputs the decoded video data and audio data to the outside. Note that each port 21 is provided with a control line for transmitting and receiving a predetermined signal to and from the server core 10.

The switch matrix 30 includes the server core 1
Channels assigned to each port 21 are freely set by control from 0. That is, it is possible to set a connection path of a request signal and an acknowledge signal transmitted and received between each address counter 11 and each port 21. Further, the switch matrix 30 includes, for example, not only the connection between the address counter 11c and the port 21g, but also
At the same time, another address counter 11 can be connected to another port 21.

Next, a case where compressed data stored in the hard disk 14 is supplied to a predetermined port 21 will be described. Here, a case where compressed data is supplied to the port 21g which is a decoder will be described.

First, the server core 10 sets the switch matrix 30 so as to connect the address counter 11c and the control line of the port 21g. As a result, the switch matrix 30 transmits, for example, a request signal from the address counter 11c to the predetermined port 21g, and is ready to transmit an acknowledge signal from the port 21g to the address counter 11c.

The address counter 11c determines that the port 2
A predetermined address on the buffer memory 15 corresponding to 1g is generated, and this address is
Is supplied to the controller 13 via the.

The controller 13 reads compressed data to be supplied to the port 21g from the hard disk 14 in advance, and expands the compressed data on the buffer memory 15. Then, the controller 13 reads out the compressed data indicated by the address from the address counter 11c and supplies it to the time slot bus 16.

On the other hand, when the timing at which the compressed data read from the buffer memory 15 appears on the port 21g via the time slot bus 16 is reached, the address counter 11c
A request signal is transmitted to 1g.
Here, the request signal is a request signal for requesting the server core 10 to receive predetermined compressed data on the time slot bus 16 from each port 21.

When the port 21g receives the request signal, it receives the compressed data on the time slot bus 16, and when the reception of the compressed data is completed, the port 21g sends an acknowledgment signal to the server core 10 via the switch matrix 30. Send Here, the acknowledgment signal is a response signal indicating that each port 21 has received the compressed data from the server core 10.

When receiving the acknowledge signal, the address counter 11c increments and
Generate the next address to provide other compressed data to g. Conversely, the address counter 11c does not generate the next address for supplying other compressed data to the port 21g until receiving the acknowledge signal. As a result, the address counter 11c generates the next address signal after the port 21g is ready to receive another compressed data, and
Is supplied to the controller 13 via the.

The controller 13 has a buffer memory 15
, And reads out the compressed data indicated by the next address and supplies it to the time slot bus 16.

Then, as each circuit repeatedly performs the above-described processing, compressed data necessary for decoding is read from the hard disk 14 and supplied to the port 21g.

As described above, the AV server system 1
By providing the switch matrix 30 between the address counter 11 and the port 21, the number of ports 21 can be increased regardless of the number of channels of the server core 10 (the number of address counters 11). Thus, A
The V server system 1 can connect as many ports 21 as necessary irrespective of the frequency of use, and can switch the ports 21 according to the use status.

Further, the AV server system 1 can manage the number of channels of the server core 10 and the number of ports 21 separately, and can dynamically allocate channels of the server core 10 to the ports 21. Therefore, since the resources of the server core 10 can be used to the maximum, the resources can be effectively used in the small-scale server core 10.

Next, a second embodiment of the present invention will be described. Circuits that are the same as the circuits in the above-described embodiment are given the same reference numerals, and detailed descriptions thereof are omitted.

The second embodiment of the present invention is, for example, shown in FIG.
Is applied to the AV server system 1A having the configuration shown in FIG. In the above-described embodiment, each port 21 normally consumes less data than the input data. Therefore, it is considered that each port 21 takes in the compressed data from the time slot bus 16 not when receiving the request signal, but rather when outputting the acknowledge signal. Therefore, the AV server system 1A of the present embodiment obtains a monitor output using the acknowledge signal.

The AV server system 1A includes a server core 10 for storing compressed data and reading it out as needed.
A plurality of ports 21 (21a to 21a)
h) and a switch matrix 30.

The ports 21a to 21g are composed of an encoder, a decoder and the like, and can be used freely by the user. On the other hand, the port 21h comprises a monitor decoder. That is, the port 21h (hereinafter, port 21h)
This is referred to as “monitor decoder 21h”. ) Is port 21a
This monitors the video at the time of encoding or decoding of up to 21 g. When a predetermined signal is supplied from the switch matrix 30, the compressed data on the time slot bus 16 is fetched and decoded, and video data for monitoring is output. I do.

The switch matrix 30 has the function described in the above embodiment, and further includes the ports 21a to 21a.
It has a switching circuit 31 to which an acknowledge signal output by 1g is supplied. The switching circuit 31 includes the ports 21a, 21
, terminal g to which an acknowledgment signal output from b,..., 21g is supplied, and terminal a
Switch 31x for selecting any one of the acknowledge signals supplied to the terminal g and supplying the selected signal to the monitor decoder 21h.
Is provided.

Here, it is assumed that the port 21b is a decoder, and that the decoded video of the port 21b is monitored by the monitor decoder 21h will be described.

The server core 10 has a switch matrix 3 so that the address counter 11a and the port 21b can transmit and receive a request signal and an acknowledge signal, for example.
Set 0. Further, the server core 10 includes the switching circuit 3
The first switch 31x is connected to the terminal b.

The address counter 11a corresponding to the port 21b generates a predetermined address on the buffer memory 15 corresponding to the port 21b, and supplies this address to the controller 13 via the address multiplexer 12.

The controller 13 reads out compressed data to be supplied to the port 21b from the hard disk 14 in advance, and expands the compressed data on the buffer memory 15. The controller 13 includes an address counter 1
The compressed data indicated by the address from 1a is read and supplied to the time slot bus 16.

On the other hand, when the timing at which the compressed data read from the buffer memory 15 appears at the port 21b via the time slot bus 16 is reached, the address counter 11a sends a request signal to the port 21b via the switch matrix 30. Send Port 21b
Receives the request signal,
6 receives the compressed data. When the reception of the compressed data is completed, the port 21b transmits an acknowledgment signal to the server core 10 via the switch matrix 30.

At this time, the switch matrix 30 transmits an acknowledge signal from the port 21b to the address counter 11a and also supplies the acknowledge signal to the monitor decoder 21h via the switching circuit 31.

Upon receiving the acknowledge signal, the monitor decoder 21h takes in and decodes the compressed data on the time slot bus 16 and outputs video data for monitor output. That is, the monitor decoder 21h
By receiving compressed data when receiving an acknowledgment signal, it is possible to obtain a monitor output which is a video decoded by the port 21b.

As described above, the AV server system 1
A is a compressed data that exists on the time slot bus 16 and notifies the monitor decoder 21h of the timing of taking in the compressed data, regardless of which port 21 is being used. Port 2
One monitor output can be obtained.

Although the embodiment has been described assuming that the port 21b is a decoder, the port 21 may be an encoder. At this time, for example, the port 21a as an encoder decodes video data supplied from the outside and converts the compressed data into the time slot bus 16.
The switch matrix 30 may supply the response signal to the monitor decoder 21h when the response signal is output to the monitor decoder 21h. Thus, the monitor decoder 21h can monitor the video encoded by the port 21a if it captures the compressed data on the time slot bus 16 when receiving the response signal.

That is, the AV server system 1A can monitor a transmission channel, monitor at the time of encoding recording, and similarly, monitor at the time of external transfer (input or output) without consuming channel resources of the server core 10. It can be carried out.

Since the AV server system 1A only monitors the monitor decoder 21h and does not affect the input / output port 21, the AV server system 1A changes the channel to be monitored, for example, from the port 21a to the port 21b. You can also switch.

[0060]

As described above in detail, according to the data transmission / reception system and the data transmission / reception method according to the present invention, it is possible to transmit / receive a control signal between any one of the plurality of input / output units and the control device. The control line is connected, and the control device and any one of the input / output units transmit and receive a control signal via the control line of the connection unit, and transmit and receive data in synchronization with the timing of transmission and reception of the control signal. Accordingly, data can be transmitted and received by connecting more input / output units than the number of channels of the control device, and the channels of the control device can be effectively utilized.

[Brief description of the drawings]

FIG. 1 shows an AV according to a first embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of a server system.

FIG. 2 shows an AV according to a second embodiment to which the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of a server system.

FIG. 3 is a block diagram showing a schematic configuration of a conventional AV server system.

FIG. 4 is a block diagram illustrating a configuration of an AV server system.

[Explanation of symbols]

1,1A AV server system, 10 server cores, 1
1 address counter, 13 controller, 14 hard disk, 15 buffer memory, 16 time slot bus, 21 ports, 30 switch matrix

Claims (10)

[Claims] 1. A plurality of input / output units for receiving data from outside and / or transmitting data to the outside, a plurality of channels for transmitting control signals to the plurality of input / output units, and a storage for storing data Means for controlling writing or reading of data transmitted / received to / from each of the input / output units via the time slot bus to / from the storage means; and each channel of the control device and the input / output unit Connecting means for connecting a control line for transmitting and receiving a control signal to and from the control means, wherein the control device and the predetermined input / output section transmit and receive a control signal via the control line of the connecting means. And transmitting and receiving the data in synchronization with the transmission and reception timing of the control signal. 2. The control device according to claim 1, wherein the control device outputs reading data as predetermined data from the storage device, and outputs a request signal for requesting to take in each of the read predetermined data as the control signal. A plurality of request signal output means, and the predetermined input / output unit outputs predetermined data read from a control device when the request signal is supplied via a control line of the connection means. 2. The data transmission / reception system according to claim 1, wherein the data received from the time slot bus is subjected to predetermined processing and transmitted to the outside. 3. The data transmission / reception system according to claim 1, wherein said connection means switches connection of a control line between any one of said input / output units and said control device. 4. The predetermined input / output unit supplies a response signal to the control device via the connection unit after the completion of the capture of the predetermined data, and the read unit of the control device transmits the response signal via the connection unit. 3. The data transmission / reception system according to claim 2, wherein after the response signal is supplied from the input / output unit, another data to be supplied to the input / output unit is read from the storage unit. 5. The request signal output means, wherein when the predetermined data appears on the predetermined input / output unit from the time slot bus, the request signal output means transmits the request to the input / output unit via the connection means. The data transmission / reception system according to claim 2, wherein a signal is supplied. 6. A control line is connected between each of the plurality of input / output units and the control unit, and each input / output unit receives input data from the outside and stores the input data in a storage unit of the control unit via a time slot bus. And / or transmitting data stored in the storage means of the control unit from the input / output units to the outside via the time slot bus. A control line for transmitting / receiving a control signal to / from any of the entry / output units is connected, and the control device and the predetermined input / output unit transmit / receive a control signal via the control line of the connection unit. And transmitting and receiving the data in synchronization with the transmission and reception timing of the control signal. 7. The control device reads out predetermined data from the storage unit, and outputs a request signal for requesting capture of each of the read predetermined data as the control signal. One of the input / output units captures, via the control line of the connection means, predetermined data read from the control device when the request signal is supplied from the time slot bus, and stores the predetermined data in the captured data. 7. The data transmission / reception method according to claim 6, wherein the data is transmitted to the outside after performing the above processing. 8. The data transmission / reception method according to claim 6, wherein a connection of a control line is switched between any one of the input / output units and the control device. 9. The input / output section supplies a response signal to the control device via the connection means after completion of the capture of the predetermined data, and the control device transmits the response signal via the connection means. 8. The data transmission / reception method according to claim 7, wherein after the response signal is supplied from the output unit, another data to be supplied to the input / output unit is read. 10. The request signal is supplied to the input / output section via the connection means when a timing at which predetermined data appears in the one of the input / output sections from the time slot bus comes. The data transmission / reception method according to claim 7, wherein