JPH11340343A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for fabricating a field effect transistor having an insulation gate in which reliability of gate insulation film can be enhanced. SOLUTION: A gate insulation film 21 is formed on a semiconductor substrate 10 having a channel forming region and a first conductive layer 30 of amorphous silicon containing conductive impurities is formed on the gate insulation film 21. Subsequently, the first conductive layer 30 is heat treated to obtain a crystallized first conductive layer 30a which is then patterned into gate electrode and a source-drain region to be connected with the channel forming region is formed in the semiconductor substrate 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a field effect transistor.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory (EEPROM) is known.
Programmable ROM is DRAM (Dynamic Random Acces)
Since the area of a storage element per bit can be theoretically minimized as compared with other semiconductor storage devices such as a s Memory, a large capacity is expected as a semiconductor storage device. Consideration is being actively given as an alternative. As an EEPROM, a floating gate type, MNOS type or MO
Structures having various features such as NOS type and TEXTURED POLY type have been developed.

FIG. 12 is a sectional view showing an example of a floating gate type semiconductor nonvolatile memory device which is one of the EEPROMs. A gate insulating film 21 made of, for example, a thin silicon oxide is formed on a channel formation region of the semiconductor substrate 10 separated by the element isolation insulating film 20.
A floating gate 30b made of, for example, polysilicon is formed thereon, and an intermediate insulating film 22a made of, for example, an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film) is formed thereon. On the upper layer of the intermediate insulating film 22a, for example, a control gate 31 having a polycide structure in which polysilicon and tungsten silicide are laminated (shown as a single layer in the drawing)
a is formed. On both sides of the control gate 31a, the intermediate insulating film 22a and the floating gate 30b, for example, a sidewall insulating film 23 of silicon oxide
Are formed. A source / drain diffusion layer 12 is formed in the semiconductor substrate 10 on both sides of the control gate 31a, and a conductive impurity having a lower concentration than the source / drain diffusion layer 12 is formed on the channel formation region side. (Lightly Doped Drain) diffusion layer 11 containing GaN. As described above, the floating gate 30b covered with the insulating film is provided between the control gate 31a and the channel formation region in the semiconductor substrate 10.
Is formed.

A silicon oxide interlayer insulating film 24 is formed on the entire surface so as to cover the transistor, and the source / drain diffusion layer 12 and the control gate 3 are formed.
A contact hole exposing 1a is opened, and source / drain diffusion layer 12 and control gate 31a are opened.
Are formed to connect to the respective electrodes.

In the floating gate type semiconductor nonvolatile memory device having the above-mentioned structure, the floating gate 30b has a function of retaining electric charge in the film, and has a gate insulating film 21, an intermediate insulating film 22a and a sidewall insulating film 23. Has a role of confining charges in the floating gate 30b. When an appropriate voltage is applied to the control gate 31a, the semiconductor substrate 10 or the source / drain diffusion layer 12, a Fowler-Nordheim tunnel current is generated, and charges are injected from the semiconductor substrate 10 to the floating gate 30b through the gate insulating film 21, Alternatively, charges are released from the floating gate 30b to the semiconductor substrate 10.

As described above, the floating gate 30b
When electric charges are accumulated therein, an electric field is generated by the accumulated charges, so that the threshold voltage of the transistor changes. This change allows data to be stored. For example, data can be erased by accumulating electrons in the floating gate 30b, and data can be written by discharging electrons accumulated in the floating gate 30b.

A method of manufacturing the above-mentioned floating gate type semiconductor nonvolatile memory device will be described below with reference to the drawings. First, as shown in FIG. 13A, for example, a LOCOS (Local Oxid
The element isolation insulating film 20 is formed by a method of formation (Silicon). Next, a gate insulating film 21 of silicon oxide is formed on the active region (channel forming region) separated by the element isolation insulating film 20 by, for example, a thermal oxidation method.

Next, as shown in FIG. 13B, for example, a CVD (Chemical Vapor Dep
osition) method to deposit polysilicon containing no conductive impurities, and to form a floating gate layer 30c.
To form

Next, for example, as shown in FIG.
The conductive impurity D such as phosphorus is diffused into the floating gate layer 30c by thermal diffusion using POCl ₃ to form the floating gate layer 30a having conductivity.

Next, as shown in FIG. 1D, an oxide film is formed on the floating gate layer 30a by, for example, a thermal oxidation method or a CVD method.
A nitride film is formed by the D method, and then a thermal oxidation method or a CV
An oxide film is formed by the method D, and an intermediate insulating film 22 which is an ONO film (a stacked insulating film of an oxide film-nitride film-oxide film) is formed. Next, polysilicon and tungsten silicide are sequentially laminated by, for example, a CVD method to form a control gate layer 31 having a polycide structure (shown as a single layer in the drawing).

Next, as shown in FIG. 14E, a resist film R of a gate electrode pattern is formed by a photolithography process, and processed into a gate electrode pattern by etching such as RIE (reactive ion etching).
The floating gate 30b, the intermediate insulating film 22a, and the control gate 31a are formed.

Next, as shown in FIG. 14F, the conductive impurity D1 is ion-implanted using the control gate 31a as a mask to form the LDD diffusion layer 11.

Next, as shown in FIG. 15G, silicon oxide is deposited on the entire surface by, eg, CVD, and
Etching is performed on the entire surface by etching such as to remove silicon oxide on both sides of the control gate 31a, the intermediate insulating film 22a, and the floating gate 30b, and remove the other portions to form a silicon oxide sidewall insulating film 23.

Next, as shown in FIG. 15H, ions of a conductive impurity D2 are implanted at a higher concentration than the LDD diffusion layer 11 using the side wall insulating film 23 as a mask. 12 is formed. Above,
A field effect transistor to be a memory transistor having a floating gate structure having a source / drain region having an LDD structure is formed.

Next, as shown in FIG. 15 (i), the above-mentioned field effect transistor is covered and
Silicon oxide is deposited by a method to form an interlayer insulating film 24.

Next, a contact hole for exposing the control gate 31a and the source / drain diffusion layer 12 is opened in the interlayer insulating film 24, and a conductive layer of, for example, aluminum is formed on the entire surface by filling the contact hole. And then pattern the control gate 31a and the source / drain diffusion layer 1
2 are formed to be connected to the electrodes 2 respectively. As described above, the operation reaches the semiconductor nonvolatile memory device shown in FIG.

[0017]

However, the floating gate type semiconductor nonvolatile memory device manufactured by the above-mentioned conventional method has a problem that the reliability of the gate insulating film as the tunnel insulating film is low. When a charge is injected into or released from the floating gate to store or erase data, a tunnel current flows through the gate insulating film,
Since the gate insulating film is deteriorated and eventually destroyed by repeating data writing / erasing, the number of times of data writing / erasing largely depends on the reliability of the gate insulating film. If the reliability of the gate insulating film is low, the number of possible data write / erase operations is small, which is not practical.

Further, not only the transistor having the floating gate structure as described above, but also the ordinary MOS field-effect transistor, there is a demand for improvement of the reliability of the gate insulating film.

The present invention has been made in view of the above problems, and accordingly, the present invention relates to a field effect transistor having an insulating gate, such as a transistor serving as a memory transistor having a floating gate structure in a semiconductor nonvolatile memory device. It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of improving the reliability of a gate insulating film.

[0020]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a gate insulating film on a semiconductor substrate having a channel forming region; A step of forming a first conductive layer made of amorphous silicon containing a conductive impurity in an upper layer, a heat treatment step of crystallizing the first conductive layer, and a step of processing the first conductive layer into a gate electrode pattern. Forming source / drain regions connected to the channel formation region in the semiconductor substrate.

The method of manufacturing a semiconductor device according to the present invention is as follows.
A gate insulating film is formed over a semiconductor substrate having a channel formation region, and a first conductive layer made of amorphous silicon containing a conductive impurity is formed over the gate insulating film. Next, heat treatment for crystallizing the first conductive layer is performed. Next, the first conductive layer is processed into a pattern of a gate electrode, and a source / drain region connected to a channel formation region is formed in the semiconductor substrate.

According to the above-described method for manufacturing a semiconductor device, a floating gate or a MOS transistor of a transistor having a floating gate structure is formed on a gate insulating film.
A first conductive layer serving as a gate electrode in a field-effect transistor is deposited as amorphous silicon containing a conductive impurity such as phosphorus, and crystallized in a later step,
The reliability of the gate insulating film can be improved, and in particular, in a transistor having a floating gate structure, the number of times of data writing / erasing can be increased.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming the first conductive layer,
It is formed by containing phosphorus at a concentration of 0.06% by weight or more. Alternatively, preferably, in the heat treatment step, 9
Heat treatment is performed at a temperature of 00 ° C. or less. Or preferably,
In the heat treatment step, heat treatment is performed for 30 minutes or more. By forming the first conductive layer under these conditions,
The reliability of the gate insulating film can be further improved.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, in the step of forming the gate insulating film, a silicon oxide film is formed by a thermal oxidation method. A silicon oxide film formed by a thermal oxidation method is a dense and favorable film, and can further improve the reliability of a gate insulating film.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the heat treatment step and before the step of processing the first conductive layer into a gate electrode pattern, a step of forming an intermediate insulating film on the first conductive layer; And forming the second conductive layer into a gate electrode pattern. In the step of processing the first conductive layer into a gate electrode pattern, the intermediate insulating film and the second conductive layer are processed into the same pattern. More preferably, in the step of forming the intermediate insulating film, a stacked insulating film of an oxide film-nitride film-oxide film is formed.

According to the above method of manufacturing a semiconductor device, a memory transistor having a floating gate structure in which a first conductive layer is used as a floating gate and a second conductive layer is used as a control gate to store data by storing charges in the floating gate. Can be formed. In the transistor having the above-described structure, charge is injected into or released from the floating gate through the gate insulating film, and the number of times of data writing / erasing largely depends on the reliability of the gate insulating film. Since the reliability of the insulating film can be improved, the number of times of writing / erasing data can be increased.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of processing the first conductive layer into a gate electrode pattern, the method further comprises the step of forming a sidewall insulating film on a side wall of the patterned first conductive layer, Forming a region, forming a low-concentration region containing conductive impurities by performing ion implantation before the step of forming the sidewall insulating film;
Forming a region containing a high concentration of conductive impurities by ion implantation after the step of forming the sidewall insulating film. As a result, LDD (Lightly Doped Drain
3) A source / drain region having a structure can be formed, and a short channel effect of a transistor which occurs when a semiconductor device is miniaturized can be suppressed.

[0028]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First Embodiment A semiconductor device according to the present embodiment is a semiconductor nonvolatile memory device having a floating gate memory transistor. FIG. 1A is a sectional view thereof. A gate insulating film 21 made of, for example, a thin silicon oxide is formed on a channel formation region of the semiconductor substrate 10 separated by the element isolation insulating film 20, and a floating gate 30b made of, for example, polysilicon is formed thereon. And an intermediate insulating film 2 made of, for example, an ONO film (a stacked insulating film of an oxide film, a nitride film and an oxide film) as an upper layer thereon
2a is formed. In the upper layer of the intermediate insulating film 22a,
For example, a control gate 31a having a polycide structure in which polysilicon and tungsten silicide are laminated (shown as a single layer in the drawing) is formed. On both sides of the control gate 31a, the intermediate insulating film 22a, and the floating gate 30b, for example, a sidewall insulating film 23 of silicon oxide is formed. A source / drain diffusion layer 12 is formed in the semiconductor substrate 10 on both sides of the control gate 31a, and a conductive impurity having a lower concentration than the source / drain diffusion layer 12 is formed on the channel formation region side. (Lightly Doped Drain) diffusion layer 11 containing GaN. As described above, the field effect transistor having the floating gate 30b covered with the insulating film is formed between the control gate 31a and the channel formation region in the semiconductor substrate 10.

Further, an interlayer insulating film 24 of silicon oxide is formed on the entire surface so as to cover the transistor, and the source / drain diffusion layer 12 and the control gate 3 are formed.
A contact hole exposing 1a is opened, and source / drain diffusion layer 12 and control gate 31a are opened.
Are formed to connect to the respective electrodes.

In the floating gate type semiconductor nonvolatile memory device having the above-described structure, the floating gate 30b has a function of retaining charges in the film, and the gate insulating film 21, the intermediate insulating film 22a and the sidewall insulating film 23 Has a role of confining charges in the floating gate 30b. When an appropriate voltage is applied to the control gate 31a, the semiconductor substrate 10 or the source / drain diffusion layer 12, a Fowler-Nordheim tunnel current is generated, and charges are injected from the semiconductor substrate 10 to the floating gate 30b through the gate insulating film 21, Alternatively, charges are released from the floating gate 30b to the semiconductor substrate 10.

As described above, the floating gate 30b
When electric charges are accumulated therein, an electric field is generated by the accumulated charges, so that the threshold voltage of the transistor changes. This change allows data to be stored. For example, data can be erased by accumulating electrons in the floating gate 30b, and data can be written by discharging electrons accumulated in the floating gate 30b.

A method of manufacturing the above-mentioned floating gate type semiconductor nonvolatile memory device will be described below with reference to the drawings. First, as shown in FIG. 2A, for example, a LOCOS (Local Oxidat
An element isolation insulating film 20 is formed by an ion of silicon method. Next, 9n is formed on the active region (channel formation region) separated by the element isolation insulating film 20 by, for example, a thermal oxidation method.
A gate insulating film 21 of silicon oxide is formed to a thickness of m.

Next, as shown in FIG. 2B, for example, a CVD (Chemical Vapor Depos)
The floating gate layer 30 is formed by depositing amorphous silicon containing phosphorus as a conductive impurity at a film forming temperature of 530 ° C. and a thickness of 100 nm by the ition) method. The content of phosphorus in the amorphous silicon film can be, for example, 0.06 to 0.75% by weight.

Next, as shown in FIG. 2C, a heat treatment is performed to crystallize the amorphous silicon, thereby forming a crystallized floating gate layer 30a. The heat treatment temperature can be, for example, 650 to 900 ° C., and the heat treatment time can be, for example, 30 minutes to 10 hours.

Next, as shown in FIG. 3D, an oxide film is formed on the floating gate layer 30a by, for example, a thermal oxidation method or a CVD method.
A nitride film is formed by a thermal oxidation method or CVD.
An ONO film (oxide film-nitride film-
An intermediate insulating film 22 which is a stacked insulating film of an oxide film) is formed to a thickness of about 20 nm in terms of an oxide film. Next, polysilicon and tungsten silicide are sequentially deposited to a thickness of about 200 nm by, for example, a CVD method to form a control gate layer 31 having a polycide structure (shown as a single layer in the drawing).

Next, as shown in FIG. 3E, a resist film R of a gate electrode pattern is formed by a photolithography process, and is processed into a gate electrode pattern by etching such as RIE (reactive ion etching). The floating gate 30b, the intermediate insulating film 22a, and the control gate 31a are formed.

Next, as shown in FIG. 3F, the conductive impurity D1 is ion-implanted using the control gate 31a as a mask to form the LDD diffusion layer 11.

Next, as shown in FIG.
Silicon oxide is deposited on the entire surface by the VD method, etched back by etching such as RIE, and the other portions are removed except for the silicon oxide on both sides of the control gate 31a, the intermediate insulating film 22a and the floating gate 30b. A side wall insulating film 23 of silicon oxide is formed.

Next, as shown in FIG. 4H, the conductive impurity D2 is changed to L using the sidewall insulating film 23 as a mask.
The source / drain diffusion layers 12 are formed by ion implantation so as to have a higher concentration than the DD diffusion layers 11. Above,
A field effect transistor to be a memory transistor having a floating gate structure having a source / drain region having an LDD structure is formed.

Next, as shown in FIG. 4 (i), an interlayer insulating film 24 is formed by depositing silicon oxide on the entire surface covering the field effect transistor by, for example, a CVD method.

Next, a contact hole for exposing the control gate 31a and the source / drain diffusion layer 12 is opened in the interlayer insulating film 24, and a conductive layer of aluminum or the like is formed on the entire surface by filling the contact hole, for example, by a sputtering method. And then pattern the control gate 31a and the source / drain diffusion layer 1
2 are formed to be connected to the electrodes 2 respectively. As described above, the operation reaches the semiconductor nonvolatile memory device shown in FIG.

According to the method of manufacturing the semiconductor nonvolatile memory device of the present embodiment, the conductive layer serving as the floating gate in the transistor having the floating gate structure is formed on the gate insulating film by the amorphous layer containing a conductive impurity such as phosphorus. By depositing as silicon and crystallizing in a later step, the reliability of the gate insulating film can be improved and the number of times of data writing / erasing can be increased.

Example 1 In the above embodiment, the heat treatment temperature was fixed at 650 ° C., the heat treatment time was fixed at 30 minutes, and the phosphorus content in the amorphous silicon layer serving as the floating gate layer was 0.06 wt. %, 0.5% by weight, and 0.75% by weight. A constant current TDDB (Time Dependent Dielect) is used for these semiconductor devices and a semiconductor device as a comparative example formed by introducing phosphorus by thermal diffusion using POCl ₃ into a polysilicon layer serving as a floating gate layer by a conventional method.
ricBreakdown) characteristics (Qbd value) were examined. FIG. 5 shows the results. The intrinsic withstand voltage in the TDDB characteristic (the withstand voltage in the abrasion region) is higher than that of the comparative example in any of the semiconductor devices of the present embodiment.
It was found that the intrinsic withstand voltage was the highest at 0.75% by weight.

(Example 2) In the above embodiment, the phosphorus content in the amorphous silicon layer serving as the floating gate layer was fixed at 0.5% by weight, the heat treatment time was fixed at 30 minutes, and the heat treatment temperature was set at 650. ℃, 830 ℃, 9
A semiconductor device was set at a temperature of 00 ° C. These semiconductor devices and a comparative semiconductor device fabricated by introducing phosphorus by thermal diffusion using POCl ₃ into a polysilicon layer serving as a floating gate layer according to a conventional method were defined in the same manner as in Example 1. Current TDDB characteristics (Qbd value)
Was examined. FIG. 6 shows the results. The intrinsic withstand voltage in the TDDB characteristic is higher than that of the comparative example in any of the semiconductor devices of this embodiment. In particular, the lower the heat treatment temperature, the higher the intrinsic withstand voltage.
It was found that the intrinsic withstand voltage was highest at 50 ° C.

(Example 3) In the above embodiment, the phosphorus content in the amorphous silicon layer serving as the floating gate layer was 0.5% by weight, and the heat treatment temperature was 650 ° C.
, And heat treatment times were set to 30 minutes and 10 hours, respectively, to produce a semiconductor device. These semiconductor devices and comparative semiconductor devices fabricated by introducing phosphorus by thermal diffusion using POCl ₃ into a polysilicon layer serving as a floating gate layer according to a conventional method were defined in the same manner as in Example 1. The current TDDB characteristic (Qbd value) was examined. FIG. 7 shows the results. The intrinsic withstand voltage in the TDDB characteristic is higher in each of the semiconductor devices of the present example than in the comparative example, and it has been found that the intrinsic withstand voltage is higher when the heat treatment time is long for 10 hours.

Second Embodiment The semiconductor device according to this embodiment is a semiconductor device having a MOS field effect transistor. FIG. 8 is a sectional view thereof. A gate insulating film 21 made of, for example, a thin silicon oxide is formed on a channel formation region of the semiconductor substrate 10 separated by the element isolation insulating film 20, and a lower gate electrode 33 made of, for example, polysilicon is formed thereon.
upper gate electrode 3 made of tungsten and tungsten silicide
A gate electrode having a polycide structure formed by laminating 4a is formed. On both sides of the gate electrode, for example, sidewall insulating films 23 of silicon oxide are formed.
A source / drain diffusion layer 12 is formed in the semiconductor substrate 10 on both sides of the gate electrode, and a conductive impurity having a lower concentration than the source / drain diffusion layer 12 is formed on the channel formation region side. An LDD diffusion layer 11 is formed. As described above, the MOS field effect transistor is configured.

Further, an interlayer insulating film 24 of silicon oxide is formed on the entire surface so as to cover the transistor, and the source / drain diffusion layer 12 and the upper gate electrode 34a are formed.
Are formed, and electrodes 32 respectively connected to the source / drain diffusion layer 12 and the upper gate electrode 34a are formed.

A method for manufacturing a semiconductor device having the above MOS field effect transistor will be described below with reference to the drawings. First, as shown in FIG. 9A, an element isolation insulating film 20 is formed on a silicon semiconductor substrate 10 by, for example, a LOCOS method. Next, a gate insulating film 21 of silicon oxide is formed on the active region (channel forming region) separated by the element isolation insulating film 20 by, for example, a thermal oxidation method.

Next, as shown in FIG. 9B, for example, a CVD (Chemical Vapor Depos) is formed on the upper layer of the gate insulating film 21.
Amorphous silicon containing phosphorus as a conductive impurity is deposited at a deposition temperature of 530 ° C. and a thickness of 100 nm by the ition) method to form a lower gate electrode layer 33.
The content of phosphorus in the amorphous silicon film can be, for example, 0.06 to 0.75% by weight.

Next, as shown in FIG. 9C, a heat treatment is performed to crystallize the amorphous silicon, and a crystallized lower gate electrode layer 33a is formed. The heat treatment temperature can be, for example, 650 to 900 ° C., and the heat treatment time can be, for example, 30 minutes to 10 hours.

Next, as shown in FIG. 10D, tungsten silicide is deposited on the upper layer of the lower gate electrode layer 33a by, for example, a CVD method to form an upper gate electrode layer 34. Thus, a gate electrode layer having a polycide structure is formed.

Next, as shown in FIG. 10E, a resist film R of a gate electrode pattern is formed by a photolithography process, and is processed into a gate electrode pattern by etching such as RIE (reactive ion etching).
A gate electrode having a polycide structure composed of an upper gate electrode 34a and a lower gate electrode 33b is formed.

Next, as shown in FIG. 10F, ions of a conductive impurity D1 are implanted using the gate electrode as a mask.
An LDD diffusion layer 11 is formed.

Next, as shown in FIG. 11G, silicon oxide is deposited on the entire surface by, for example, a CVD method, and RIE is performed.
Etching is performed on the entire surface by etching such as to leave the silicon oxide on both sides of the gate electrode and to remove the remaining silicon oxide, thereby forming a silicon oxide sidewall insulating film 23.

Next, as shown in FIG. 11H, the conductive impurity D2 is ion-implanted so as to have a higher concentration than the LDD diffusion layer 11 using the sidewall insulating film 23 as a mask. 12 is formed. Above,
A field effect transistor having a source / drain region having an LDD structure is formed.

Next, as shown in FIG. 11 (i), the above-mentioned field effect transistor is covered and
Silicon oxide is deposited by a method to form an interlayer insulating film 24.

Next, a contact hole for exposing the upper gate electrode 34a and the source / drain diffusion layer 12 is opened in the interlayer insulating film 24, and the inside of the contact hole is filled with a conductive layer such as aluminum by sputtering, for example. An electrode 32 connected to the upper gate electrode 34a and the source / drain diffusion layer 12 is formed by patterning and patterning. This leads to the semiconductor device shown in FIG.

According to the method of manufacturing a semiconductor device of the present embodiment, a conductive layer serving as a gate electrode in a MOS field effect transistor is deposited on a gate insulating film as amorphous silicon containing a conductive impurity such as phosphorus. By performing crystallization in a later step, the reliability of the gate insulating film can be improved.

The method of manufacturing a semiconductor device according to the present invention is not limited to the above embodiment. For example, the control gate in the semiconductor nonvolatile memory device according to the first embodiment and the gate electrode in the semiconductor device according to the second embodiment have a two-layer structure of polycide, but have a single-layer structure or a multi-layer structure other than polycide. You can also. Also,
Various structures other than the LDD structure can be adopted for the source / drain. When a semiconductor nonvolatile memory device having a floating gate structure is used, the semiconductor memory device may be either a NOR type, a NAND type, or a DINOR type. It does not matter whether writing or erasing is performed. In addition, various changes can be made without departing from the gist of the present invention.

[0061]

According to the method of manufacturing a semiconductor device of the present invention, a floating gate in a transistor having a floating gate structure or a floating gate structure is formed on a gate insulating film.
A first conductive layer serving as a gate electrode in a MOS field-effect transistor is deposited as amorphous silicon containing a conductive impurity such as phosphorus, and is crystallized in a later step to improve the reliability of the gate insulating film. Can,
In particular, in a transistor having a floating gate structure, the number of times of data writing / erasing can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor nonvolatile memory device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating manufacturing steps of a method for manufacturing a semiconductor nonvolatile memory device according to the first embodiment of the present invention. FIG. (C) shows up to the step of forming the layer for the floating gate and up to the step of crystallization of the layer for the floating gate.

FIG. 3 shows a step subsequent to that of FIG. 2; (d) shows up to a control gate layer forming step, (e) shows up to a gate electrode pattern processing step, and (f) shows an LDD diffusion layer forming step. Up to

4 shows a step subsequent to that of FIG. 3; (g) shows up to a step of forming a sidewall insulating film; (h) shows a step up to a step of forming a source / drain diffusion layer; and (i) shows an interlayer insulating film. Up to the formation step.

FIG. 5 is a diagram illustrating a constant current TDDB (Time) according to the first embodiment;
Dependent Dielectric Breakdown) Characteristics (Qbd value)
FIG. 3 is a diagram showing the phosphorus content dependency of the present invention.

FIG. 6 is a diagram illustrating a heat treatment temperature dependency of a constant current TDDB characteristic (Qbd value) according to the second embodiment.

FIG. 7 is a diagram illustrating a heat treatment time dependency of a constant current TDDB characteristic (Qbd value) according to the third embodiment.

FIG. 8 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIGS. 9A and 9B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, wherein FIG. 9A illustrates up to the step of forming a gate insulating film, and FIG. (C) shows the process up to the crystallization process of the lower gate electrode layer.

10 shows a step subsequent to that of FIG. 9; (d) shows up to a step of forming an upper gate electrode layer; (e) shows up to a gate electrode pattern processing step; and (f) shows formation of an LDD diffusion layer. The process is shown.

FIG. 11 shows a step that follows the step in FIG. 10, and (g)
5A shows the steps up to the step of forming the sidewall insulating film, FIG. 5H shows the steps up to the step of forming the source / drain diffusion layers, and FIG.

FIG. 12 is a sectional view of a semiconductor nonvolatile memory device according to a conventional example.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a semiconductor nonvolatile memory device according to a conventional example, and FIG.
4A shows a process up to the step of forming a gate insulating film, FIG. 4B shows a process up to a process of forming a layer for a floating gate, and FIG. 5C shows a process up to a process of introducing impurities into the layer for a floating gate.

FIG. 14 shows a step that follows the step shown in FIG. 13;
4E shows the steps up to the step of forming the control gate layer, FIG. 5E shows the steps up to the step of forming the gate electrode pattern, and FIG.

FIG. 15 shows a step that follows the step in FIG. 14, and (g)
5A shows the steps up to the step of forming the sidewall insulating film, FIG. 5H shows the steps up to the step of forming the source / drain diffusion layers, and FIG.

[Explanation of symbols]

Reference Signs List 10: semiconductor substrate, 11: LDD diffusion layer, 12: source / drain diffusion layer, 20: element isolation insulating film, 21: gate insulating film, 22, 22a: intermediate insulating film, 23: sidewall insulating film, 24: interlayer Insulating film, 30, 30a, 30
c ... Floating gate layer, 30b ... Floating gate, 31 ... Control gate layer, 31a ...
Control gate, 32 ... electrode, 33, 33a ... lower gate electrode layer, 33b ... lower gate electrode, 34 ... upper gate electrode, 34a ... upper gate electrode, R ... resist film, D, D1, D2 ... impurities.

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[Procedure amendment]

[Submission date] July 30, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction contents]

Example 1 In the above embodiment, the heat treatment temperature was fixed at 830 ° C. , the heat treatment time was fixed at 30 minutes, and the phosphorus content in the amorphous silicon layer serving as the floating gate layer was 0.06 wt. %, 0.5% by weight, and 0.75% by weight. A constant current TDDB (Time Dependent Dielect) is used for these semiconductor devices and a semiconductor device as a comparative example formed by introducing phosphorus by thermal diffusion using POCl ₃ into a polysilicon layer serving as a floating gate layer by a conventional method.
ricBreakdown) characteristics (Qbd value) were examined. FIG. 5 shows the results. The intrinsic withstand voltage in the TDDB characteristic (the withstand voltage in the abrasion region) is higher than that of the comparative example in any of the semiconductor devices of the present embodiment.
It was found that the intrinsic withstand voltage was the highest at 0.75% by weight.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/115 29/78 21/336

Claims (8)

[Claims] A step of forming a gate insulating film on a semiconductor substrate having a channel forming region; and a step of forming a first conductive layer made of amorphous silicon containing a conductive impurity on an upper layer of the gate insulating film; A heat treatment step of crystallizing the first conductive layer; a step of processing the first conductive layer into a pattern of a gate electrode; and a step of forming source / drain regions connected to the channel formation region in the semiconductor substrate. A method for manufacturing a semiconductor device having: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first conductive layer is performed by adding phosphorus at a concentration of 0.06% by weight or more. 3. The method according to claim 1, wherein the heat treatment is performed at a temperature of 900 ° C. or less. 4. The method according to claim 1, wherein the heat treatment is performed for a heat treatment for 30 minutes or more. 5. The method according to claim 1, wherein in the step of forming the gate insulating film, a silicon oxide film is formed by a thermal oxidation method.
The manufacturing method of the semiconductor device described in the above. 6. A step of forming an intermediate insulating film on the first conductive layer after the heat treatment step and before processing the first conductive layer into a gate electrode pattern; The method according to claim 1, further comprising: forming a second conductive layer as an upper layer, wherein in the step of processing the first conductive layer into a gate electrode pattern, processing the intermediate insulating film and the second conductive layer into the same pattern. 2. The method for manufacturing a semiconductor device according to claim 1. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the step of forming the intermediate insulating film, a stacked insulating film of an oxide film-nitride film-oxide film is formed. 8. After the step of processing the first conductive layer into a gate electrode pattern, the method further comprises the step of forming a sidewall insulating film on a side wall of the patterned first conductive layer; The step of forming a drain region includes the steps of forming a low-concentration region containing conductive impurities by ion implantation before the step of forming the sidewall insulating film, and forming ions after the step of forming the sidewall insulating film. Implanting to form a region containing a high concentration of conductive impurities.