JPH11339497A - Testing apparatus for electronic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a testing apparatus which prevents the occurrence of a timing error by a method wherein scan data according to a test pattern is written into a memory through a first scan chain and the scan data is read out from the memory through a second scan chain which couples a plurality of unit memory circuits constituting the output circuit of the memory. SOLUTION: When a test mode is selected at the high level '1' of a selector signal from a pin 62, respective selectors in multiplexers 78 to 81, a multiplexer 96 and scan flip-flops 84, 86 select input terminals for a test mode. Signals which are input from pins 63, 64 are supplied to data terminals of flip-flops 90, 91 via the multiplexers 79, 80, and the address '0' of a memory 88 is designated. A scan clock is supplied sequentially to scan flop-flops 92 to 94 on the output side, and the same sequence is repeated with reference to all addresses of the memory 88.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electronic circuit test apparatus, for example, an ASIC (Application Specific Integrated Circuit).
It can be applied to a case where a memory built in an LSI (Large Scale Integrated Circuit) such as the above is tested using a memory test algorithm.

[0002]

2. Description of the Related Art Conventionally, to test a memory built in an ASIC, a circuit configuration as shown in FIG. 2 or 3 has been used.

In FIG. 2, one package ASIC 1
0 has input pins 11 to 13 and an output pin 14 on its outer peripheral portion. Pins 11, 12, and 14 are
Used during normal and testing.

The ASIC 10 includes input / output buffers 15 to 18, an internal logic 19, multiplexers 20 to 22, and a memory 23.

The multiplexer 20 on the input side is connected to the pin 13
Normally, the output signal from the internal logic 19 is selected according to the selector signal supplied from the
And supplies the selected signal to the memory 23. The memory 23 is an asynchronous memory that does not use a method of synchronizing data input / output with a clock.

[0006] Like the multiplexer 20, the multiplexer 21 receives the output signal of the internal logic 19 or the pin 12.
Is selected and supplied to the memory 23.

The multiplexer 22 on the output side normally selects output data of the internal logic 19 in accordance with the selector signal supplied from the pin 13, and reads out data from the memory 23 at the time of testing, and sends out the data from the pin 14. . In FIG. 2, the illustration of the configuration for specifying the address in the memory 23 is omitted.

A normal path through which the data signal in the ASIC 10 is transmitted is the internal logic 19 → multiplexers 20, 21 → memory 23 → internal logic 19, but when the memory 23 is tested, this path is
The path is changed from 12 → multiplexers 20, 21 → memory 23 → multiplexer 22 → pin 14.

In FIG. 3, one package ASIC 3
0 has input pins 31 to 34 and output pins 35 to 37 on its outer peripheral portion. Of these, the input and output pins 31, 32, 35, and 36 are used only during normal times, and the scan-in pin 34 and scan-out pin 37 are used only during testing.

In the ASIC 30, input buffers 37 to 40, internal logic 41, and scan FFs (flip-flops) 42 to 4 for data input are provided.
3, scan FFs 44 to 45 for data output, a synchronous memory 46, and buffers 47 to 49 for output.

A line extending from the pin 34 to the scan FFs 42 and 43 and further from the scan FFs 44 and 45 to the pin 37 forms one scan chain 50.

In FIG. 3, F for addressing is used.
The configuration for operating the F and the selectors in the scan FFs 42 and 43 is omitted.

In the writing period during the test, first, the memory 46 is in the writing mode, each selector in the FFs 42 and 43 selects the scan-in instead of the internal logic 41, and the scan data is written to each address. go. The scan data for writing is scan FF4
After being written to each address while moving from 2 to 43, it is transmitted on the scan chain 50 and
7 is output.

On the other hand, in the read period during the test, each address of the memory 46 in the read mode is designated, and the scan data read from each address is transmitted on the scan chain 50 and 3
7 is output.

[0015]

However, in the configuration shown in FIG. 2, the memory 23 itself is asynchronous, and the peripheral circuits do not have a configuration for synchronizing the writing and reading of data to and from the memory 23 with a clock. Therefore, there is a disadvantage that a timing error easily occurs.

In the configuration of FIG. 3, when writing and reading at the time of testing are repeated, the scan data input from the pin 34 for writing passes through the scan FF 43 and at least passes through the memory until the scan data passes through the scan FF 45. In a test using a test pattern, for example, a march pattern or the like, in which data cannot be read from the memory 46 and switching between writing and reading is repeated, the timing is long and the test time is long. The burden on external equipment for testing is large.

Furthermore, the configuration of the pins 33, 34 and 37 and the buffers 39, 40 and 49 is used only at the time of testing and is not used at normal times, so that there is much waste in the configuration.

[0018]

In order to solve this problem, the operation of a memory device comprising a memory and its peripheral circuits is performed by writing and reading data to and from a memory according to a predetermined test pattern and examining the read data. In an electronic circuit test device for checking the normality of
It is characterized by having the following configuration.

That is, according to the present invention, (1) a first scan chain for connecting a plurality of unit storage circuits constituting an input circuit of the memory, and (2) scan data corresponding to the test pattern, Writing means for writing to the memory through the first scan chain;
(3) a second scan chain for coupling a plurality of unit storage circuits constituting an output circuit of the memory;
(4) A reading means for reading the written scan data from the memory through the second scan chain.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) Embodiment Hereinafter, an electronic circuit test apparatus according to the present invention will be described with reference to an ASIC.
An embodiment will be described with reference to an example in which the present invention is applied to an (application-specific integrated circuit).

(A-1) Configuration of Embodiment FIG. 1 shows a circuit configuration of an ASIC 60 in one package according to the embodiment. The ASIC 60 has an internal logic 61 corresponding to a specific application.

In FIG. 1, input pins 62 to 66 and output pins 67 and 68 are provided on the outer periphery of the package of the ASIC 60. The pin 66 is used for switching between the normal mode and the test mode, and the pins 62 to 65 and the pins 67 and 68 are all usable in the normal mode and the test mode.

Input pins 70 are provided at pins 62 to 66.
74, the output buffers 75,
76 are connected respectively. The output terminals of the input buffers 70 to 73 are connected to multiplexers 78 to 8 respectively.
1 and one input terminal [1] and the input terminal of the internal logic 61. These multiplexers 78 to 81
The output terminal of the internal logic 61 is connected to the other input terminal [0]. The input terminals [0] of the multiplexers 78 to 81 are for the normal mode, and the input terminal [1] is for the test mode. The control terminals of the multiplexers 78 to 81 are connected to the input terminal [0] or
A pin 66 for receiving a selector signal for switching the selection of [1] is connected.

The output terminal of the multiplexer 78 has a scan chain 83 and a scan F at the lowermost end on the data input side.
F84 is connected, but this part C1 surrounded by a broken line
4 is shown in FIG.

As shown in FIG. 4, the scan FF 84 includes a selector 84A and a D flip-flop 84B. Similarly, the uppermost scan FF 86 on the data input side also includes a selector 86A and a D flip-flop 86B. Although omitted in FIG. 1, between the scan FFs 84 and 86, a selector 85A and a D flip-flop 85 are similarly provided.
A required number of scan FFs such as the scan FF 85 having B are provided.

The selectors 84A to 86A select the input terminal [0] or [1] in accordance with the selector signal supplied from the pin 66, and transmit the signal supplied to the input terminal [0] or [1] to each D. This is a circuit connected to the input terminals D of the flip-flops 84B to 86B.

In the scan chain 83, the output terminal of the multiplexer 78 and the input terminal [1] for the test mode of the selector 83A are connected by the scan chain 83A at the lower end. The scan chain 83 is the second scan chain 83B from the bottom, and the FF 84
B output terminal Q and selector 85A in scan FF 85
And input terminals [1] of the selectors in the scan FFs above the output terminals Q of the FFs are sequentially connected in the same manner. Has become. The output terminals Q of these FFs 84A to 86B
Respectively represent the write data lines D1 (ＤD
i) Since they are also connected to D2, the scan FFs 84 to 86 function as shift registers for serial input and parallel output as far as the test mode is concerned.

The input terminal [0] for the normal mode of the selector 84A is connected to the output terminal of the multiplexer 78, and the input terminal [0] for the normal mode of the selectors 85A and 86A is connected to the internal logic 61. Connected to output terminal.

The output terminals of the multiplexer 81 are connected to the clock input terminals of the D flip-flops 84B to 86B in order to receive the supply of the scan clock in the test mode and the supply of the normal clock in the normal mode.

Returning to the description of FIG.

In FIG. 1, a scan FF 84 is provided on the input side.
FFs 90 to 91 arranged below the D flip-flops for address designation, have their data input terminals connected to the output terminals of the multiplexers 79 to 80, and their output terminals connected to the address lines A1 to A2 of the memory 88. Have been.
The required number of multiplexers are provided between the multiplexers 79 and 80, and the same number of FFs are provided between the FFs 90 and 91. The FFs and the multiplexers are connected one-to-one. .

Each of the clock input terminals of the FFs 90 to 91 is connected to a pin 65 via a multiplexer 81, and is supplied with the same scan clock as the FFs 84B to 86B.

A WRN signal is supplied to a WRN terminal of the memory 88 via a line (not shown), and the memory 88 is switched between a write mode and a read mode.

On the other hand, on the output side of the memory 88, a portion C2 and a scan chain 95 surrounded by a broken line are replaced with a portion C1 and a scan chain 83 on the input side shown in FIG.
Perform the operation corresponding to. The part C2 and the scan chain 95 also function as a kind of shift register in the test mode. However, this shift register is a parallel input serial output contrary to FIG.

Read data lines Q1 to Q2 of the memory 88
The scan chain 95 that serially transmits the data of one word read from the MPU 1 supplies the serial data to the input terminal [1] of the multiplexer 96.

The output terminal of the internal logic 61 is connected to the input terminal [0] for the normal mode of the multiplexer 96. As shown in FIG. 1, the output terminal of the multiplexer 96 is connected to the input terminal of the output buffer 76, and the output terminal of the internal logic 61 is connected to the input terminal of the buffer 75.

The write data line D1 of the memory 88
To D2 and the read data lines Q1 to Q2 have the same number and the same word length, and have a one-to-one correspondence.
The number of 1 to A2 is determined by the capacity of the memory 88 and the number of ports
It is determined according to the configuration and the like.

Hereinafter, the operation of the present embodiment having the above configuration will be described.

(A-2) Operation of the Embodiment In order to test the memory 88, first, a selector signal is supplied from outside the ASIC 60 via the pin 66. As shown in FIG. 5B, when the test mode is selected at the high level "1" of the selector signal, the selectors 84A to 86A in the multiplexers 78 to 81, the multiplexer 96, and the scan FFs 84 to 86 Select the input terminal [1] for all test modes. Therefore, for example, as shown in FIG.
Even if the low level “0” is supplied from the internal logic 61 to the input terminal [0] of the selector 86A in F86, this signal has no meaning and is invalid.

Similarly, in the test mode, FIG.
(G) Input terminal [0] of the multiplexer 78, FIG.
Signals supplied from the internal logic 61 to the input terminal [0] of the multiplexer 80 in (H) and the input terminal [0] of the multiplexer 79 in FIG.

Each selector 92B-94B in the scan FFs 92-94 is operated by the selector signal "1" in FIG.
Selects the output terminal [1] for the test mode.

FIG. 5 assumes that the process of writing "0" to all bits from the lowest address to the highest address of the memory 88 has been completed in the previous process shown.

At the timing when the fifth scan clock S1 from the left end in FIG. 5A is supplied via the pin 65, as shown in FIG. Is a read mode.

The signals input from pins 63 to 64 are supplied to FFs 90 to 91 via multiplexers 80 to 79.
, And designates an address “0” of the memory 88 as shown in FIG.

In this state, the scan clock S1 of FIG. 5A is sequentially supplied to the scan FFs 92 to 94 on the output side. At the rise of the scan clock S1, the data "0" on the read data lines Q1 to Q2 of the memory 88 is read.
Are output from the output terminal Q such as the scan FF 92 in order from Q1, as shown in FIGS. 5 (L) and (M). In the order, the output data of the scan FF 92 at which the scan clock S1 arrives earlier in the configuration of FIG. 1 is first, and the output data of the scan FF 94 is last.

FIG. 5L showing the output of the scan FF 92.
(M) showing the output of the scan FF 94 as compared to FIG.
Rise and fall are delayed by one scan clock, respectively.
Scan FF9 after reaching the lower end scan FF92
4 indicates that it takes less than the scan clock interval to reach 4. This time may be longer.

Next, while the signal supplied from the pins 63 to 64 continues to specify the address "0", the scan clock S2 is supplied from the pin 65, and
(D) WRN is at the low level, that is, the write period W1
And the memory 88 enters the write mode.

The signal supplied from the pin 62, that is, the scan data, has been at the high level "1" before this time, as shown in FIG. As shown in FIGS. 5J and 5K, scan FFs 84 to 86 on the input side.
Already has its output Q set to "1" at the rise of the scan clock S0 before the scan clock S1.

The output Q of these scan FFs 84-86
Is stored in the address “0” of the memory 88 which has been in the write mode during the period W1.

Then, in the read mode in the period R2, these data "1" read from the memory 88 are output from the scan FFs 92 to 94. During this time pin 6
The scan data supplied from 2 changes from “1” to “0” as shown in FIG.

This scan data "0" is applied during period R2.
Next, in the writing period W2, the data is written to the address “0” of the memory 88.

Therefore, in the next reading period R3, data "0" is output from the pin 68.

During the reading period R3, the pins 63 to 63
The signal supplied from 64 changes, and the address "1" is designated as shown in FIG.

Thereafter, reading and writing are performed for address "1", address "2",... And all addresses of the memory 88 in the same sequence.

The time chart of FIG. 5 shows a part of an example in which a so-called marching pattern, which is one of the test patterns with the smallest number of cycles, is changed by changing the order of the patterns so that the address change is reduced. It is shown.

In this march pattern, processing of writing "0" to all bits from the lowest address to the highest address and reading "0" from the lowest address to the highest address are performed on the memory 88 to be tested. A table sequence consisting of a process of writing “1”, a process of reading “1” from the highest address to the lowest address and writing “0”, and a process of writing “1” to all bits from the lowest address to the highest address , A process of reading "1" from the lowest address to the highest address and writing "0", and a process of reading "0" from the highest address to the lowest address and writing "1". A back sequence and the like are sequentially performed.

By changing the timing of each signal in FIG. 5, the march pattern can be executed in a sequence in which the address is frequently changed as described above.

In the above description, the test was performed without the intervention of the internal logic 61. However, the test of the internal logic 61 and the memory 88 can be performed by utilizing the internal logic 61. First, the selector signal shown in FIG.
Are supplied to D1 to D2 and A1 to A2 of the memory 88 and stored in the write mode. Then, the selector signal is set to the high level to set the test mode, and the data stored in the memory 88 is transmitted to the internal logic 61. Take it out without going through. Thus, the internal logic 61 can be tested together with the memory 88.

On the contrary, first, the internal logic 61
By storing data in the memory 88 from the outside without going through the memory, and then reading and using the data in the internal logic 61, the internal logic 61 can be tested together with the memory 88.

Further, the test results obtained by these methods are as follows:
By combining and analyzing the above test results, only the internal logic 61 is tested, the memory 88 is tested, and the interface between the internal logic 61 and the memory 88 is tested. Gender can be checked.

It should be noted that a high level signal (FIG. 5)
In the normal mode where (B)) is not supplied, the input terminals [0] of the multiplexers 78 to 81 and 96 and the selectors 84A to 86A are selected, and the internal logic 61 and the memory 88 are selected.
In between, data will be exchanged.

(A-3) Effects of Embodiment As described above, according to the ASIC 60 of this embodiment, even in a test using a test pattern in which switching between writing and reading such as a march pattern is repeated, the timing is synchronized. In addition to being less prone to errors, there are fewer restrictions on timing, so that the test time can be shortened and the load on the external test equipment is small.

Further, all the pins used in the test mode of the ASIC 60 can be used in the normal mode, and have an efficient configuration.

(B) Other Embodiments In the above description, the march pattern has been mainly described. However, the electronic circuit test apparatus of the present invention can use other test patterns. There is a great advantage when using a test pattern in which switching between read and read is repeated.

The configuration of the part C1 is not limited to the above-described one. Any circuit having a function of shifting serially input data to the memory 88 while shifting it according to the scan clock can be used. It may be a configuration. Similarly, the configuration of the portion C2 may be any configuration as long as the circuit can serially output data input in parallel from the read data line of the memory 88 according to the scan clock. In short, part C
1 and C2 may have any configuration as long as they are circuits having a function as a scan chain.

The write data line D1 of the memory 88
The order in which data is input to .about.D2 may be from the lowest D1 as described above, or may be from the highest D2. Similarly, the read data lines Q1 to Q1 of the memory 88
The order in which data is output from Q2 may be from the lowest Q1, or vice versa.

Further, the data may be written in the memory 88 from the lowermost bit D1 and read out from the uppermost bit Q2. This is because the test external device recognizes this point and performs necessary processing such as rotating each word.

It is assumed that the peripheral circuit of the memory described in the claims can also include the internal logic 61. Therefore, the memory device may include an ASIC or the like.

The scope of application of the present invention is not limited to ASICs, but can also be used for testing ICs including a memory, and for externally testing a substrate on which a memory IC is mounted.

That is, according to the present invention, when the normality of the operation of the memory device including the memory and its peripheral circuit is checked by writing and reading to and from the memory in accordance with a predetermined test pattern and examining the read data, Can be widely applied.

[0071]

As described above, according to the present invention, even in a test using a test pattern in which switching between writing and reading such as a march pattern is repeated, a timing error hardly occurs, and timing restrictions are reduced. Therefore, the test time is short, and the load on external devices used in the test is small.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration of an ASIC according to an embodiment.

FIG. 2 is a schematic diagram showing a configuration of a conventional ASIC.

FIG. 3 is a schematic diagram showing a configuration of a conventional ASIC.

FIG. 4 illustrates an input scan FF of the ASIC according to the embodiment.
It is a detailed configuration of a part.

FIG. 5 is a time chart of the ASIC according to the embodiment.

[Explanation of symbols]

10, 30, 60: ASIC, 11 to 13, 14, 31
... 37,62-68 ... pins, 20-22,78-81,
96 ... multiplexer, 23, 46, 88 ... memory, 8
4B-86B, 90-91 ... D flip-flop, 5
0, 81, 95: scan chain, S0 to S2: scan clock, R1 to R5: readout period, W1 to W
4: Write period.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takeshi Oba 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. An electronic circuit test apparatus for writing and reading data to and from a memory in accordance with a predetermined test pattern and checking the read data to check the normal operation of a memory device including the memory and its peripheral circuits. A first scan chain for coupling a plurality of unit storage circuits constituting an input circuit of the memory; and a writing means for writing scan data corresponding to the test pattern to the memory through the first scan chain. A second scan chain that couples a plurality of unit storage circuits that constitute an output circuit of the memory; and a reading unit that reads out the written scan data from the memory through the second scan chain. A test apparatus for an electronic circuit, comprising: 2. The electronic circuit test apparatus according to claim 1, wherein a multiplexer is provided between an external terminal of the memory device provided for connecting an external device and the input circuit, and the external terminal is tested. An electronic circuit testing device characterized by being used both at normal and normal times. 3. The electronic circuit test apparatus according to claim 1, wherein a multiplexer is provided between an external terminal of the memory device provided for connecting an external device and the output circuit, and the external terminal is tested. An electronic circuit testing device characterized by being used both at normal and normal times. 4. The test apparatus for an electronic circuit according to claim 1, wherein the memory device is an application-specific integrated circuit having an internal logic for performing a predetermined function in addition to the memory. Characteristic electronic circuit test equipment.