JPH11339485A - Flash eeprom system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash EEPROM system. SOLUTION: The flash EEPROM system comprises a processor 21 and a memory system comprising an array 33 of nonvolatile floating gate memory cells divided into a plurality of sectors. The sector includes a definite group of the memory cell arrays erasable simultaneously as one unit. At least one user data section and overhead section of memory cell are provided in each sector, an address in a format for designating at least one magnetic disc sector from a processor, and the address of at least one nonvolatile memory sector corresponding to at least one magnetic disc sector is designated in response to that address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a semiconductor electrically erasable program read only memory (EEprom), and more particularly to a system integrating flash EEprom chip circuits.

[0002]

2. Description of the Related Art Computer systems typically use magnetic disks to store large amounts of data. However, disk drives have disadvantages in that they are large and that they require highly precise mechanical drives. Therefore, they are not rugged, have not only reliability problems, but also consume considerable power. DRAMs and SRAMs, which are solid-state storage devices, do not have these disadvantages. However, they are fairly expensive, require constant power to maintain their memory (volatility), and are expensive.

[0003] EEprom and Flash EEprom are similarly solid state storage devices. However, it is non-volatile and retains its memory even after power has been lost. However, normal flash EEpro
m is the write (or program) they can withstand
/ Has a finite life in the number of times of erasing. Typically, these devices become unreliable after 10 ² to 10 ³ write / erase cycles. Conventionally, such devices have been used where semi-permanent data or program storage is required, and where there may be some restrictions on the need for reprogramming.

[0004]

SUMMARY OF THE INVENTION Accordingly, one object of the present invention is to provide a flash EEprom storage system having an extended function capable of withstanding a considerable number of times of writing / erasing and maintaining reliability. is there. Yet another object is to provide an improved flash EEprom system that can be used as non-volatile memory in a computer system. It is yet another object of the present invention to provide an improved flash EEprom system that can be used instead of a magnetic disk drive in a computer system. It is yet another object of the present invention to provide a flash EEprom system with improved erase operations. Still another object of the present invention is to provide a flash EEprom system capable of performing improved error correction. Yet another object of the present invention is to provide a flash EEprom by improving write operations.
An object of the present invention is to provide a flash EEprom that can minimize stress on a system. It is still another object of the present invention to provide a flash EEprom system with improved write operations.

[0005]

SUMMARY OF THE INVENTION The above and additional objects are achieved by improvements in the structure, circuitry, and technology of EEprom chip systems.

One feature of the present invention is that the EEpr on chip
An array of om cells is organized into sectors, and all cells contained in each of those cells are erased simultaneously. Flash EEprom memory systems have one or more flash EEprom chips under the control of a controller. In the present invention,
It allows any combination of sectors between chips to be erased simultaneously. This makes the system according to the invention faster and more effective than the conventional arrangement in which all conventional sectors are erased every time or one sector is erased at a time. In the present invention, any combination for erasing a sector or any combination that is not selected in order to prevent further erasure in an erasing operation is made possible. This feature is important in stopping extra erasing of sectors that were initially correctly "erased", thereby preventing unnecessary stress on the flash EEprom system. .
In the present invention, by allowing all sectors in the entire system not to be selected as a whole, it is possible to prevent all sectors from being selected for erasure. The overall reset is to return the system to a state of selecting a sector to be selected for its initial erase. Yet another feature of the invention is that the selection is made independently of a chip select signal that selects a particular chip for a write, read or write operation. This means that one chip of the EEprom chip can be selected for erasing that is not included in another chip on which another read or write operation is being performed.

In accordance with another aspect of the invention, an improved error correction circuit used to correct errors originating from defective flash EEprom memory cells, or
Technology is to be used. One feature of the present invention is to allow mapping of defective cells at the cell level, thereby allowing replacement of defective cells with cells of the same sector. A defect pointer for connecting the defective cell to the address of the replaced cell is stored in the defect map. Each time a defective cell is accessed, its bad data is replaced with good data from a replacement cell.

[0008] Yet another feature of the present invention is to allow defect mapping at the sector level. When the number of defective cells in one sector exceeds a certain number, the sector containing the defective cell is replaced by another sector.

An important feature of the present invention is that defective cells and defective sectors are remapped as soon as they are found. Thus, by appropriately correcting the error correction code, errors that may occur in the system can be minimized.

In accordance with yet another aspect of the present invention, the provision of a write cache provides a flash EEpro.
That is, the number of times of writing to m can be minimized. This is to prevent the flash EEprom memory from being aged by subjecting it to less stress generated by the number of times of writing / erasing. The most active data file is written to cache memory instead of flash EEprom memory. When the level of activity is reduced to a predetermined level, a data file is written from cache memory to flash EEprom memory. Another advantage of the present invention is increased by using faster cache memory.

In accordance with yet another aspect of the present invention, a printed circuit board having a controller and an EEprom circuit chip for long term non-volatile storage is provided as a computer system memory, but is provided instead of a hard disk system. Is Rukoto. The printed circuit card can then incorporate various other features of the present invention, alone or in combination.

Further objects, features and advantages of the present invention will be understood from the following description of a preferred embodiment of the present invention with reference to the accompanying drawings.

[0013]

DETAILED DESCRIPTION OF THE INVENTION (EEprom System) A computer system incorporating various features of the present invention is shown generally in FIG. 1A. A typical computer system has a microprocessor 21 connected to a bus line 23, thereby allowing random access to main system memory 25, and at least one or more input / output devices 27, such as a keyboard, monitor, modem And so on. Another major computer element connected to a typical computer system bus 23 is a large amount of long-term non-volatile memory 29. Typically such a memory is a disk drive system with 10 megabytes of data storage capacity. Data is easily retrieved and used in volatile memory 25 in the system, and is easily replenished, changed, or changed.

One aspect of the present invention is to change the above-described disk drive system to a certain semiconductor memory. In this case, the system is non-volatile, and the erasing and rewriting of data in the memory is easy. Do not sacrifice access speed, cost and reliability. This is an electrically erasable and programmable read only memory (E
It is completed by using a semiconductor circuit chip of Eprom). This type of memory has the additional advantages of lower operating power and very light weight compared to those that drive magnetic memory media with a hard disk, thereby making it portable and battery operated. It can be said that it is suitable for computers.

The entire storage device 29 is a memory controller 31 connected to the system bus 23 of the computer.
And an array 33 of EEprom integrated circuit chips. Data and instructions are uniquely communicated from the controller 31 to the EEprom array 33 via the serial data line 35. Similarly, the data and the status signal are communicated from the EEprom 33 to the controller 30 via the serial data line 37. FIG. 1A does not show other control and status circuits between the controller 31 and the EEprom array 33.

Referring to FIG. 1B, the controller 31
Are preferably formed on one integrated circuit chip. A system address and data bus 39, which is part of the system bus 23, is connected to a system and system control line 41, which includes read, write and other normal computer system control lines. .

The EEprom array 33 includes a plurality of EEprom integrated circuit chips 43, 45, 47, and the like. Each is provided with a respective chip select and enable line 49, 51, 53 from the interface circuit 40.
Contains. The interface circuit 40 further functions as an interface between the circuit 57 and the serial data lines 35 and 37. Memory location addresses and data written to or read from the EEprom chips 43, 45, 47 are transferred to the memory chips 43, 45, 47 via a bus 55, a logic and register circuit 57 and another bus 59.
And so on.

The entire memory 29 shown in FIGS. 1A and 1B is manufactured in a memory size appropriate for one printed circuit card. The various system buses 39 and 41 of FIG. 1B, along with other computer systems, are connected to the connection pins of such a card. In addition, various standard power supply voltages (not shown) are connected to the card and its components.

For large amounts of memory, one array 3
3 may not be enough. In such a case, an additional EEprom array can be connected to the serial data lines 35, 37 of the control chip 31. This is preferably done by one printed circuit card, but if there is not enough space to do so, one or more EEprom arrays may be placed on the second printed circuit card. And providing it physically on the first one, or by providing it and connecting it to a common controller chip 31.

(Erase of Memory Structure) In a system design in which data to be stored is performed as a file or a block, the data is periodically revised,
Or new information needs to be inserted. In some cases, it is desired to store additional information by performing further writing on information that is no longer needed. In flash EEprom memories, memory cells must first be erased before storing information. In other words, this means that an erase operation always precedes a write (or program) operation.

In a conventional flash erase memory device, there are several methods of erasing operation, one of which is performed. For example, Intel Corporation 2
7F-256, CMOS flash EEprom erases entire chip at once. If not all of the information on the chip should be erased,
First, the information must be temporarily rescued. It is then written to another memory (typically RAM). The information is then restored into the nonvolatile flash erase memory by reprogramming the device. This is time consuming, expensive, and requires work space.

Other devices, such as Seek Technology
Incorporated Model 48512 Flash E
In Eprom chips, the memory is divided into blocks (or sectors), which can be separately separated and erased. However, it must be done one by one each time. Upon selection of a desired sector, an erasing step is started, and the designated area is erased. Although the need for temporary storage is eliminated, erasing various memory areas still requires time consuming sequential work.

In the present invention, the flash EEpro
The m-memory is divided into several sectors, where the cells contained in that sector can be erased simultaneously. Each sector is addressed separately and selectively erased. The most important feature is that several sector combinations can be selected to be erased together. This can provide a faster erasing system as compared to what is found in the prior art of erasing each independently.

FIG. 2 schematically illustrates several sectors selected for erasure. One Flash EEprom
The system includes one or more flash EEprom chips, eg, 201, 203, 205. They are connected via line 209 to controller 31
Communicating with Typically, controller 31 itself is in communication with a microprocessor system (not shown). The memory in each flash EEprom chip is divided into sectors, and all storage cells in one sector can be erased simultaneously. Available to the user, for example, each sector has 512 bytes (ie, 512 × 8 cells), and one chip has 1024 bytes.
Have a sector. Each sector is independently addressably divided and, for example, sectors 211, 21
A plurality of sectors, such as 3, 215, 217, etc., are selected to be erasable. As shown in FIG. 2, the selected sector can be limited to one EEprom chip or distributed among several chips in the system. The selected sectors will be erased at the same time. This capability allows the memory system according to the present invention to operate faster than with conventional structures.

FIG. 3A is a block diagram illustrating a flash EEprom (eg, chip 201 of FIG. 2) with one or more sectors selected or not selected for erasing. In practice, each sector,
For example, 211 or 213 is provided in association with each sector. For example, depending on whether the state of an erasable register such as 211 or 213 is set or whether a tag is selected or selected depending on the setting, 223
Is selected. The selection and the subsequent erasing operation are performed under the control of the controller 31 (see FIG. 2).
The circuit 220 is in communication with the controller 31 via a plurality of lines 209. Command information from the control is captured in circuit 220 by command register 225 via serial interface 227. Then, it is decoded by the command decoder 229, and the command decoder 229 outputs various control signals. Similarly, address information is captured by address register 231 and decoded by address decoder 233.

As an example, to select sector 211 for erasure, the controller sends the address of sector 211 to circuit 220. This address is on line 23
5, which is decoded in register 221
Is used in conjunction with the erase enable signal on enable bus 237 to set output 239 to HIGH. As a result, the sector 211 can perform a subsequent erasing operation. Similarly, if sector 213 is required to be erased as well, its associated register 23 of register 223 will also be set high.

FIG. 3B shows the structure of the register 221 or 223 in more detail. The erase enable register 221 is a SET / RESET latch. The set input terminal 241 is obtained from the erase enable signal set of the bus 237 gated by the address decode line 235. Similarly, reset input 243 is connected to line 235
Bus 237 gated by address decode in
Obtained from those that clear the erase enable signal inside. In this way, when the erase enable signal or the signal for clearing the erase enable signal is generated in all the sectors, the signal becomes valid only in the addressed sector.

After all sectors to be erased have been selected, the controller returns to circuit 220, also when all global erase commands are represented by 251 at line 2.
A high voltage for erasing is generated along 09. Thus, the device will erase all selected sectors (eg, sectors 211 and 213) simultaneously. In addition to the desired sectors in the chip being erased, the structure according to the invention allows the selection of sectors on different types of chips for simultaneous erasure.

FIGS. 4 (1)-(11) illustrate the algorithm used in connection with the circuit 220 of FIG. 3A. In FIG. 4 (1), the controller shifts the address in circuit 220 to the erase enable register associated with the sector to be erased that has been decoded.
In FIG. 4B, the controller decodes to set the erase enable command used to latch the address decoded signal into the erase enable register of the addressed sector. This tag is for subsequent erasure of the sector. In FIG. 4 (3), if more sectors are to be tagged, FIG. 4 (1) to FIG. The related operation shown in (2) is repeated.
After all the sectors to be erased have been tagged, the controller initiates the erase cycle shown in FIG. 4 (4).

An optimized erase arrangement is disclosed in a co-pending US patent application. They were filed on June 8, 1988 by Dr. Eliyahou Harari in co-pending U.S. patent application Ser. Read / Write Circuit and Its Technology ". The flash EEprom cell is erased by applying an erase pulse, and subsequent reading verifies that the cell has been erased and is in an erased state. If not, the pulse application and verification are repeated until the cell is verified to be in the erased state. By erasing in this controlled manner, the cell is EEpro
m is aged or protected from over-erasure which would make programming difficult.

Others may reach an erased state sooner when a selected group of sectors is in an erase cycle. Another important feature of the present invention is the ability to remove sectors that have been verified for erasure from the selected group, thereby preventing over-erasure.

Referring again to FIG. 4 (4), once all sectors to be erased have been tagged, the controller initiates an erase cycle for the group of tagged sectors. In (5) of FIG. 4, the tag EE to be erased is used.
Shift a global command called global erase enable through the prom chip. This means that in FIG. 4 (5), the controller has a certain duration,
This means that the erase voltage (VE) is increased by a certain value. The controller reduces this voltage at the end of the erasure period. In (6) of FIG. 4, the controller performs read verification of a sector selected for erasing. In (7) of FIG. 4, if none of the sectors is verified, the sequence shown in (5) to (7) of FIG. 4 is repeated. 4 (8) to 4 (9), if one or more sectors are verified as erased, they are taken out of the sequence. Referring also to FIG. 3A, this lowers the erasable register by clearing the erase command in bus 237 to the address of the controller corresponding to each verified sector. The sequence shown in (5) to (10) of FIG. 4 is repeated until it is verified that the group has been erased as shown in (11) of FIG. Upon completion of the erase cycle, the controller transitions to a no-operation state (NOP) command, and the global erasable command is pulled up to protect against erroneous erasure.

The ability to select which sectors to erase or not to erase is as effective as stopping which erases is effective. As a result, those which have been erased before the sector to be erased later are separated from the erase sequence, and can be protected from being subjected to the above stress by the device. This would improve the reliability of the system. It is advantageous to skip a sector if it is bad or unavailable for some reason, so that erasure does not occur in that sector. For example, if a sector is defective and there is a short circuit, it will erase more power. By skipping the erase cycle, the present invention has the significant system advantage of reducing the power required for erasure in the chip.

Having the ability to select the sectors to be erased in the device leads to another consideration in reducing the power consumption of the system. The resiliency of the erasure structure in the present invention allows erasure requirements to be adopted according to the power capabilities of the system. This may be accomplished by providing the system with different erase states by software or by providing a basic structure with other systems.
It could also cause the controller to change the amount of erasure by monitoring the voltage level in a system such as a laptop computer.

Still another feature of the system in the present invention is the ability to issue a reset command to the flash EEprom chip to clear all erase enable latches, and to prevent further erase cycles. This is shown in FIG. 2A and FIG.
One reset signal is shown. Performing this operation invariably for all chips would reduce the time to reset all erase enable registers.

Another additional capability is the ability to perform an erase operation independent of chip select. When an erasing operation is started in a certain memory chip, the controller can access other memory chips to read and write them. In addition, it is selected that the erasing device is erasing, and the address of the command for the next erasing can be stored.

(Defect Mapping) Physical defects in the memory device cause difficult malfunctions. Data is destroyed each time it is stored in a defective cell. In conventional memory devices, such as RAMs and disks, any physical defects that occur during the manufacturing process are corrected at the factory. In a RAM, a spare redundant memory cell is provided on a chip, which is connected instead of a defective cell. When the medium is incomplete in the conventional disk drive device, it is liable to be a defect problem. To solve these problems, manufacturers have devised various methods for these defects that exist, and the most commonly used is the mapping of sector defects. In a normal disk system, a medium is divided into cylinders and sectors. A sector is a basic unit for storing data. In the system, those which are divided into various sectors and which are marked as bad are not used in the system. This has been achieved in various ways. A table of defect maps is provided at a specific position on the disk to be used and is used via the interface controller. Further, a bad sector having a defect is physically given a special ID, and is given an ID and a flag marker. When the defective one is addressed, the data is usually located at another alternate location. Due to the requirement of this alternative sector, extra sectors are provided at certain intervals or at certain locations. This reduces the capacity of the memory and offers the problem of how to provide alternative sectors.

One important application of the present invention is to replace conventional disk storage with a system implemented by an array of flash EEprom chips. The EEprom system is preferably set to be equal to or more than a conventional disk, and can be regarded as a “solid disk”.

In a "disk" system made with such a solid-state memory device, care must be taken that it can be achieved at a low cost in order to handle defects efficiently. Another important feature of the invention is that it allows error correction so that more memory can be saved as much as possible. As a practical matter, it means that a defective cell is searched for every cell so that the entire sector, for example (usually 512 bytes), is not thrown away every time a defect occurs. This proposal is particularly suitable for flash EEprom media. This is because the majority of errors occur as bit errors, and the streams typically found on conventional disk media are not long, adjacent defects.

In the prior art, both RAM and magnetic disk, once the device is shipped from the factory, there is little or no means to replace hard errors resulting from physical defects that appear after normal operation. There is nothing at all. For this reason, defect correction is mainly performed by using an error correction code (ECC).

Due to the nature of the flash EEprom device, cell defects can be expected to increase gradually as the number of times of writing / erasing increases. Errors in the hardware that accumulates when used eventually overwhelm the ECC,
It renders the device unusable. One important feature of the present invention is the ability to correct the system hardware error whenever the system hardware error occurs. Also during the read operation, a defective cell is found and E
Positioned by CC. As soon as a defective cell is identified, the controller will provide a defect mapping to replace the defective cell with a free cell, which is normally located in the same sector. This dynamic hard error correction can effectively extend the life of the device in addition to the normal error correction scheme.

Another feature of the present invention is that it is suitable for an approach to error correction. Error correction code (EC
C) is always used to correct soft errors and to correct hard errors that may occur. As soon as a hard error is detected, the defect mapping is used to replace the defective cell with a spare cell present in its same sector block. Only if the number of defective cells exceeds the capability of defect mapping for that particular sector is the entire sector replaced by a regular disk system. This scheme can be halted with minimal loss without compromising credibility.

FIG. 5 illustrates the memory structure of the cell remapping scheme. As previously mentioned,
The flash EEprom memory is divided into sectors, and cells belonging to each sector can be erased at the same time. A typical memory structure of the sector 401 is a data section 4
03 and a spare (or shadow) unit 405. The data section 403 is a memory space that can be used by a user. The spare part 405 further includes a substitute part area 4 for defect data.
07, a defect mapping area 409, a header area 411,
And an ECC and another area 413. These areas include information that can also be used by the controller to manipulate defective areas and other overhead information, such as headers and ECC.

Each time a defective cell is found in a sector, one good cell in the defective data area replacement section 407 is allocated to back up data designated as a defective cell. Thus, if data is erroneously stored in the defective cell, an error-free copy is stored in the backup cell. The addresses of the defective cell and the backup cell are stored in a defect pointer in the defect map 409.

It should be understood that there is no need to strictly distinguish between the user data area 403 and the spare section 405. The relative size of each assigned area can be logically reassigned. Furthermore, the grouping of various areas is needed mainly for discussion,
Not physically required. For example, the replacement part 407 of the defective data area merely indicates that the area occupied by the spare part 405 is not available to the user.

In a read operation, the controller first reads the header, the defect map, and then the replacement defect data portion. Then read the actual data. It keeps track of the defective cell and the location of the replacement data by the defect map. To encounter a defective cell, the controller substitutes the bad data with good data from the defective replacement cell.

FIG. 6 illustrates the read data path control in the preferred embodiment. The memory device 33 includes a plurality of flash EEproms under the control of the controller 31.
Includes chips. The controller 31 itself forms part of a microprocessor system under the control of a microprocessor (not shown). To start reading a sector, the microprocessor loads the address generator 503 in the controller with the address to start the read operation. This information is loaded via the interface port 505 of the microprocessor. The microprocessor then loads the DMA controller 507 with a buffer memory or a start location on the address bus where data reads are to be sent. The microprocessor then stores the header information (head, cylinder, sector) in the register file 509.
To load. Finally, the microprocessor loads a read command into the command sequencer 511 before controlling the controller 31.

After starting the control, the controller 31 first addresses the sector header and verifies that the memory has been accessed at the address specified by the user. This is achieved by the following sequence. The controller selects one memory chip (chip select) in the memory device 33, and outputs the address of the header area from the output of the address generator 503 to the memory device 33.
Is shifted to the selected memory. The controller switches the multiplexer 513 and the memory device 33
To shift the read command output. The memory device then reads the sent address and begins transmitting serial data from the addressed sector to the controller. A receiver 515 in the controller receives this data and places it in a parallel format. In one embodiment, one byte (8 bits) is compiled at a time and the microprocessor compares the received data with the header information pre-stored in holding register file 509. If the result of the comparison is correct, correct information and a correct position are verified (verified), and the operation continues.

Next, the controller 31 reads the defect pointer and loads the positions of these defective addresses into the holding register file 509. This was followed by reading of the controller's defective data, the replacement of which was written to replace the wrong bit when it was written. The replacement bits are stored in a replacement file 517 of defective data, which is accessed when the data bits are read.

When the headers match and the loading of the defective pointer and replacement bits is completed, the controller begins shifting out the lowest address of the desired sector to be read. Data from a sector in the memory device 33 is transferred to the controller chip 31. Receiver 515 converts the data into a parallel format and transports each byte to a temporary holder, FIFO 519, for transmission from the controller.

When the pipeline structure is changed from the receiver 515 to F
Used to start the controller to IFO 519 to provide efficient processing power when data is gated. As each data bit is received from memory, the controller continues to compare the address of the data to be sent (stored in address generator 507) with the defect pointer map (stored in register file 509). . If the match of the output of comparator 521 determines that the address is in a bad location, the bad bit from memory received by receiver 515 is replaced with a good bit in that location. The good bits come from the defective data replacement file. This is done by switching the multiplexer 523 to receive good bits from the defective data replacement file instead of bad bits from the receiver 515.
When there is corrected data in the FIFO, it is ready to be sent to buffer memory or system memory (not shown). The data is
DMA controller 5 from I / O 519
07 to the system memory. The controller 507 then requests access to the system bus, and issues an address, and gates data via the output interface 255 onto the system bus. This is done by loading each byte into FIFO 519. The corrected data is F
When loaded into the IFO, it is also gated to the ECC hardware 527, where the data file is
Processed by C.

Thus, in the manner described above, data read from memory device 33 is gated to be sent to the system via controller 31. This process continues until the last bit of the addressed data has been transferred.

Despite the defect mapping of the previously detected defective cell, a new hard error may occur at the last mapping transition. The latest hard errors that may occur during defect mapping as dynamic defect mapping permanently pushes out new defect cells are fully handled by the ECC. As the data is gated by the controller 31, the controller determines whether the stored value matches the remaining value just calculated,
The CC bit is gated into the ECC hardware 227. If it matches, the read operation has been completed, assuming that the data transferred to system memory was correct. However, if there is an error in the ECC register, a correction calculation is performed on the data sent to system memory. Then, the corrected data is retransmitted. The method of calculating the error is performed by a usual method in hardware or software. The ECC can calculate and locate defective cells due to errors. This is controller 3
1 is used to update the defect map in relation to the sector in which the defective cell was found. In this way, hard errors are always excluded from the flash EEprom system.

FIG. 7 illustrates write data path control in the preferred embodiment. The first part of the writing sequence is common to the reading sequence already described. The microprocessor first loads the memory device 33 and the address pointer for the DMA as in the reading sequence. It stores the desired header in the address generator 50.
3 and then load the command queue into the command sequencer 511. The command queue is loaded together with the read header command first. afterwards,
Control is passed to the controller 31. The controller then gates the address and command to the memory device 33 as in a read sequence. The memory device returns the header data via the controller's receiver 515. The controller compares the received header data with the expected value (stored in holding register 509). If the result of the comparison is correct, the normal position has been verified and the sequence continues. Then, the controller loads the defective address pointer from the memory device 33 into the holding register file 509 and loads the substitute data into the defective data substitute file 527.

Next, the controller starts fetching write data from a system memory (not shown). The controller performs this by accessing the system bus, outputs a memory or bus address, and performs a read cycle. The controller pulls data into the FIFO 601 via the input input interface 603. The controller then shifts the address of the starting sector (address of the lowest byte) from the address generator 503 to the selected memory device 33. This is followed by data from the FIFO 601. These data are stored in multiplexers 605 and 513.
And is converted to a serial format before being sent to the memory device 33. This sequence continues until all bytes for the write cycle have been loaded into the selected memory.

A pipeline structure is employed to provide effective and effective processing power when data is gated from FIFO 601 and gated to selected memory 33. The data is gated from FIFO 601 and sent to ECC hardware 527, where the remaining values will be calculated in the ECC. In the next stage, the data is transferred to the multiplexers 605 and 51.
3 when sent to the memory device via
1 compares that address from address generator 503 with the address of the defect pointer in holding register file 509. When a match occurs, it indicates that the defective location is about to be written, and the controller stores this bit in the defective data replacement file 517. All error bits sent to memory at the same time will be sent as zeros.

After the write cycle bytes have been loaded into the selected memory device, the controller issues a program command to the memory device to begin the write cycle. An ideal structure for a write operation for a flash EEprom device is the above-cited co-pending U.S. patent application Ser.
rom read and write circuits and techniques are shown in what is referred to as such, and the relevant portions are hereby incorporated by reference. Briefly, during a write cycle, the controller is supplying program (or write) voltage pulses. This is followed by a verify read to determine if programming of all bits is appropriate. If that bit is not verified, the controller repeats the program / verify cycle until all bits are correctly programmed.

If the verify fails even after one bit extends the program / verify cycle, the controller will designate the bit as a defective bit and update the defect map accordingly. The update is performed dynamically as soon as a defective cell is detected. A similar operation is employed in the case where the erase verify fails.

After all bits have been programmed and verified, the controller loads the next data bit from FIFO 601 and addresses the next location in the address sector. The controller then performs another program / verify sequence on the next byte. This sequence is continuously performed until the last data of the sector. Once this occurs, the shadow memory (header area) associated with the sector (see FIG. 5) is addressed, and the contents of the ECC register are written to this area.

In addition, the set of bits flagged as defective and stored in the defective data replacement file 516 are written to the replacement defective data location (see FIG. 5), and are thereby used for subsequent readings. Keep a good bit worth. Once these data groups have been written and verified, writing to that sector is considered complete.

The present invention has provisions for mapping defects for the entire sector, but only after a defect exists that exceeds the defect sector mapping capability of that particular sector. The count is stored as the number of defective cells in each sector. When the number in a sector exceeds a certain amount, the controller maps that sector to the other sector as defective. The defect pointer of the relevant sector will be stored in the defective sector map. A sector defect map is provided in the first defective sector when the extra area is free of defects,
It is provided in that sector. However, when a large number of defects occur in the data area of the sector, there is a strong possibility that the number of defects also increases in the blank area at the same time.

For such a reason, in another embodiment, it is preferable to locate the sector map in another memory held by the controller. The memory is either the controller hardware or the flash EEpr
om will be located away from memory. When a controller is given a multi-region address in an access, the controller compares this address to a sector defect map. If a match occurs, access to the defective sector is denied, and an alternative address present in the defect map is entered, and the corresponding alternative sector is accessed instead.

In yet another embodiment, the remapping of the sectors is performed by a microprocessor. The microprocessor looks at the incoming address and the address and compares it with the sector defect map. If there is a match, it substitutes another location as a new command instead of issuing a command to the controller.

Apart from the faster speed of solid disks, a further advantage is that there are no mechanical parts. There is no long search time due to the rotational nature inherent in disk drive. In addition to this, no long synchronization time, synchronization mark detection time, write gap, etc. are required. Thus, less overhead time is required to access the location where the data to be read exists or where it should be written. Their simplicity and reasonableness manifest themselves as faster systems with less overhead. In addition, the files are arranged in memory in any desired address order, and the controller only needs to know how to get the required data.

[0065] Yet another feature of the invention is that the defect mapping is configured in such a way that it is not necessary to obstruct the flow of data being moved into or out of the sector. The data containing the error in the block is returned regardless, and it is corrected later. By storing the addresses sequentially, one would be able to obtain a high fast speed by itself. Furthermore, it allows the realization of an effective pipeline structure in the read / write data path of the device.

(Write Cache System) A cache memory is generally used to speed up the performance of a slow access device system. For example, accessing data from a disk storage device in a computer system is slow. And if the data is faster Ram R
If obtained from the AM, the speed will be faster. Typically, a portion of the RAM system uses a cache to temporarily hold the most recently accessed from disk. The next time that data is needed, it can be obtained from a faster cache instead of a slower disk. The system works well in situations where the same data is used repeatedly. This is found in most configurations and programs, because computers tend to work only in very small storage areas when running programs. Another example of caching is to utilize a faster SRAM cache to speed up access to less expensive but slower DRAM.

Most conventional cache designs are read caches to speed up reading from memory. In some situations, a write cache is used to speed up writing to memory. However, in the case of writes to system memory (eg, disk), data is written directly each time they occur, whereas the cache is written simultaneously. This is updated when power is lost, and this is done due to concerns that files will be lost. If the write data is stored only in the cache memory (volatile), the loss of power means that the newly updated data is stored in the system memory (non-volatile).
Before the old data in the file is updated, the updated file disappears from the cache memory. When these files continue to be used, the system will operate on old data. The need to write main memory every time would break the cache mechanism for writing. In a read cache, there is no such concern, since data that would be lost from the cache is backed up on disk.

In the present invention, the flash EEpro
The system m is used in place of a conventional system having a disk-type storage device. However, the flash EEprom is subject to wear due to excessive program (erase cycles). US patent application Ser. No. 204,175, entitled "Multi-State EE"
Even in the improved flash EEprom memory device disclosed in the application filed concurrently with the present invention by Sanjay Mehalopola and Dr. Eliyahou Harari, the endurance limit is almost 10 ^6. Program / erase cycle. If the life of this device is extended to 10 years, erasure is limited to once every 5 minutes.
This is a limit in normal computer use.

To solve this problem, cache memory systems are used in a novel way so that they can be decoupled from surviving numerous program / erase cycles. The primary function of the cache is used to write to flash EEprom memory,
Flash EEpr unlike traditional cache usage
It is not used for reading from the om memory. Flash EEp
Instead of writing to rom memory, each time the data is updated, the data will be operated several times in the cache before being sent to flash EEprom memory. Thus, the number of times of writing to the flash EEprom memory can be reduced. Still further, by writing primarily into the faster cache memory, the advantage is obtained that the number of writes to the slower flash EEprom can be reduced and write efficiency in the overall system can be increased.

In realizing the present invention, a cache memory having a relatively small size is extremely effective. This helps to overcome the problem of data loss in volatile cache memory during power down. In such a case, maintaining the cache memory for a sufficiently long time with a sufficient power supply and packing the data in a nonvolatile memory which is a special reserved space in the flash EEprom memory. Can also. In the event of power loss or power failure in this system,
The write cache system is decoupled from the entire system, and the prepared rechargeable power supply is only used for powering the cache system and the space provided in the flash EEprom memory.

FIG. 8 schematically shows a cache system 701 forming part of the controller of the device according to the invention. One side of the cache system 701 is connected to the flash EEprom memory array 33. On one side, it is connected via a host interface 703 to a microprocessor system (not shown). This cache system 708 is 2
Has two memories. One is a cache memory 705 for temporarily storing a write data file. The other is a tag memory 709 for storing information related to the data file held in the cache memory 705.
It is. The memory timing / control circuit 713 controls writing of a data file from the cache memory 705 to the flash EEprom memory 33. The memory control circuit 713 causes the power supply of the microprocessor system to respond to the power detection input 715 connected via the host interface 703 and line 717 as well as the information stored in the tag memory.
The degradation of the microprocessor system power is detected by the memory control circuit 713, which will download all of the data files in the volatile cache memory 705 to the non-volatile flash EEprom memory 33.

In the present invention, the flash EEprom
The memory array 33 is organized into sectors (typically 512 bytes in size), and all memory cells in each sector can be erased together. Thus, each sector is considered a data file, and write operations on the memory array are performed on one or more such files.

During the reading of a new sector in the flash EEprom memory 33, the data file is read and sent directly to the controller via the host. This file is not used to fill the cache memory 705 as in a normal cache system.

When the host system has completed processing the data in the file and wishes to write it back into the flash EEprom memory 33, it accesses the cache system 701 by requesting a write cycle. The controller will then accept this request and operate on that cycle.

In one embodiment of the present invention, a data file is written to cache memory 705. At the same time, the other two pieces of information relating to the data file are written to tag memory 709. The first is a file pointer that defines a file that exists in the cache memory 705. The second is a timestamp, which tells the time of the last file in the cache memory. In this way, whenever the host wants to write to the flash EEprom memory 33, the data file is the one that was originally actually stored in the cache memory 705 with the pointer and the time stamp in the tag memory 709.

According to yet another embodiment of the present invention, when there is a write from the host, the controller first determines whether the file was already in cache memory, or A check is made by looking in the tag memory 709 to see if any of the tags are attached. If it has not been tagged, it is written to flash memory 33. On the other hand, the sign and the time stamp are stored in the tag memory 70.
Written in 9. If the file already exists in cache memory or is tagged, it is updated in cache memory and not written into flash memory. With this method, only the data files that are not frequently used are written to the flash memory, while the data files that are frequently used are captured in the cache memory.

According to yet another embodiment of the present invention, when there is a write from the host, it is a data file that has been further written anywhere during a predetermined time (eg, only 5 minutes). Check to see if it is. If not, it is written to the flash memory 33.
On the other hand, the sign and the time stamp are written into the tag memory 709. If the data file was written within a predetermined time interval, it is written into cache memory 705 and not into flash memory. At the same time, the sign and the time stamp are written to the tag memory 709 as in the other embodiments.
In this method as well, only the rarely used data files are recorded in the flash memory, while the frequently used data files are captured in the cache.

In all embodiments, the cache memory 705 is used to be filled at any time. When the controller detects that it has reached a predetermined fully filled state, the controller
5 and starts saving by writing into the flash memory 33 prior to the other files.

In any of the embodiments, the cache memory 705 is always started in the filling direction. When the controller detects that it has reached a certain fulfilled state, the controller saves the files in cache memory 705 over the others by writing them into flash memory 35. Start. The tag bits, which are the file indicators for these files, are then reset. It indicates that these files have been written. This creates space for new data to enter the cache memory.

The controller is also responsible for returning the least recently used files that were moved first to the flash memory 33 to make room for new working files. To keep track of the activity level of each file, the time stamp for each file is accumulated by the controller each time it is activated, unless reset for a new activity in that file. This timing is provided by the timer 711. At every time step (count), the controller systematically accesses the data file in the cache memory and reads the last written stamp for this data file. The controller then increments this time stamp by another time step (ie, increments the count by one).

For a file's timestamp, two things happen according to the activity of the file. One possibility is that the timestamp is reset by an event that a new activity has occurred. Another possibility is that no new activity occurs for the file and that the timestamp is incremented until it is removed from the cache. In fact, the maximum limit is reached when the timestamp increases indefinitely. For example, the timestamp may be incremented by the system up to a maximum of 5 minutes of inactivity. Therefore, when a data file is written to cache memory,
The file timestamp is set to the initial value. Thereafter, unless the time stamp is reset to the initial value by another write update, the time stamp starts to increase while incrementing at each time step. For example, after 5 minutes of inactivity, the timestamp is incremented to the maximum terminal count.

In one embodiment of maintaining the count, each time a file count increment occurs,
Bits may be shifted to certain locations in the shift register. If the file is updated (a new activity has occurred), the bit position will be set to the original position of the shift register. On the other hand, when the file is inactive, in some cases the bits will gradually shift towards the final shift position. The count value of each file is stored for each time step, and is then incremented. After each increment, the count value is compared to a master counter, the difference being the time delay in question.

Thus, if the file is active, the added time stamp is reset back to the original value each time the data file is rewritten. In this way, a file that is constantly being updated will have a low stamp indicator and will be stored in cache memory until its activity is reduced. After the period of inactivity has elapsed, they get the largest timestamp indicator. Unused files are gradually stored in flash memory, freeing up space in cache memory for new, more used files. Even in the tag memory, space is opened as these inactive files are moved to the flash memory.

At any time, space needs to be made available for a new data file to enter cache memory, and the controller removes some old files and stores them in flash memory 33. Scheduling is performed by a memory timing / control circuit 713 in the controller. The decision to save a file is based on various areas. The controller keeps track of the frequency of writes in the system and sees how full the cache is. If there are empty rooms, spaces, and vacancies in the cache, there is no need to save them. If more room is required, the file with the fastest timestamp is moved first and stored in flash memory.

Although the invention has been described with reference to hardware components in the controller, it should be understood that other configurations are possible. For example, the cache memory may reside anywhere in the system or may be implemented by software used in existing microprocessor systems. Such variations are within the scope of the present invention.

The profile of how many times data has been written back to the flash memory is determined based on various factors. It depends on the size of the cache memory and the frequency of writes occurring in the system. In the case of a small cache memory system, only the most frequent files will be cached.
Files that are accessed less frequently will be cached in connection with increasing the size of the cache memory. In the present invention, that is, when a relatively cheap and small amount of cache memory is used, it is preferable to use a cache memory of about 1 megabyte. By avoiding constantly writing to the most frequently used files (eg the top 5%), Flash EEp
The write frequency of rom could be reduced from every millisecond to about 5 minutes per second. This allows
Memory exhaustion time can be extended to be almost permanent. This improvement manifests itself in improving the operating efficiency of the system during write time.

The realization of a time tag in the concept of a write cache has the advantage of making the write cache buffer memory relatively small. It is often used to store data files to be written, while other files are flash EEprom
It is written directly to memory. The second feature is that the management of a moving data file upon entry and exit of the write cache buffer does not require advanced knowledge of which data file will be called next, so that it can be automated.

The various aspects of the present invention described above relate to a flash EEprom memory array system in which flash EEprom memory can replace conventional non-volatile mass storage devices.

While the embodiments of the various aspects of the invention described above are suitable, those skilled in the art will appreciate that variations thereof are also possible. Accordingly, the invention is to be protected within the full scope of the appended claims.

[Brief description of the drawings]

FIG. 1A is a block diagram of a microprocessor system including a flash EEprom memory system according to the present invention.

FIG. 1B is a block diagram illustrating a system including a number of flash EEprom memory chips and a controller chip.

FIG. 2 is a schematic diagram of a flash EEprom chip system including memory sectors selected to be erased.

FIG. 3A is a block diagram showing a circuit of a controller for implementing selective erasure of a large number of sectors according to the present invention.

FIG. 3B is a circuit diagram showing details of an exemplary register used to select one sector for erasure shown in FIG. 2A.

FIG. 4 is a flowchart illustrating an erase sequence of a plurality of sector erase selections.

FIG. 5 is a schematic diagram showing that one flash EEprom sector is divided into a data area and a spare redundant area.

FIG. 6 is a block diagram illustrating a data path during a read operation using defect mapping according to the present invention.

FIG. 7 is a block diagram illustrating a data control path at the time of writing using defect mapping according to the present invention.

FIG. 8 is a block diagram illustrating a write cache circuit in the controller.

[Explanation of symbols]

 21 Microprocessor 23 System Bus 25 RAM 27 I / O Device 29 Bulk Memory 31 Memory Controller 33 EEprom Array (Memory) 35, 37 Serial Data Line 39 Data Bus 40 Interface Circuit 41 System Control Line 43, 45, 47 EEprom Chip 49, 51, 53 Chip select (enable) 57 Logic and register circuit 59 Bus 201, 203, 205 EEprom chip 209 Line 211, 213 Sector 221, 223 Register 225 Command register 227 Serial interface 229 Command decoder 231 Address register 233 Address decoder 503 Memory address Generator 505 port (μp interface) 507 DMA controller 509 Hold Grayed register file 511 the command sequencer 513 multiplexer 515 receiver 517 defective data replacement file 519 FIFO 521 comparator 523 multiplexer 525 output interface 527 ECC hardware 601 FIFO 603 interface 605 multiplexer

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Robert Dee. Norman United States, 95120, San Jose, California, Pebblewood Court 6656 (72) Inventor Sanjay Melotra United States, 95035, California, Milpitas, Berkshire Place 735

Claims (29)

[Claims] 1. A method of operating a computer system including a processor and a memory system, wherein the memory system includes an array of non-volatile floating gate memory cells divided into a plurality of sectors, each of the sectors being Providing at least one user data part and at least one overhead part of a memory cell in an individual sector in a method of operating a computer system comprising a distinct group of said memory cell array which can be erased simultaneously as one unit And receiving an address of a format designating at least one magnetic disk sector from the processor, and designating an address of at least one nonvolatile memory sector corresponding to the at least one magnetic disk sector accordingly. Writing user data to or reading user data from a user data portion of the at least one non-volatile memory sector; and Writing overhead data relating to any of the data stored in the user data section of the at least one nonvolatile memory sector to the overhead section of the at least one nonvolatile memory sector, or Operating the computer system, comprising: 2. The method of claim 1, further comprising: detecting a predefined condition when an individual sector becomes unusable; and linking an address of the unusable sector with an address of another available sector. Claim 1 consisting of
Operating method of the computer system described. 3. The method of claim 2, wherein detecting the predefined condition comprises detecting when an individual sector becomes defective. 4. The method of claim 3, wherein detecting when an individual sector becomes defective includes determining when the number of individual defective memory cells in the sector exceeds a predetermined number. How to operate a computer system. 5. The method of claim 1, wherein the user data portion of each non-volatile memory sector has a capacity of substantially 512 bytes. 6. The method according to claim 1, wherein the information stored in the overhead section of each sector includes an address of each overhead section of each sector. 7. The method of claim 1, wherein the information stored in the overhead section of each sector includes an error correction code calculated from data stored in a user data section of a corresponding sector of each sector. Operating method of the computer system described. 8. The method of claim 1, wherein linking an address of an unavailable sector with an available sector maintains a list linking addresses of corresponding sectors of the unavailable sector and other available sectors. To do
3. The method of claim 2, wherein accessing an available sector comprises referencing the list to change an address of an unavailable sector to an address of an available sector. 9. The method of claim 1, wherein linking the address of the unusable sector comprises storing an address of a corresponding available sector in each of the defective sectors and corresponding to the unusable sector. 3. The method of claim 2, wherein accessing the available sector comprises referencing an available sector address stored in the unavailable sector. 10. The method of claim 1, wherein causing the controller to generate an address of a non-volatile memory sector comprises:
Performing such for a non-volatile memory sector corresponding to only one magnetic disk sector, wherein the user data portion of each non-volatile memory sector is substantially the same as the user data portion of said one magnetic disk sector. 3. The method of operating a computer system according to claim 2, having the same capacity. 11. The method of claim 1, wherein dividing the memory cells comprises dividing the memory cells in individual sectors to further include a spare memory cell section. . 12. The method, wherein the overhead data stored in the overhead portion of an individual sector comprises identifying any defective cells in user data of a corresponding sector of the sector, the method further comprising: The controller has at least one of said addressed
12. The computer of claim 11, further comprising: reading the identification of a defective cell from an overhead portion of one of the non-volatile memory sectors, and subsequently replacing the defective cell with another cell in a spare cell portion of at least one of the addressed non-volatile memory sectors. How to operate the system. 13. The method according to claim 1, wherein each sector is one.
2. The method according to claim 1, comprising only one user data portion and only one overhead data portion. 14. The method of claim 1, further comprising providing a memory controller connectable to said processor for controlling operation of an array.
Operating method of the computer system described. 15. The method of claim 1, wherein the memory system is provided in a card removably connected to the computer system. 16. The method of claim 14, wherein the memory controller is provided in a card removably connected to the computer system. 17. The method of claim 1, wherein the memory controller and the memory system are provided in a card that is removably connected to the computer system.
5. The operation method of the computer system according to 4. 18. A memory system having electrical terminals for connection to a host computer system, wherein the memory system is an array of non-volatile floating gate memory cells divided into a plurality of sectors, wherein each of the sectors is A well-defined group of said memory cells, which can be erased simultaneously as one unit, wherein each sector has enough cells to store a certain amount of user data and some overhead data An array of non-volatile floating gate memory cells and a memory controller connected between the electrical terminals and the memory cells for controlling the operation of the array, wherein the controller addresses one or more non-volatile memory sectors One or more through the electrical terminals Responsive to receipt of the address of the large memory storage block of claim 1, wherein said addressing means includes means for responding to the identification of any non-volatile memory sector that is unavailable for replacement with another available sector. Responsive means; means for reading overhead data stored in the addressed sector; reading user data from the addressed sector;
Or means responsive to the overhead data read for either writing user data to said sector. 19. In the memory system, ascertaining any unusable sectors comprises creating a list maintained in a memory system unit that links the addresses of the unusable sectors and the corresponding available sectors. 20. The memory system of claim 18, including: 20. In the memory system, ascertaining any unusable sectors comprises assigning an individual address of an alternate available sector stored in each sector of the unusable sectors as part of overhead data. 20. The memory system of claim 18, including storing. 21. In the memory system, identifying any unusable sectors includes identifying inoperable or defective sectors.
21. The memory system according to any one of 20. 22. In the memory system, confirming any unusable sectors includes confirming a sector having a plurality of defective cells exceeding a preset number. Memory system. 23. The memory system according to claim 18, wherein in the memory system, the predetermined amount of user data is substantially equal to 512 bytes. 24. In the memory system, the controller further includes means for selecting a plurality of sectors for an erasing operation, and means for performing an erasing operation on only the selected plurality of sectors at the same time. The memory system according to claim 1. 25. In the memory system, each of the non-volatile memory sectors further includes a redundant memory cell exceeding a required number of cells for storing the predetermined amount of user data and the overhead data. 19. The memory system of claim 18, wherein said controller further comprises means for replacing defective memory cells in individual sectors with redundant memory cells in individual sectors. 26. In the memory system, the overhead data reading means includes means for reading an address of the addressed sector from the overhead data of the addressed sector, and the controller stores the address of the read overhead data as an address of the sector. 19. The memory system of claim 18, further comprising means for comparing to confirm that a desired sector has been addressed. 27. In the memory system, the predetermined amount of user data storable in individual sectors is substantially equal to the size of individual mass memory storage blocks of the host computer system, and the addressing means. 27. The memory system according to any one of claims 18 to 20, 25 and 26, wherein the addresses map addresses of individual blocks of the mass memory storage block to unique individual sectors of the non-volatile memory sector. 28. In the memory system, the memory system unit executes on a single printed circuit card.
The memory system according to claim 1. 29. In the memory system, the address of one or more mass memory storage blocks to which the addressing means of the controller responds comprises the address of one or more magnetic disk sectors. 27. The memory system according to claim 26.