JPH11338783A - Microcomputer system and optical equipment provided with the system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the malfunction of a microcomputer to be operated based on a program or data stored in a non-volatile memory when any abnormality occurs in this non-volatile memory where the program or data are stored. SOLUTION: This system has a first microcomputer 101, non-volatile memory storing the program or data for the first microcomputer 101 and second microcomputer 102 capable of detecting abnormality in a non-volatile memory 128 by communicating with the first microcomputer 101 and when abnormality is detected in the non-volatile memory 128, the second microcomputer 102 inhibits the operation of the first microcomputer 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device having a nonvolatile memory and an optical apparatus having the microcomputer device having a nonvolatile memory.

[0002]

2. Description of the Related Art A microcomputer is a read only memory (ROM) or a read only memory (ROM).
The processing is executed in accordance with a program or data stored in advance in a storage unit called AM (random access memory; hereinafter, referred to as “RAM”).

A program for a so-called embedded device such as a camera is often stored in a mask ROM (mask-version read-only memory; hereinafter, referred to as "mask ROM").

[0004] A mask ROM is a memory in which information is recorded using wiring in a semiconductor manufacturing process. Data once written cannot be rewritten after a chip is manufactured. Are used as storage means for information that does not require rewriting due to the nature of data.

[0005] On the other hand, EPROM (Electrically Writable ROM) is a ROM, but is a rewritable storage means.
And non-volatile memory such as EEPROM (electrically erasable and erasable ROM) and even EEPROM, but a type of erasing that can be performed collectively, are used in place of the mask ROM of the microcomputer for embedded devices. It has come to be.

[0006] Flash EEPROM is a type of EEPROM.
In particular, it refers to an EEPROM that can be erased not in units of bits or bytes but in blocks of some extent.

[0007] Since it is more cost-effective than a normal EEPROM, it is often used as a large-capacity storage means for storing a program.

When the nonvolatile memory is used as the ROM for storing the program, the contents of the program can be rewritten even after the chip is manufactured, so that the number of steps for writing the program code can be reduced, and the program can be easily changed after the product is completed. There are advantages such as.

[0009]

However, since nonvolatile memories are based on the principle of storing (recording) data by retaining charges in a floating gate in a semiconductor, they are compared with mask ROMs that record in the form of wiring. Generally, the performance of data retention is inferior.

Therefore, in such a non-volatile memory, there is no possibility that data abnormalities (such as garbled storage) will occur, and when a data abnormality actually occurs, a microcomputer which executes processing in accordance with a program of the memory will be used. Operation is no longer guaranteed.

[0011]

According to a first aspect of the present invention, there is provided a first microcomputer, a nonvolatile memory storing a program or data for the first microcomputer, A second microcomputer that communicates with a microcomputer of the second type and can detect an abnormality of the nonvolatile memory;
Is characterized in that the operation of the first microcomputer is prohibited when the abnormality of the nonvolatile memory is detected.

According to an eighth aspect of the present invention, in a microcomputer device in which a first microcomputer and a second microcomputer communicate with each other, a first program or data for the first microcomputer is stored. A non-volatile memory, a second non-volatile memory in which a program or data for a second microcomputer is stored, a first detecting means for detecting an abnormality of the first non-volatile memory, Second detecting means for detecting an abnormality of the non-volatile memory, and when the second detecting means detects the abnormality, the first microcomputer inhibits the operation of the second microcomputer. When the first detecting means detects an abnormality, the second microcomputer operates the first microcomputer. It is characterized in that to prohibit.

[0013]

(First Embodiment) FIG. 1 is a block diagram illustrating the configuration of a camera (optical apparatus) according to a first embodiment of the present invention.

In this embodiment, the camera is controlled by a microcomputer device comprising two microcomputers, a main microcomputer 101 and a sub-microcomputer 102.

The main microcomputer 101 is a CPU (central processing unit).
(Hereinafter referred to as “CPU”) 124, RAM 125, EEPROM 126, and mask ROM 127.

The EEPROM 126 is used for storing adjustment data of the camera.
Although it is designed to be built-in to 1, the EEPROM single chip may be externally connected using a serial bus.

The sub-microcomputer 102 comprises a CPU 121, a RAM 122, and a flash EEPROM 123. Therefore,
The program of the sub microcomputer 102 is stored in the nonvolatile memory.

The main microcomputer 101 and the sub-microcomputer 102 are connected by a serial bus 305 and exchange commands and data with each other to control the camera.

Normally, a serial bus is often composed of three lines of a clock signal, input, and output.

A signal 307 is a reset signal for the sub-microcomputer 102, which can be controlled by the main microcomputer 101.
The logic of this signal is reset at a low potential level (hereinafter abbreviated as “L level”), and is reset at a high potential level (hereinafter, “L level”).
The reset is released by "H level".

Reference numeral 103 denotes a lens communication circuit, and a serial bus 304
Connected to the main microcomputer 101, and further connected to the lens microcomputer 200 inside the taking lens 2 outside the camera body and the serial bus.
Connected at 302. The camera body 1 performs serial communication via the lens communication circuit 103 to instruct the photographing lens 2 to drive the distance ring or the aperture or to input various lens information from the photographing lens 2.

Reference numeral 104 denotes a PC (personal computer; hereinafter abbreviated as "PC") communication circuit, and serial buses 301 and 303.
, The camera body 1 can communicate with the external computer 3.

Using this communication path, the external computer 3 can instruct the main microcomputer 101 in the camera to rewrite the flash EEPROM of the sub microcomputer 102.

The LCD display circuit 111 is connected to the main microcomputer 101 via a signal line 306, and according to an instruction from the main microcomputer 101, various setting values and control values of the camera are displayed on the LCD on the upper part of the camera.
This is a circuit to display on the display or LCD display in the viewfinder.

The photometric sensor 309 and the light control sensor 310 output analog signals 309 and 310 corresponding to the amount of incident light, respectively, and the main microcomputer 101 receives the signals at the A / D input terminal and performs A / D conversion. Used for exposure control.

Reference numeral 108 denotes a shutter drive circuit, which drives a shutter (not shown) according to an instruction from the main microcomputer via a signal line 311.

Reference numeral 109 denotes a motor drive circuit, which is a signal line 312 which is controlled by a main microcomputer to issue an instruction from the film feeding motor 110.
Is driven.

As described above, the main microcomputer 101 controls most of the basic functions of the camera. Since these specific camera functions are not directly related to the present invention, further description will be omitted.

In the camera of this embodiment, the sub microcomputer 10
Reference numeral 2 denotes a microcomputer dedicated to focus detection processing.
The main microcomputer 101 is in charge of control that does not require much speed, and the sub-microcomputer 102 executes the focus detection processing at high speed in parallel with the operation of the main microcomputer 101.

Therefore, the sensor output signal 308 of the focus detection sensor 105 is input to the A / D input of the sub-microcomputer 102, and the sub-microcomputer 102 A / D converts the signal, and based on the data, the photographing lens 2 At high speed.

By sharing the control of the camera by the two microcomputers in this manner, a high-speed focus adjustment operation can be performed.

The ROM section of the sub-microcomputer 102 is composed of the flash EEPROM 123 as described above, and the program can be changed in a short time after the completion of the camera in accordance with the improvement of the focus detection processing or the change of the specification. .

Although the flash EEPROM memory has such an advantage, as described above, the flash EEPROM memory is more uneasy in the retention characteristics of the stored data as compared with the mask ROM memory.

In order to cope with this, in the present embodiment, the main microcomputer 101 of the mask ROM checks the data stored in the flash EEPROM of the sub-microcomputer 102, and if there is an abnormality, stops the operation of the sub-microcomputer 102 and further issues a warning. Is displayed to draw the user's attention.

The operations of the main microcomputer 101 and the sub microcomputer 102 according to the first embodiment will be described with reference to the flowcharts shown in FIGS.

When the release button of the camera is pressed, power is supplied to the main microcomputer 101 by a power supply control circuit (not shown), and the main microcomputer 101 executes step S10 according to a program stored in the built-in mask ROM 127 in advance.
0].

As described above, since the ROM of the main microcomputer 101 is a mask version, its storage program is written by wiring during semiconductor manufacturing.

In the next step [S101], the main microcomputer 101 resets the reset signal 30 which has been "L level" until then.
7 is set to “H level”, and the reset of the sub microcomputer 102 is released.

The sub-microcomputer 102 releases the reset
According to the program stored in the built-in flash EEPROM 123, the operation after step [S200] in FIG. 4 is started.

In the next step [S201] of FIG. 4, the sub-microcomputer 102 calculates its own "checksum" of the flash EEPROM 123.

The "checksum" is a final addition result obtained by adding data contents in a predetermined memory space in units of bytes or words and ignoring overflow, and is often used for data verification of a memory. It is a technique that is used.

If the "initial checksum value" calculated at the time of storing the data does not match the "latest checksum value" calculated at a later time, it is known that an error has occurred in the current stored data.

The sub-microcomputer 102 transmits the “latest checksum value” calculated in step [S202] to the main microcomputer 101 via the serial bus 305.

The main microcomputer 101 proceeds to step [S10
After the reset of the sub-microcomputer 102 is released in [1], reception of the checksum from the sub-microcomputer 102 is waited in steps [S102] and [S103].

When the "latest checksum value" is sent from the sub-microcomputer 102, the process proceeds to step [S104], where the "initial checksum value" which is the correct checksum value of the sub-microcomputer 102 stored in advance is used. Compare.

The "initial checksum value" may be stored in the EEPROM 127 in the main microcomputer 101, or may be stored in the flash EEPROM of the sub-microcomputer 102, and may be stored together with the "latest checksum value". You may have it sent.

Although the "initial checksum value" itself may cause a data error, the possibility of a data error is low in the first place.
And the "initial checksum value" that caused the data error happens to coincide with the probability that the data length of the checksum value is 1/256 if the data length is 8 bits and 1/65536 if the data length is 16 bits. If you prepare 16 bits or more, you can feel safe.

If it is determined in step [S104] of the main microcomputer 101 that the "initial checksum value" matches the "latest checksum value", the process proceeds to step [S105], where the sub-microcomputer 102 is determined in advance. The operation of the sub-microcomputer 102 is permitted by transmitting the “operation permission code”, and the flow proceeds to the flow of “camera operation of main microcomputer” after step [S106].

When the "operation permission code" is transmitted from the main microcomputer 101, the sub-microcomputer 102 which has been waiting for it in steps [S203] and [S204] is also changed to the "camera operation of the sub-microcomputer" after step [S205]. Move on to flow execution.

What has been described above is the sub-microcomputer 10
This is the operation when it is confirmed that the data of the flash EEPROM of No. 2 is normal (no data error has occurred), from which the original camera operation is executed.

On the other hand, if the two checksum values do not match in step [S104], the main microcomputer 101 may not operate normally due to a data error in the program.
At 7], the sub-microcomputer 102 is reset by setting the reset signal 307 to “L level”, and the operation is stopped.

Then, in the next step [S108], a warning is displayed on the display unit of the camera using the LCD display circuit, and in step [S109], the subsequent camera operation is terminated.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a camera (optical device) according to the embodiment.

Portions common to the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

The difference from the first embodiment is that the ROM of the main microcomputer 101 is replaced with a flash EEPROM 128 like the sub microcomputer 102. In addition, since the adjustment parameters of the camera may be stored in the flash EEPROM 128, the EEPROM 126 of FIG. 1 is deleted in FIG.

The second embodiment is an embodiment in which both memories for storing programs of two microcomputers are constituted by flash EEPROMs.

In this embodiment, the flash EEPROMs of the other microcomputers are checked with each other, and if a data error occurs in the partner flash EEPROM,
In this configuration, the normal microcomputer inhibits the operation of the abnormal microcomputer.

In FIG. 2, in addition to the reset signal 307 for the sub-microcomputer 102 shown in FIG.
A control line 314 is connected to the LCD display so that the sub-microcomputer 102 can warn of an abnormality of the main microcomputer 101 by adding a reset signal 313 for the main microcomputer so that the main microcomputer 101 can reset the main microcomputer 101. Is also connected.

FIGS. 5 and 6 are flowcharts for explaining the operation of the main microcomputer 101 and the sub-microcomputer 102 of this embodiment.

As in the first embodiment, when the release button of the camera is pressed, power is supplied to the main microcomputer 101 by a power supply control circuit (not shown), and the main microcomputer 101 is stored in a built-in flash EEPROM 128 in advance. The operation from step [S300] is started according to the program.

In this embodiment, the program code is stored in the flash EEPROM of the main microcomputer 101 as in the case of the sub-microcomputer 102.

In the next step [S301], the main microcomputer 101 resets the reset signal 30 which has been "L level" until then.
7 is set to “H level”, and the reset of the sub microcomputer 102 is released.

The main microcomputer 101 proceeds to the next step [S30
In [2], the “latest checksum M” of the flash EEPROM 128 is calculated, and in [S303], it is transmitted to the sub-microcomputer 102 via the serial bus 305.

On the other hand, the sub-microcomputer 102 starts the operation after step [S400] in FIG. 6 according to the program stored in the built-in flash EEPROM 123 by releasing the reset similarly to the flowchart in FIG.

The sub-microcomputer 102 also performs the next step [S401].
Calculates the "latest checksum S" of the flash EEPROM 123, and transmits it to the main microcomputer 101 in [S402].

As described above, both the main microcomputer 101 and the sub-microcomputer 102 calculate the latest checksum of their own flash EEPROMs and transmit the checksums to each other, and the main microcomputer 101 executes the sub-microcomputer in steps [S304] and [S305]. Microcomputer 1
02 waits for the latest checksum of the other party in steps [S403] and [S404].

[Latest checksum S] of the sub microcomputer 102
Is received, the main microcomputer 101 compares the "initial checksum S" with the "latest checksum S" in step [S306].
The subroutine 102 then proceeds to
The operation permission code is transmitted to permit the operation of the sub-microcomputer 102.

Further, in steps [S308] and [S309], an "M operation permission code" for permitting the operation to the main microcomputer itself, which is transmitted from the sub-microcomputer 102, is waited for, and transmitted. When it comes, step [S310]
Then, the flow after “the camera operation of the main microcomputer” is executed.

On the other hand, in step [S306], the sub-microcomputer 10
If the two checksum values do not match, the sub microcomputer 102
May not work properly.
1 is the reset signal 307 at "L level" in step [S311]
To reset the sub-microcomputer 102 and stop its operation.

Then, in the next step [S312], a warning is displayed on the display unit of the camera using the LCD display circuit, and in step [S313], the operation of the camera in charge of the main microcomputer 101 is terminated.

The steps after step S403 in FIG. 6 showing the operation of the sub-microcomputer 102 are exactly the same as those after step S305 in the main microcomputer 101 in FIG. Since the operation is being performed, a detailed description is omitted. However, if the data in the flash EEPROMs in the two microcomputers are both normal, the camera operation is performed. If either one of the data is abnormal, the camera operates abnormally. The operation of the microcomputer using the flash EEPROM is prohibited, and an operation is further performed to display a warning.

(Other Embodiments) In the embodiment described above, the flash EEPROM is checked when the power is turned on. However, the flash EEPROM is checked at another timing, for example, every time the release button is pressed, or periodically (for example, every one minute). ) Can be executed at all.

The flash EE is used as a nonvolatile memory.
Although the description has been made with reference to the example of the PROM, the present invention employs ordinary EPROM, EROM, and the like.
Obviously, it is applicable to EPROM.

Further, in the above-described embodiment, when an abnormality occurs in the flash EEPROM, the operation is stopped and a warning is displayed. However, since the sub-microcomputer 102 is dedicated to focus detection, the related focus detection operation is performed. Only the basic function of the camera which is handled by the main microcomputer may be configured to operate at a minimum. If the role of the sub-microcomputer 102 is another function, only that function can be stopped.

Although the flash EEPROM has been described as a built-in memory, it is obvious that the flash EEPROM can be attached externally.

Further, the warning is not limited to the LCD display, but may be a sound or another display.

Further, the microcomputer is not limited to the two configurations.

[0078]

As described above, according to the first aspect of the present invention, a first microcomputer, a non-volatile memory storing a program or data for the first microcomputer, and A second microcomputer that communicates with a first microcomputer and is capable of detecting an abnormality of the nonvolatile memory; wherein the second microcomputer detects the abnormality of the nonvolatile memory when the abnormality is detected in the nonvolatile memory; By prohibiting the operation of the microcomputer, it is possible to prevent a malfunction of the microcomputer device caused by the abnormality of the nonvolatile memory.

According to an eighth aspect of the present invention, in a microcomputer device in which a first microcomputer and a second microcomputer communicate with each other, a first program or data for the first microcomputer is stored. A non-volatile memory, a second non-volatile memory in which a program or data for a second microcomputer is stored, a first detecting means for detecting an abnormality of the first non-volatile memory, Second detecting means for detecting an abnormality of the non-volatile memory, and when the second detecting means detects the abnormality, the first microcomputer inhibits the operation of the second microcomputer. When the first detecting means detects an abnormality, the second microcomputer operates the first microcomputer. By prohibiting, it is possible to prevent malfunction of the microcomputer device caused by the non-volatile memory error.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a camera (optical apparatus) according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram of a camera (optical apparatus) according to a second embodiment of the present invention.

FIG. 3 is a flowchart illustrating the operation of the camera according to the first embodiment.

FIG. 4 is a flowchart illustrating the operation of the camera according to the first embodiment.

FIG. 5 is a flowchart illustrating the operation of the camera according to the second embodiment.

FIG. 6 is a flowchart illustrating the operation of the camera according to the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Camera main body 2 Shooting lens 101 Main microcomputer 102 Sub microcomputer 123 Flash EEPROM in sub microcomputer 102
M 127 Mask ROM in main microcomputer 102 305 Serial bus connecting main microcomputer 101 and sub microcomputer 102 307 Reset signal of sub microcomputer 102 313 Reset signal of main microcomputer 101

Claims (9)

[Claims] 1. A first microcomputer, a non-volatile memory storing a program or data for the first microcomputer, and an abnormality in the non-volatile memory communicating with the first microcomputer. And a second microcomputer that detects the abnormality of the nonvolatile memory and prohibits the operation of the first microcomputer when the second microcomputer detects an abnormality in the nonvolatile memory. apparatus. 2. A first microcomputer, a non-volatile memory storing a program or data for the first microcomputer, and an abnormality in the non-volatile memory communicating with the first microcomputer. And a second microcomputer that detects the abnormality of the nonvolatile memory and prohibits the operation of the first microcomputer when the second microcomputer detects an abnormality in the nonvolatile memory. Optical equipment with equipment. 3. The nonvolatile memory according to claim 1, wherein the nonvolatile memory is an EPROM (Electrically Writable ROM). 4. The non-volatile memory according to claim 1, wherein the non-volatile memory is an EEPROM (Electrically Writable / Erasable ROM). 5. The nonvolatile memory according to claim 1, wherein the nonvolatile memory is a flash EEPROM. 6. The method according to claim 1, wherein the second microcomputer, when detecting the abnormality, prohibits the operation of the first microcomputer and displays a warning. 7. The method according to claim 1, wherein an abnormality in the storage unit is detected by a checksum. 8. A microcomputer device in which a first microcomputer and a second microcomputer communicate with each other, comprising: a first nonvolatile memory storing a program or data for the first microcomputer; A second nonvolatile memory storing a program or data for the second microcomputer;
First detecting means for detecting an abnormality in the nonvolatile memory of
And second detection means for detecting an abnormality of the second nonvolatile memory, wherein when the second detection means detects an abnormality,
The first microcomputer inhibits the operation of the second microcomputer, and when the first detecting means detects an abnormality, the second microcomputer operates the first microcomputer.
A microcomputer device which prohibits the operation of the microcomputer. 9. An optical apparatus provided with a microcomputer device for communicating between a first microcomputer and a second microcomputer, wherein a first nonvolatile memory storing a program or data for the first microcomputer. A nonvolatile memory, a second nonvolatile memory storing a program or data for a second microcomputer, and a first nonvolatile memory.
First detecting means for detecting an abnormality in the nonvolatile memory of
And second detection means for detecting an abnormality of the second nonvolatile memory, wherein when the second detection means detects an abnormality,
The first microcomputer inhibits the operation of the second microcomputer, and when the first detecting means detects an abnormality, the second microcomputer operates the first microcomputer.
An optical apparatus comprising a microcomputer device, wherein operation of the microcomputer is prohibited.