JPH11331846A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a data quantity without deteriorating a reproduced picture with respect to variable length coded word data by providing a means removing specific components in coded data. SOLUTION: At the time of inputting a first discrete cosine transformation(DCT) coefficient, an inverse quantization means 103 obtains a first quantized matrix from a first quantizing matrix means 104 to execute inverse quantizing processing on the first DCT coefficient to generate inverse quantization data and outputs it to a quantizing means 105. A second quantizing matrix means 106 keeps a second quantized matrix and at the time of inputting inverse quantization data, the means 105 obtains the second quantized matrix by a second quantizing matrix means 106 to execute quantizing processing with respect to inverse quantization data to generate a second DCT coefficient. In this case, the second quantized matrix is set to make the value zero with respect to many high-pass AC components compared with the first quantized matrix.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly to a video signal processing apparatus for reducing the amount of digitized and compression-coded data.

[0002]

2. Description of the Related Art By digitizing an image, which is an analog signal, and handling it as a digital image signal, it is possible to uniformly handle digitized audio signals, character data, programs, and the like. Data processing such as processing can be easily performed.

[0003] Image data such as a digital video signal is usually an array of pixels which are discrete digital data having pixel values representing luminance and color difference, and is processed for each frame corresponding to one screen. It will be. When recording or transmitting image data for each frame by compression encoding, intra-frame encoding based on spatial correlation within one frame is performed. The compression ratio can be improved by also performing inter-frame coding based on the spatial correlation. According to the intra-frame encoding, an I-picture that can be decoded independently is obtained. However, in the case of the inter-frame encoding, a P-picture is obtained by performing prediction in the forward direction.
By performing prediction in both forward and reverse directions, a B picture is obtained.
These can improve the compression ratio by processing the difference data, but become data that cannot be decoded alone.

In a general compression encoding technique such as MPEG, a discrete cosine transform (DCT) process is performed.
DCT processing is performed on a pixel block including a fixed number of pixels, and before the processing, pixel values are randomly distributed in the pixel block. However, in DCT coefficients obtained by DCT processing, Since a large pixel value is unevenly distributed at a low frequency, the value of a high-frequency component is set to 0 by performing a quantization process as a division process on the pixel value, and furthermore, a variable length coding process based on the continuation of the same value Is performed to obtain compressed variable-length codeword data. Normally, the variable length codeword data is recorded and transmitted.

In recording such digitized and compression-encoded data on a recording medium, in addition to the conventionally used baseband recording system,
There is a transparent recording system typified by PEG2-TS. In the case of the transparent recording system, data such as variable-length codeword data transmitted as a bit stream is recorded as it is. It has the advantage that it does not need a decoder or a decoder, and that the image quality of transmitted data can be stored as it is.

One of the recording media used for recording and storing digital video signals is a digital video cassette tape. HD-DVCR (Digita
l DVB (Digita
l Video Broadcasting) The signal recording DVCR standard specifies the recording format for digital TV broadcast signals processed in accordance with MPEG.
Among them, a standard for recording special reproduction data is also included as an option. Hereinafter, recording of high-speed reproduction data in this standard will be described.

Here, it is assumed that two types of high-speed reproduction data having different search speeds are recorded. When recording on a tape recording medium, a signal is recorded on a portion called a track. High-speed reproduction data can be searched at high speed by being repeatedly recorded on a plurality of tracks. Therefore, the maximum search speed is determined by the number of recorded repetitions. In this case, the T which can be read at a maximum of 18 times the search speed is used.
Two types of data, PH data and TPL data that can be read at a maximum of four times the search speed, are recorded.

FIG. 14 is a view for explaining the recording state of such data on a tape recording medium.
FIG. 3 is a diagram showing a track pattern of a DVCR in which TS data is arranged on a tape. As shown, in this track format, a unit composed of four tracks (F0, F1, F0, F2 in the figure) is repeated. When data for special reproduction (high-speed reproduction) is recorded in this format (since it is optional as described above), it should be placed at a specific position in the tape.

The data recorded on the tape is in units of a fixed amount of sync block, and the data for high-speed reproduction is specified every 5 sync blocks in a specific video data recording area shown in FIG. Recorded in position. The TPH data includes sync block numbers 40 to 44, 62 to 66, 84 to 88, and 106 to 11 of the F0 track.
5 at positions 0, 128-132, and 150-154
It is recorded in a total of 30 sync blocks of 6 sync blocks. Further, the TPL data is recorded in the sync block numbers 131 to 155 of the F1 track in 25 sync blocks.

As described above, the recording of special reproduction data is optional in this standard, and the identification of the data recorded at the above position is performed by using a sync block extra header assigned to each sync block. Is used. FIG. 15 is a diagram showing the state of the sync block extra header added to the high-speed playback data. The sync block extra header is a one-byte header included for each sync block, and one bit b7 shown is used for discriminating between normal reproduction data and high-speed reproduction data. In the figure, the value of b7 is 1, which is special reproduction data (high-speed reproduction data).
It is shown that it is.

Of the other bits forming the sync block extra header, one bit b6 is a bit used to determine whether or not it is new frame data, and is a frame toggle bit used as a toggle. is there. It is specified that the frame toggle must not be performed more than once in one track. b2 to b5
Are used as a counter for distinguishing the special reproduction data area. Further, b0 to b1 are reserved. As described above, in the DVCR, data for high-speed reproduction is recorded at a specific position in accordance with the option standard, and the fact that the data recorded at that position is data for special reproduction (high-speed reproduction) is identified by the header portion. Can be done.

[0012]

As described above, when handling digitized video data, DCT is used.
The compression, encoding, and recording or transmission are performed by conversion, quantization, and variable-length encoding. However, since the variable-length codeword data obtained by such processing includes a high-frequency (high-frequency) component of the DCT coefficient, the influence on the reproduction image quality is small. Even though the amount of data to be transmitted can be reduced, such a reduction in the amount of data has hardly been performed.

As a conceivable method, if variable-length codeword data, which is digital data, is once converted to analog, high-frequency components are deleted from the analog signal, and digital conversion is again performed to obtain variable-length codeword data, It is possible to appropriately remove high-frequency components and reduce the amount of data. However, in the case of such a method, the inverse of the digitization and compression encoding that generated the variable-length codeword data is performed, and further reprocessing is performed, so that the circuit scale increases, and the processing time increases. What is needed is a problem. In particular, since the circuit scale and the number of processing steps for the conversion between digital and analog have a great influence, it is not practical to reduce the amount of data by such processing.

When the digital data obtained as described above is recorded on a tape recording medium or the like, the above-mentioned transparent recording method is used when recording as data for special reproduction such as high-speed reproduction. However, there is a problem that the image quality at the time of special reproduction becomes extremely poor. This is because in the case of the transparent recording method, the above-described I, P, or B picture is recorded as it is, so that a P picture or a B picture which does not essentially assume decoding and reproduction processing alone is used. This is because when used for high-speed reproduction data, loss of information becomes enormous.

Therefore, if only the I picture is extracted and used, usable high-speed reproduction data can be obtained. However, as described above, in the recording format of the tape recording medium, the high-speed reproduction data is not used. Since the recording position is specified, in order to secure a practical update cycle, instead of recording all the I pictures,
It is desired to reduce the amount of data for recording. In this case, in order to simplify the processing procedure, several I
A method is conceivable in which one I picture is selected from the pictures and is used as high-speed reproduction data.

However, when the high-speed reproduction data is generated in this manner, when reproducing the data, a display in which motion information is lost is displayed, so that a good display result cannot be obtained. Therefore, it is desirable to reduce the amount of data for all I-pictures and to obtain high-speed reproduction data that can transmit motion information even if the image quality is slightly degraded. No method of reducing the data amount has been proposed in the video signal processing according to the above.

The present invention has been made in view of such circumstances, and provides a video signal processing apparatus capable of reducing the amount of variable-length codeword data without greatly deteriorating the reproduction image quality. The purpose is to do.

Further, the present invention provides a video signal processing apparatus capable of recording at a reduced data amount without greatly deteriorating the reproduced image quality when recording data for high-speed reproduction on a tape recording medium or the like. The purpose is to provide.

[0019]

In order to achieve the above object, a video signal processing apparatus according to a first aspect of the present invention provides a video signal processing apparatus for processing encoded data obtained by compressing and encoding a digitized video signal. A signal processing apparatus comprising a specific component removing unit for removing a specific component in the encoded data.

The video signal processing apparatus according to a second aspect is the video signal processing apparatus according to the first aspect, wherein the coded data to be processed is variable-length coded, and the specific component removing means includes: The high-frequency component contained in the variable-length coded data is removed as the specific component.

According to a third aspect of the present invention, in the video signal processing apparatus according to the second aspect, the specific component removing unit performs a variable length decoding process on the variable length encoded data. A long decoding means, an inverse quantization means for performing an inverse quantization process on the processing result of the variable length decoding means using a first quantization matrix, and a processing result of the inverse quantization means. And a variable length encoding unit that performs a variable length encoding process on a processing result of the quantization unit, the quantization unit performing a quantization process using a second quantization matrix. is there.

According to a fourth aspect of the present invention, in the video signal processing apparatus according to the second aspect, the specific component removing means performs variable length decoding on the variable length coded data. Long decoding means, decoding result processing means for performing a process of changing the value of a specific part constituting the processing result with respect to the processing result in the variable length decoding means, and decoding result processing means And a variable-length encoding means for performing a variable-length encoding process on the processing result in.

According to a fifth aspect of the present invention, in the video signal processing apparatus according to the second aspect of the present invention, the specific component elimination means is configured to remove the variable length encoded data from the variable length encoded data. A code characteristic detecting means for detecting the characteristic of the variable-length code, and removing a specific code included in the variable-length-coded data based on the characteristic of the variable-length code detected by the code characteristic detecting means. Specific code removing means.

According to a sixth aspect of the present invention, in the video signal processing apparatus according to the fifth aspect, the specific component removing means reads the code length of a variable length code constituting the variable length coded data. Length reading process, code length sum calculation process of accumulating code lengths read in the variable length code length reading process to obtain a code length sum,
A variable length code that compares the total code length obtained in the above code length total calculation process with a preset threshold value and outputs a variable length code having a code length not exceeding the threshold value according to the result of the comparison. The specific variable length code is removed by performing a long code output process.

According to a seventh aspect of the present invention, in the video signal processing apparatus according to the fifth aspect, the specific component removing unit determines the number of unit data included in the variable length code constituting the variable length coded data. The number acquisition process to be acquired, the unit data number total calculation process of cumulatively adding the number of unit data acquired in the number acquisition process to obtain the total number of unit data, and the unit acquired in the unit data number total calculation process By comparing the total number of data with a preset threshold value, and performing a variable-length code output process of outputting a variable-length code having a unit data number not exceeding the threshold value according to the result of the comparison. This is to remove the specific variable length code.

The video signal processing device according to claim 8 is the device according to claim 2, wherein the specific component removing means generates a digital video signal from the variable length coded data. Means, for the digital video signal generated by the digital video signal generating means, a specific digital signal removing means for removing a specific portion constituting the digital video signal, and a processing result of the specific digital signal removing means, A variable-length encoded data generating means for generating variable-length encoded data,
It is provided with a quantization matrix holding unit for holding a quantization matrix used for the processing in the digital video signal generation unit and the processing in the variable length coded data generation unit.

According to a ninth aspect of the present invention, in the video signal processing apparatus according to the first aspect, the coded data to be processed is obtained by intra-frame coding and inter-frame coding. The specific component removing means removes, as the specific component, a high-frequency component contained in intra-frame encoded data in the encoded data.

A video signal processing device according to a tenth aspect of the present invention is the video signal processing device according to the ninth aspect, wherein an intra-frame encoded portion extracting means for extracting intra-frame encoded data from the encoded data to be processed. A data holding unit for temporarily holding data, a read instruction signal generating unit for generating a signal for instructing a read timing for data held in the data holding unit, and a read instruction signal generating unit for generating a signal. Based on the signal
Data reading control means for controlling reading of data held in the data holding means.

The video signal processing apparatus according to claim 11 is the apparatus according to claim 10, wherein the specific component removing means removes the specific component from the processing result of the intra-frame coded part extracting means. The data holding means holds the processing result of the specific component removing means.

According to a twelfth aspect of the present invention, in the video signal processing apparatus according to the eleventh aspect, the specific component removing means outputs a first characteristic value to the processing result of the intra-frame coded part extracting means. A first specific component removing unit that removes the specific component based on the first component, and a second process that removes the specific component based on a second characteristic value with respect to a processing result of the intra-frame encoded part extracting unit. And a data holding means for storing a processing result of the first specific component removing means.
And a second data holding means for holding a processing result in the second specific component removing means, wherein the data read control means reads the data from the first data holding means. , And second data read control means for controlling reading from the second data holding means.

According to a thirteenth aspect of the present invention, in the video signal processing device according to the tenth aspect, the data holding means holds a processing result of the intra-frame coded part extracting means, and the specific component The removing means removes the specific component from the data held by the data holding means.

Further, the video signal processing apparatus according to claim 14 is the apparatus according to claim 13, further comprising a removal characteristic determining means for determining a characteristic value used for removing the specific component in the specific component removing means, The specific component removing means removes the specific component based on the characteristic value determined by the removing characteristic determining means.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 The video signal processing device according to the first embodiment of the present invention reduces the amount of data by performing inverse quantization and quantization using different quantization matrices. FIG. 1 is a block diagram showing a configuration of the video signal processing device according to the first embodiment. As shown, the video signal processing apparatus according to the first embodiment includes a VLD unit 102, an inverse quantization unit 103, a first
Matrix means 104, quantization means 105, second quantization matrix means 106, and VLC means 10
7, a variable length codeword data which is a device input of the video signal processing device is input from an input terminal 101, and a processed variable length code which is a device output of the video signal processing device is output from an output terminal 108. Output word data.

The VLD means 102 performs a decoding process on the input variable-length codeword data input from the input terminal 101 to generate a first DCT coefficient. The inverse quantization means 103 includes a first quantization matrix means 104 described later.
VLD using the first quantization matrix obtained from
An inverse quantization process is performed on the first DCT coefficient generated by the means 102 to generate inverse quantized data. The first quantization matrix unit 104 holds the first quantization matrix used for the processing in the inverse quantization unit 103, and outputs the first quantization matrix to the inverse quantization unit 103. The quantization means 105 uses the second quantization matrix obtained from the second quantization matrix means 106 described later to
Performs a quantization process on the generated inversely quantized data to generate a second DCT coefficient. The second quantization matrix means 106 holds the second quantization matrix used for the processing in the quantization means 105, and
5 is output. The VLC means 107 includes a quantization means 105
Performs an encoding process on the generated second DCT coefficient to generate output variable-length codeword data. The output variable-length codeword data is output from the output terminal 108 as a device output of the video signal processing device.

The operation of the thus configured video signal processing apparatus according to the first embodiment when processing variable-length codeword data will be described below. As a device input of the video signal processing device of the first embodiment, input variable-length codeword data to be subjected to data reduction is input to an input terminal 101, and is input to a VLD unit 102 inside the video signal processing device. . The VLD means 102 performs a predetermined decoding process on the input variable-length codeword data to generate a first DCT coefficient. Generated first D
The CT coefficient is converted from the VLD means 102 to the inverse quantization means 103
Is output to

In the first quantization matrix means 104, prior to processing in the video signal processing apparatus,
A first quantization matrix is retained, and
Upon input of the first DCT coefficient, the inverse quantization means 103 obtains the first quantization matrix from the first quantization matrix means 104. And the inverse quantization means 10
3 is the first DCT using the first quantization matrix.
An inverse quantization process is performed on the coefficients to generate inverse quantization data. The generated inversely quantized data is transmitted to the inverse quantization means 1
03 to the quantization means 105.

In the second quantization matrix means 106, prior to the processing in the video signal processing apparatus,
A second quantization matrix is retained, and
Upon input of the inversely quantized data, the quantization means 105 obtains a second quantization matrix from the second quantization matrix means 106. Then, the quantization means 105
Performs a quantization process on the inversely-quantized data by using a second quantization matrix to generate a second DCT coefficient.

Here, the second quantization matrix is the first quantization matrix.
The value is set to 0 for many high-frequency AC components than the quantization matrix of. Therefore, the second DCT generated by the quantization means 105
The coefficients are such that the values of the high-frequency AC components that are larger than the first DCT coefficient are 0.

The generated second DCT coefficient is output from the quantization means 105 to the VLC means 107. The VLC means 107 performs a predetermined variable length encoding process on the input second DCT coefficient, and generates output variable length codeword data. The generated output variable-length codeword data is output from the output terminal 108 to the outside of the device as the device output of the video signal processing device.

As described above, since the value of the second DCT coefficient is 0 for more high-frequency AC components than the first DCT coefficient, the data amount of the output variable-length codeword data is It is smaller than the long codeword data. In the video signal processing apparatus according to the first embodiment, the high-frequency AC having a value of 0 is set by setting the second quantization matrix.
Since the ratio of the components can be determined, the degree of data reduction in the output signal can be adjusted.

As described above, according to the video signal processing apparatus of the first embodiment, the VLD means 102 and the inverse quantization means 10
3. First quantization matrix means 104, quantization means 1
05, second quantization matrix means 106, and VLC
A means having a relatively small circuit scale because it has means 107 and does not perform conversion between digital and analog, and the quantization matrix used for the inverse quantization process is different from the quantization matrix used for the quantization process. Since the value of the high-frequency AC component of the second DCT coefficient generated by the quantization means 105 is set to be 0, the data amount of the output variable-length codeword data output from the VLC means 107 can be reduced. Becomes possible.

Embodiment 2 The video signal processing device according to the second embodiment of the present invention reduces the amount of data by directly processing DCT coefficients.
FIG. 2 is a block diagram showing a configuration of the video signal processing device according to the second embodiment. As shown in the figure, the video signal processing apparatus according to the second embodiment includes a VLD unit 202, an AC component reducing unit 203, and a VLC unit 204.
The input terminal 201 inputs variable-length codeword data which is a device input of the video signal processing device, and the output terminal 205 outputs processed variable-length codeword data which is a device output of the video signal processing device.

The VLD means 202 performs a decoding process on the input variable-length codeword data input from the input terminal 201, and generates a first DCT coefficient. The AC component reducing unit 203 is configured to output the first DC generated by the VLD unit 202.
A transform process is performed on the T coefficient to generate a second DCT coefficient. The VLC means 204 includes an AC component reducing means 203
Performs an encoding process on the generated second DCT coefficient to generate output variable-length codeword data. The output variable-length codeword data is output from an output terminal 205 as a device output of the video signal processing device.

The operation of the thus configured video signal processing apparatus of the second embodiment when processing variable-length codeword data will be described below. As the device input of the video signal processing device according to the second embodiment, input variable-length codeword data to be subjected to data reduction is input to the input terminal 201 and input to the VLD means 202 inside the video signal processing device. . The VLD means 202 performs a predetermined decoding process on the input variable-length codeword data to generate a first DCT coefficient. Generated first D
The CT coefficient is output from the VLD means 202 to the AC component reducing means 2.
03 is output.

In the AC component reduction means 203, prior to the processing in the video signal processing apparatus, a specific component whose value is changed in the conversion process among the AC components constituting the DCT coefficient to be processed is determined by setting. It has become. Here, by setting the high-frequency AC component as an object to be changed, it is possible to reduce the influence of the data amount reduction on the reproduction image quality.

The AC component reducing means 203 is provided by the VLD means 2
When the first DCT coefficient is input from 02, the value of the specific AC component is changed to 0 according to the setting, and the second DCT coefficient is generated. Therefore, the second DCT coefficient is a high-frequency AC having a value of 0 as compared with the first DCT coefficient.
It will contain more components. Generated second DC
The T coefficient is converted from the AC component reducing means 203 to the VLC means 20.
4 is output.

The VLC means 204 receives the input second DC
A predetermined variable-length coding process is performed on the T coefficient to generate output variable-length codeword data. The generated output variable-length codeword data is output from the output terminal 505 to the outside of the device as the device output of the video signal processing device. As in the case of the processing in the apparatus of the first embodiment, the second DC
Since the T coefficient has a value of 0 for more high-frequency AC components than the first DCT coefficient, the data amount of the output variable-length codeword data is smaller than the input variable-length codeword data. I have. In the video signal processing device according to the second embodiment, the value is set to 0
Can be determined, whereby the degree of data reduction in the output signal can be adjusted.

As described above, according to the video signal processing apparatus of the second embodiment, the VLD means 202, the AC component reducing means 203, and the VLC means 204 are provided, and the AC component reducing means 203 converts the specific AC component. By the processing, the value of the high-frequency AC component of the second DCT coefficient is set to 0, so that the data amount of the output variable-length codeword data output from the VLC means 204 can be reduced. Although the setting flexibility is slightly inferior, the circuit size can be further reduced as compared with the video signal processing device according to the first embodiment.

Embodiment 3 The video signal processing apparatus according to the third embodiment of the present invention analyzes the code length and performs a conversion process corresponding to the result, thereby reducing the data amount. FIG. 3 is a block diagram showing a configuration of the video signal processing device according to the third embodiment. As shown in the figure, the video signal processing device of the third embodiment
02, and an AC component reduction unit 303. The input terminal 301 receives the variable-length codeword data which is the device input of the video signal processing device, and the output terminal 304 outputs the device output of the video signal processing device. Outputs certain processed variable-length codeword data.

The code length analysis means 302 obtains the code length of the input variable length code word data by calculation. The AC component reduction unit 303 removes a specific portion from the input variable length codeword data based on the code length acquired by the code length analysis unit 302, and generates output variable length codeword data.

The operation of the thus configured video signal processing apparatus according to the third embodiment when processing variable-length codeword data will be described below. As a device input of the video signal processing device of the third embodiment, input variable-length codeword data to be subjected to data reduction is input to an input terminal 301, and a code length analysis unit 302 inside the video signal processing device includes: It is input to the AC component reduction unit 303.

The code length analysis means 302 obtains the code length of the input variable length code word data by calculation, and outputs a signal indicating the obtained code length to the AC component reduction means 303. A
The C component reduction unit 303 detects a break of the variable length codeword in the input variable length codeword data based on the signal input from the code length analysis unit 302, and indicates the end of the variable length codeword at a specific portion. A terminal code word (hereinafter, "EO
B ". ) Is inserted and the portion after the specific part is removed to generate output variable-length codeword data.

FIG. 4 is a diagram showing an example of the device A according to the third embodiment.
FIGS. 5 to 7 are flowcharts showing the processing procedure of the AC component reducing unit 303 when performing the processing shown in FIG. Hereinafter, the processing of the AC component reducing unit 303 according to the third embodiment will be described with reference to FIGS.

FIGS. 4A and 4B show the structures of the input variable-length codeword data input from the input terminal 301 and the output variable-length codeword data output from the output terminal 304 in FIG. FIG. As shown in FIG. 2A, the input variable-length codeword data is a representation of one DCT block by a set of variable-length codes V1 to Vn.
Vn is a code in which the variable length code length is Li and the number of DCT coefficients is Ni.

In the input variable-length codeword data, the code V1 located at the beginning of each codeword constituting the data is the lowest band data, and is located at the end except for the code Vn indicating the end. The code Vn-1 corresponds to the highest band data. Then, the AC component reduction unit 303 executes the processing procedure shown in FIGS. 5 to 7 based on the information to convert the input variable-length codeword data shown in FIG. Closer variable length code Vm to Vn-1
And output variable length codeword data composed of variable length codes V1 to Vm-1 shown in FIG.

In the video signal processing apparatus according to the third embodiment, the AC component reducing means 303 is one of the following: a DCT counting number reduction mode as the first mode, or a code length reduction mode as the second mode. The processing is executed in one of the modes. The procedure of the process performed by the AC component reduction unit 303 will be described below with reference to the flowcharts of FIGS.

(1) First Mode In the DCT coefficient number reduction mode, which is the first mode, the AC component reduction means 303 reduces the amount of data in order to keep the number of DCT coefficients constituting the output data within the limit. It is to reduce. FIG. 5 shows the AC component reducing means 3.
FIG. 13 is a flowchart illustrating a processing procedure of a DCT coefficient number reduction mode in the third embodiment.

When the process is started, in step 501 shown in the figure, the threshold value th of the number of DCT coefficients is input, and this value is set to the upper limit of the DCT coefficient allowed to be included in the output variable-length codeword data. Set as total. Therefore, the output variable-length codeword data is generated as including the DCT coefficients equal to or less than the threshold value by the processing shown in FIG.

In the following step 502, a variable i indicating the number of a certain variable length code from the head and a count value cnt for cumulatively adding the total number of DCT coefficients are initialized. As shown, the count value cnt has a value of 0,
Further, the variable i is given with the value 1 as an initial value.

Thereafter, the AC component reduction means 303 executes a reduction processing step group 520 in the first mode, which is composed of steps 503 to 510. In step 503, input variable-length codeword data (FIG. 4A)
) Is input, the i-th variable length code Vi from the beginning is read, and the variable length code length Li of the code is obtained.
From the result of the above-described analysis performed by the code length analysis unit 302 (FIG. 3), the AC component reduction unit 303 can know the variable length code length Li.

Next, step 504 is executed, and the AC component reducing means 303 determines whether or not the variable length code Vi input in step 503 is "EOB" which is a code indicating the end. If the code Vi is “EOB”, that is, if the end of the input variable-length codeword data to be processed has been reached, step 510 is executed, and the AC component reducing unit 303 constructs the output variable-length codeword data. As the code word to be processed, “EOB” indicating the end is output, and the process of the AC component reduction unit 303 ends.

On the other hand, if the code Vi is not "EOB" in the determination at step 504, that is, if the end of the input variable-length codeword data to be processed has not been reached, the processing from step 505 is executed. First, in step 505, by decoding the variable length code Vi. The number N of DCT coefficients in the code Vi
Get i.

Then, in step 506, the count value cnt held at that time is compared with step 505.
The number Ni of the DCT coefficients obtained in the step is added. In the subsequent step 507, the count value cnt obtained by the addition processing in step 506 is compared with the threshold value th set as the upper limit value in step 501, and it is determined whether or not the count value cnt has exceeded the threshold value th. judge.

If it is determined in step 507 that the count value cnt does not exceed the threshold value, step 508 is executed, and the AC component reducing means 3
03 outputs the code Vi acquired in step 503 as a code word constituting output variable-length code number data, and proceeds to step 509. On the other hand, if the count value cnt does not exceed the threshold value in the determination at step 507, the AC component reduction unit 303 proceeds to step 509 without executing step 508. Therefore, in this case, the code Vi obtained in step 503 is not output as a code constituting the output variable-length codeword data.

Whether step 508 has been performed or not, step 50
In step 9, the process returns to step 503 after the variable i specifying the variable-length code has been incremented. Therefore, the process is repeated for the next code constituting the input variable-length codeword data (FIG. 4A). Become.

As described above, the AC component reducing means 303
For each code constituting the input variable-length codeword data, a first step including steps 503 to 510 is performed.
The processing of the mode reduction processing step group 520 is repeatedly executed, and when the end of the input variable-length codeword data is reached, step 510 is executed according to the determination processing in step 504, and the processing ends. .

When the processing shown in FIG. 5 is performed on the input variable-length codeword data shown in FIG. 4A, first, in step 501, the threshold value th is set to a value corresponding to the desired data reduction amount. The number of DCT coefficients is input. And
Immediately after the initial value setting in step 502, step 5
When 03 is executed, the code V1 shown in FIG. 4A is extracted as a code to be processed. In the determination in the subsequent step 504, the code V1 is not “EOB”, so that step 505 and subsequent steps are executed. In step 505, the number N1 of DCT coefficients of V1 is obtained. In step 506, the number N1 is added to the count value of the initial value 0, and in step 507, the count value cnt whose value is N1 is compared with the threshold value th.

Here, the count value cnt is equal to the threshold value t.
Since h is smaller than h, step 508 is executed, and the first variable-length codeword V1 is output as a code constituting output variable-length codeword data. Therefore, as shown in FIG. 4 (b), the code V1 is added to the output variable-length codeword data.
Will be included. Thereafter, in step 509, the variable i is incremented, the value of the variable i is changed from 1 to 2, and the process returns to step 503.

The processing after step 503 is the same as that shown in FIG.
This is performed for the second code V2 constituting the input variable-length codeword data shown in FIG. Here, the sum of the numbers of DCT coefficients up to the code Vm-1 shown in FIG.
2 + ... + Nm-1 is smaller than the upper threshold value th set in step 501. In this case, step 503 is performed for reference numerals V2 to Vm-1 shown in FIG.
The processing from Step 509 to Step 509 is the same as that performed when the code V1 is performed as described above. Therefore, when these codes are to be processed, step 508 is executed, and as shown in FIG. 4 (b), codes V2 to Vm-1 are included in the output variable-length codeword data. Become.

When the variable i becomes the value m by the increment processing in step 509 and the processing in step 503 and subsequent steps is executed, the processing is executed for the variable length code Vm shown in FIG. Steps 506 to 506 are performed in the same manner as described above. Here, the sum of the numbers of DCT coefficients up to the code Vm, N1 + N2 +... + Nm shown in FIG.
It is assumed that the value exceeds the upper threshold value th set in step 501. Therefore, according to the determination in step 507, step 508 is not executed and the process proceeds to step 509, and the code Vm is not included in the output variable-length codeword data as shown in FIG. 4 (b).

The processing is similarly performed for the variable length code Vm + 1 and the subsequent code Vn-1 shown in FIG. 4A, and these codes are output variable length codes as shown in FIG. It will not be included in the codeword data. Thereafter, when the code Vn located at the terminal end is extracted in step 503, Vn becomes "E".
Since “OB” is output, “EOB” is output in step 510 following the determination in step 504, and then the processing in the AC component reduction unit ends.

Thus, the AC component reducing means 303
(FIG. 3) deletes the variable-length codes Vm to Vn-1 closer to the high-frequency component from the input variable-length codeword data shown in FIG. Output variable-length codeword data composed of V1 to Vm-1 is generated and output. Therefore, the data amount is reduced by the amount of the hatched portion shown in FIG.

(2) Second Mode In the code length reduction mode, which is the second mode, the AC component reduction means 303 reduces the amount of data in order to keep the code length of the output data within the limit. is there. FIG.
FIG. 9 is a flowchart illustrating a processing procedure of a code length reduction mode in the AC component reduction unit 303.

When the process is started, a code length threshold value th is input in step 601 shown in FIG.
This is set as the value of the upper limit code length allowed to have in the output variable length codeword data. Accordingly, the output variable-length codeword data having a code length equal to or smaller than the threshold is generated by the processing shown in FIG.

In the following step 602, a variable i indicating the number of a certain variable length code from the head and a count value cnt for cumulatively adding the sum of the code lengths are initialized. As shown in the figure, the count value cnt is assigned with a value 0 as an initial value, and the variable i is assigned with a value 1 as an initial value.

Thereafter, the AC component reducing means 303 executes a second mode reduction processing step group 620 comprising steps 603 to 609. In step 603, input variable-length codeword data (FIG. 4A)
) Is input, the i-th variable length code Vi from the beginning is read, and the variable length code length Li of the code is obtained.
From the result of the above-described analysis performed by the code length analysis unit 302 (FIG. 3), the AC component reduction unit 303 can know the variable length code length Li.

Next, step 604 is executed, and the AC component reducing means 303 determines whether or not the variable length code Vi input in step 603 is "EOB" which is a code indicating the end. If the code Vi is “EOB”, that is, if the end of the input variable-length codeword data to be processed has been reached, step 609 is executed, and the AC component reducing unit 303 constructs the output variable-length codeword data. As the code to be executed, “EOB” indicating the end is output, and the process of the AC component reduction unit 303 ends.

On the other hand, if the code Vi is not "EOB" in the determination in step 604, that is, if the end of the input variable-length codeword data to be processed has not been reached, the processing from step 605 is executed. First, in step 605, the code length Li acquired in step 603 is added to the count value cnt held at that time. In the subsequent step 606, the count value cnt obtained in the addition processing in step 605 is compared with the threshold value th set as the upper limit value in step 601 to determine whether or not the count value cnt has exceeded the threshold value th. judge.

If it is determined in step 606 that the count value cnt does not exceed the threshold value, step 607 is executed, and the AC component reducing means 3
03 outputs the code Vi acquired in step 503 as a code constituting the output variable-length codeword data, and proceeds to step 608. On the other hand, if the count value cnt does not exceed the threshold value in the determination in step 606, the AC component reduction unit 303 proceeds to step 608 without executing step 607. Therefore, in this case, the code Vi obtained in step 603 is not output as a code constituting the output variable-length codeword data.

Whether step 607 has been performed or not, step 60
In step 8, the process returns to step 603 after the variable i specifying the variable-length code is incremented, so that the process is repeated for the next code constituting the input variable-length codeword data (FIG. 4A). Become.

As described above, the AC component reducing means 303
For each code constituting the input variable-length codeword data, a second step including steps 603 to 609 is performed.
The processing of the mode reduction processing step group 620 is repeatedly executed, and when the end of the input variable-length codeword data is reached, step 609 is executed according to the determination processing in step 604, and the processing ends. .

When the processing shown in FIG. 6 is executed on the input variable-length codeword data shown in FIG. 4A, first, in step 601, the threshold value th is set to a value corresponding to the desired data reduction amount. The code length is input. And step 6
When step 603 is executed immediately after the initial value setting in 02, the code V1 shown in FIG. 4A is extracted as a code word to be processed. In the determination in the subsequent step 604, the code V1 is not “EOB”,
Thereafter, the code length L1 is added to the count value of the initial value 0 in step 605, and the count value cn whose value is L1 is added in step 606.
t and a threshold value th are compared.

Here, the count value cnt is equal to the threshold value t.
Since h is smaller than h, step 607 is executed, and the first variable-length code V1 is output as a code constituting output variable-length codeword data. Therefore, FIG.
As shown in (b), the code V1 is included in the output variable-length codeword data. Then, in step 608,
The variable i is incremented, and the value of the variable i is 1 to 2
After that, the process returns to step 603.

The processing after the next step 603 is as shown in FIG.
This is performed for the second code V2 constituting the input variable-length codeword data shown in FIG. Here, the sum of the code lengths up to the code Vm-1 shown in the figure, L1 + L2 +... + L
m-1 is the upper limit threshold th set in step 601
It shall be less than. In this case, the processes from step 603 to step 608 are the same as those performed on the code V1 as described above for the codes V2 to Vm-1 shown in FIG. Therefore, if these codes are to be processed, step 607 is executed. Therefore, as shown in FIG. 4 (b), codes V2 to Vm-1 are included in the output variable-length codeword data. Become.

When the variable i becomes the value m by the increment processing in step 608 and the processing after step 603 is executed, the processing is executed for the variable length code Vm shown in FIG. Steps 605 to 605 are performed in the same manner as described above. Here, the sum of the code lengths up to the code Vm, L1 + L2 +... + Lm shown in FIG.
It is assumed that the value exceeds the upper threshold value th set in 01. Therefore, according to the determination of step 606, step 6
07 is not executed and the process proceeds to step 608, and the code Vm is not included in the output variable-length codeword data as shown in FIG.

The processing is similarly performed for the variable length code Vm + 1 and the subsequent code Vn-1 shown in FIG. 4A, and these codes are output variable length codes as shown in FIG. It will not be included in the codeword data. Thereafter, when the code Vn located at the terminal end is extracted in step 603, the code Vn is “EOB”, and after “EOB” is output in step 609 following the determination in step 604, AC
The processing in the component reduction means ends.

In this way, the AC component reducing means 303
(FIG. 3) deletes the variable-length codes Vm to Vn-1 closer to the high-frequency component from the input variable-length codeword data shown in FIG. Output variable-length codeword data composed of V1 to Vm-1 is generated and output. Therefore, the data amount is reduced by the shaded portion shown in FIG.

As described above, the AC component reduction means 303 of the third embodiment removes the high-frequency component of the variable-length codeword data in any of the reduction modes. Of these, the first mode adjusts the degree of data compression according to the number of DCT counts, and is therefore effective when it is desired to suppress image distortion of an output video signal. On the other hand, in the second mode, the degree of data compression is adjusted by the accumulated code length, so that the data amount of the output video signal can be made uniform, which is effective when the data amount after reduction is determined. It is.

AC component reduction means 303 of the third embodiment
May be fixedly determined according to the use of the data to be output in which mode, but as described below, the processing is performed by switching the mode. It is also possible to use FIG. 7 is a flowchart illustrating a schematic processing procedure in a case where the AC component reduction unit 303 according to the third embodiment executes processing by switching modes according to the reduction mode specified by the user. .

When the process is started, in step 701, the same initialization as step 502 in the flow of FIG. 5 and step 602 in the flow of FIG. 6 is performed. In the initialization processing, the count value cnt is set to a value of 0, and is used as one of the sum of the number of DCT coefficients and the sum of the code lengths in accordance with the designation of the reduction mode in the subsequent stage. In step 702, a reduction mode is designated, and a threshold value indicating the upper limit of the number of DCT coefficients or the upper limit of the code length is set in accordance with the mode.

In step 703, it is determined whether or not the reduction mode specified in step 702 indicates processing in the first mode. If the first mode has been specified, the process proceeds to step 520. If not, step 6
Move to 20. Step 520 is similar to the first mode reduction processing step group 520 shown in the flow of FIG.
Step 620 is performed in the same manner as the second mode reduction processing step group 620 shown in the flow of FIG. Therefore, even in this processing procedure, the data amount is reduced by either the first or second reduction mode.

As described above, the video signal processing apparatus according to the third embodiment includes the code length analyzing means 302 and the AC component reducing means 203, and sets the upper limit of the number of DCT coefficients or the code length. By doing so, the AC component reducing means 2
At 03, the specific AC component is deleted corresponding to the upper limit, so that the data amount of the output variable-length codeword data can be reduced. Further, the circuit scale can be further reduced as compared with the video signal processing device according to the second embodiment.

Embodiment 4 The video signal processing device according to the fourth embodiment of the present invention reduces the amount of data by performing a filtering process on a digital video signal. FIG. 8 is a block diagram showing a configuration of a video signal processing device according to the fourth embodiment. As shown, the video signal processing apparatus according to the fourth embodiment includes a
2, inverse quantization means 803, inverse DCT means 804, filter means 805, DCT means 806, quantization means 807,
It comprises a quantization matrix means 808 and a VLC means 809, receives variable-length codeword data as an input of the video signal processing device from an input terminal 801, and outputs a video signal processing device from an output terminal 810. Output the processed variable-length codeword data as output.

The VLD means 802 performs a decoding process on the input variable-length codeword data input from the input terminal 801 to generate a first DCT coefficient. The inverse quantization unit 803 performs an inverse quantization process on the first DCT coefficient generated by the VLD unit 802 using a quantization matrix acquired from a quantization matrix unit 808 described below, and generates the inverse quantized data. Generate

The inverse DCT means 804 includes the inverse quantization means 80
3 performs an inverse DCT process on the generated inversely quantized data to generate a digital video signal. Filter means 80
5 removes high frequency components from the digital video signal generated by the inverse DCT means 804 and generates a filtered digital video signal. The DCT unit 806 performs a DCT process on the filtered digital video signal generated by the filter unit 805 to generate a DCT coefficient before quantization. The quantization unit 807 performs a quantization process on the pre-quantization DCT coefficient generated by the DCT unit 806,
Generate a second DCT coefficient.

The quantization matrix means 808 performs the inverse quantization processing in the inverse quantization means 803 and the quantization means 807
, And outputs it to the inverse quantization means 803 and the quantization means 807. In the video signal processing device according to the first embodiment, the inverse quantization means 103 (FIG. 1) and the quantization means 1
05 means that the first and second quantization matrices are obtained from the first and second quantization matrix means 104 and 106, respectively, and are used for processing. In the first embodiment, , Inverse quantization means 803 and quantization means 8
07 is for acquiring the same quantization matrix from the common quantization matrix means 808 and using it for processing.

The VLC means 809 performs an encoding process on the second DCT coefficient generated by the quantization means 807,
Generate output variable-length codeword data. This output variable-length codeword data is output as a device output of the video signal processing device,
Output from the output terminal 810.

The operation of the thus configured video signal processing apparatus of the fourth embodiment when processing variable-length codeword data will be described below. As a device input of the video signal processing device according to the fourth embodiment, input variable-length codeword data to be subjected to data reduction is input to an input terminal 801 and input to VLD means 802 inside the video signal processing device. . The VLD means 802 performs a predetermined decoding process on the input variable-length codeword data, and generates a first DCT coefficient. Generated first D
The CT coefficient is obtained from the VLD means 802 to the inverse quantization means 803
Is output to

In the quantization matrix means 804,
Prior to the processing in the video signal processing apparatus, the quantization matrix is held, and if the first DCT coefficient is input, the inverse quantization means 803 outputs the quantization matrix from the quantization matrix means 808. To get. Then, the inverse quantization means 803 performs an inverse quantization process on the first DCT coefficient using the quantization matrix to generate inversely quantized data. The generated inverse quantization data is output from the inverse quantization means 803 to the inverse DCT means 804.

The inverse DCT means 804 performs an inverse DCT process on the inversely quantized data to generate a digital video signal. The digital video signal is composed of a luminance signal and a color difference signal, and is output from the inverse DCT unit 804 to the filter unit 805. Filter means 805
The digital video signal is subjected to a filtering process for removing a high-frequency component to generate a filtered digital video signal. The generated filtered digital video signal is output from the filter unit 805 to the DCT unit 805.

The DCT means 806 performs DCT processing on the input filtered digital video signal,
Generate pre-quantization DCT coefficients. Therefore, DC before quantization
The T coefficient is such that the value of the AC component corresponding to the high-frequency component removed by the filter unit 805 is 0.
The generated DCT coefficients before quantization are output from the DCT unit 806 to the quantization unit 807.

When the quantizing means 807 receives the DCT coefficient before quantization, it obtains a quantization matrix from the quantization matrix means 808. Then, quantization means 807
Performs a quantization process on the pre-quantization DCT coefficient using a quantization matrix to generate a second DCT coefficient.

Here, as described above, the quantization means 807
Uses a common quantization matrix with the inverse quantization means 803, and in this regard, the second quantization matrix used for the quantization process is smaller than the first quantization matrix used for the inverse quantization process. This is different from the device of the first embodiment in which the values are set to 0 for many high-frequency AC components. However, the quantization means 8
Since the pre-quantization DCT coefficient input to 07 has a value of more high-frequency AC components being 0 due to the effect of high-frequency removal in the filter means 805 in the previous stage, the quantization means 807 Generate the second DCT coefficient, the value of more high-frequency AC components than the first DCT coefficient is zero.

The generated second DCT coefficient is output from quantization means 807 to VLC means 809. The VLC means 809 performs a predetermined variable length coding process on the input second DCT coefficient, and generates output variable length codeword data. The generated output variable-length codeword data is output from the output terminal 810 to the outside of the device as the device output of the video signal processing device.

As described above, since the value of the second DCT coefficient is 0 for more high-frequency AC components than the first DCT coefficient, the data amount of the output variable-length codeword data is It is smaller than the long codeword data. In the video signal processing apparatus according to the fourth embodiment, the ratio of the high-frequency AC component having a value of 0 can be determined by setting the filtering process in the filtering means, thereby reducing the data in the output signal. The degree can be adjusted.

Then, regarding the influence of the filter processing,
Since the digital video signal composed of the luminance signal and the color difference signal on the input side and the output side of the filter means 805 can be easily confirmed, the apparatus according to the fourth embodiment has the following features. Although the circuit scale is larger than that of the first embodiment, the setting can be performed more flexibly and easily.

As described above, according to the video signal processing apparatus of the fourth embodiment, the VLD means 802 and the inverse quantization means 80
3, inverse DCT means 804, filter means 805, DCT
Means 806, quantization means 807, quantization matrix means 808, and VLC means 809, and high-frequency components are removed by filtering the digital video signal. It is possible to reduce the amount of data.
Since the removal of the high frequency component is performed on the digital video signal, the reduction of the data amount can be flexibly set, and the setting can be easily confirmed.

Embodiment 5 FIG. The video signal processing apparatus according to the fifth embodiment of the present invention receives a bit stream signal, reduces the amount of data, and generates two types of high-speed playback data. FIG. 9 shows the fifth embodiment.
1 is a block diagram showing a configuration of a video signal processing device according to the first embodiment. As shown in the figure, the video signal processing apparatus according to the fifth embodiment includes an I-picture extracting unit 902, a data amount reducing unit 90
3, a memory 904, a timing signal generating means 905, and a memory control means 906.
A bit stream signal that is a device input of the video signal processing device is input from the output terminal 907, and two types of high-speed reproduction data that are device outputs of the video signal processing device are output from an output terminal 907;
It outputs TPH data and TPL data.

The I picture extracting means 902 extracts I picture data from a bit stream signal to be processed. The data amount reducing unit 903 reduces the data amount of the I-picture data extracted by the I-picture extracting unit by removing the high-frequency components, and generates reduced data. The memory 904 holds the reduced data generated by the data amount reducing unit 903. The timing signal generator 905 generates a timing signal that specifies the timing at which data stored in the memory 904 is read. The memory control unit 906 controls data input / output in the memory 904 according to the timing signal generated by the timing signal generation unit 905.

FIG. 10 is a block diagram showing the internal configuration of the data amount reducing means 903 provided in the video signal processing apparatus according to the fifth embodiment. As shown in FIG.
03 denotes a VLD unit 1002, an inverse quantization unit 1003,
Inverse DCT means 1004, filter means 1005, DCT
Means 1006, quantization means 1007, quantization matrix means 1008, and VLC means 1009,
The I picture data extracted by the I picture extraction means 902 is input from the input terminal 1001, and the reduced data is output from the output terminal 1010.

That is, the data amount reducing means 903 provided in the video signal processing apparatus of the fifth embodiment is different from that of the fourth embodiment.
Has the same internal configuration as the video signal processing device according to the above. Therefore, the VLD means 1002, the inverse quantization means 1
003, inverse DCT means 1004, filter means 100
5, DCT unit 1006, quantization unit 1007, quantization matrix unit 1008, and VLC unit 1009 are the same as 802 to 809 in the fourth embodiment, and thus description thereof will be omitted.

The operation of the thus configured video signal processing apparatus according to the fifth embodiment when processing a bit stream signal will be described below. Embodiment 5
As a device input of the video signal processing device, a bit stream signal is input to an input terminal 901 and is input to an I picture extraction unit 902 inside the video signal processing device. Here, the input bit stream signal is MP
According to a general standard such as EG2-TS,
And variable-length codeword data in which I picture data by intra-frame coding and P or B picture data by inter-frame coding are mixed. .

The I picture extracting means 902 specifies I picture data by syntax analysis of the input bit stream signal, extracts the data, and outputs the data to the data amount reducing means 903. As described above, the data of the P-picture and the B-picture have properties unsuitable to be used for high-speed reproduction data, and will not be used in the subsequent processing.

In the data amount reduction unit 903 shown in FIG. 10, I picture data, which is variable length codeword data, is input to the VLD unit 1002. The data amount reduction unit 903 performs the same operation as the video signal processing device according to the fourth embodiment, and the VLC unit 1009 outputs reduced data from which high-frequency components have been removed. In FIG. 9, the reduction-processed data generated by the data amount reduction unit 903 is output to the memory 904 and stored.

The data held in the memory 904 is read out, output to the outside of the device, recorded, transmitted, and the like. Here, outside the device, the data is stored on a tape recording medium as high-speed reproduction data. Shall be recorded. Therefore, it is necessary to record at a predetermined position on the tape recording medium as shown in FIG.

In the video signal processing apparatus according to the fifth embodiment, the timing signal generating means 905 generates a timing signal for designating a readout timing required for recording at a predetermined position as described above. This is output to the memory control means 906. The memory control unit 906 performs control so that the reduced data stored at an appropriate position on the memory 904 is read out and output from the output terminal 907 in accordance with the input timing signal.

The video signal processing apparatus according to the fifth embodiment has
Since PH data and TPL data are generated, the timing signal generating means 905 generates a TPH data read timing signal and a TPL data read timing signal so that recording as shown in FIG. 14 can be performed. Things. Thereby, the memory control means 9
The data read from the memory 904 and output from the output terminal 907 according to the control of 06 are recorded as TPH data or TPL data at an appropriate position on the tape recording medium.

As described above, the video signal processing apparatus according to the fifth embodiment includes the I picture extracting means 902, the data amount reducing means 903, the memory 904, the timing signal generating means 905, and the memory control means 906. The data amount reducing unit 903 has the same internal configuration as that of the video signal processing apparatus according to the fourth embodiment, thereby reducing the data amount by removing the high frequency component of the extracted I picture data.
It is possible to generate high-speed reproduction data that does not impair the feeling of motion while suppressing deterioration in image quality.

In the video signal processing apparatus according to the fifth embodiment, the internal configuration of the data amount reducing means 903 is the same as that of the apparatus according to the fourth embodiment. Similarly, flexible settings can be made for data amount reduction. However, the data amount reducing means 90
3 is not limited to those having such an internal configuration,
Even if it has an internal configuration equivalent to that of the video signal processing device of the first, second, or third embodiment, the TPH data and T
PL data can be output.
Although the setting flexibility is inferior to that shown in the above, the circuit size can be reduced.

Embodiment 6 FIG. The video signal processing apparatus according to the sixth embodiment of the present invention generates two types of high-speed reproduction data in the same manner as in the fifth embodiment. A corresponding reduction amount can be set. FIG. 11 is a block diagram showing a configuration of a video signal processing device according to the sixth embodiment.
As shown in the figure, the video signal processing device of the sixth embodiment
I picture extraction unit 1102, first data amount reduction unit 1103, first memory 1104, second data amount reduction unit 1105, second memory 1106, timing signal generation unit 1107, first memory control unit 1108, And a second memory control unit 1108, like the device of the fifth embodiment, to input a bit stream signal which is a device input of the video signal processing device from an input terminal 1101, and to output the bit stream signal from an output terminal 1110. It outputs two types of high-speed reproduction data, TPH data and TPL data, which are device outputs of the video signal processing device.

The I picture extracting means 1102 extracts I picture data from a bit stream signal to be processed. First and second data amount reducing means 110
3 and 1105 are the I pictures extracted by the I picture extraction means.
By removing high-frequency components from the picture data, the data amount is reduced, and reduced data is generated. Each of the first and second data amount reducing units 1103 and 1105 has the internal configuration shown in FIG. 10 similarly to the data amount reducing unit 903 included in the device of the fifth embodiment. Each of the reduction processes performed may have different characteristics. Here, it is assumed that the amount of data reduction differs between the two.

First and second memories 1104 and 1104
106 is a first and second data amount reducing unit 110
3 and 1105 respectively hold the reduced data. The timing signal generation unit 1107 generates a timing signal that specifies the timing for reading the data held in the first and second memories 1104 and 1106. The first and second memory control means 1108 and 1109 correspond to the first, second and third memory control means in response to the timing signal generated by the timing signal generation means 1107.
And data input / output in the second memories 1104 and 1106, respectively.

The video signal processing apparatus according to the fifth embodiment has the structure shown in FIG.
As shown in the figure, the data reduction unit (903) and the memory (9
04) and one memory control means (905). Since both TPH data and TPL data, which are two types of high-speed reproduction data, are processed by these, any of the data is As a result, the same amount of data is reduced.

As described above, since the maximum search speed differs between TPH data and TPL data, the allowable limit for the degree of image quality deterioration due to the reduction in the data amount is different. The video signal processing apparatus according to the fifth embodiment has a reduced circuit scale in order to reduce the same data amount for any data.
The apparatus according to the sixth embodiment uses different data reduction units, memories, and memory control units for processing for TPH data and processing for TPL data, thereby reducing different data amounts. Is what you can do.

The operation of the video signal processing apparatus according to the sixth embodiment configured as described above when processing a bit stream signal will be described below. Embodiment 6
As a device input of the video signal processing device, a bit stream signal is input to an input terminal 1101 and input to an I-picture extraction unit 1102 inside the video signal processing device. As in the case of the fifth embodiment, the input bit stream signal is generated by compression encoding including intra-frame and inter-frame encoding according to a general standard such as MPEG2-TS. , Variable-length codeword data in which I picture data obtained by intra-frame coding and P or B picture data obtained by inter-frame coding are mixed.

The I picture extracting means 1102 specifies I picture data by syntax analysis of the input bit stream signal, extracts the data, and
To the data amount reducing unit 1103 and the second data amount reducing unit 1105. As in the case of the fifth embodiment, the data of the P picture and the B picture are not used in the subsequent processing.

The first and second data amount reduction means 1103 and 1105 having the internal configuration shown in FIG. 10 perform a data amount reduction process for removing high-frequency components according to the respective settings, and the first and second data amount reduction units 1103 and 1105 having different reduction amounts. , And second processed data are generated. The generated first and second processed data are stored in a first and second memory 110, respectively.
4, and 1106.

The timing signal generating means 1107 determines that the processed data held in each memory is
A timing signal is read out as PH data or TPL data and specifies a read timing required to be recorded at a predetermined position on an external recording medium. The timing signal generating means sends the generated first timing signal to the first memory control means 1108 and sends the generated second timing signal to the second memory control means 11.
09 is output. Memory control means 1108 or 110
Reference numeral 9 indicates that the reduced data stored in an appropriate position on the first or second memory 1104 or 1106 is read out in response to the input timing signal and output from the output terminal 1110. To control. This allows
The data output from the output terminal 1110 is recorded at an appropriate position on the tape recording medium as TPH data or TPL data.

As described above, according to the video signal processing apparatus of the sixth embodiment, the I picture extracting unit 1102, the first data amount reducing unit 1103, the first memory 1104, and the second data amount reducing unit 1105 , The second memory 110
6. Equipped with a timing signal generator 1107, a first memory controller 1108, and a second memory controller 1108, and removes high frequency components of I picture data extracted similarly to the video signal processing device of the fifth embodiment. Embodiment 5 is to generate data for high-speed reproduction in which the amount of data is reduced and the deterioration in image quality is suppressed, and the feeling of movement is not impaired.
Although the circuit scale is larger than that of the video signal processing device, it is possible to perform reduction processing suitable for each high-speed reproduction data for which different image quality is desired.

In the video signal processing apparatus according to the sixth embodiment, the first and second data amount reducing units 1103 and 1105 have the same internal configuration as the apparatus according to the fourth embodiment. Although it is assumed that flexible setting can be performed, the video signal processing apparatus according to the first, second, or third embodiment has the same internal configuration as the data amount reducing unit 903 included in the apparatus according to the fifth embodiment. In this case, the circuit scale can be reduced.

Embodiment 7 FIG. The video signal processing device according to the seventh embodiment of the present invention can set a reduction amount corresponding to the required reproduction image quality for each of the two types of data in the same manner as in the sixth embodiment. Can be set. FIG. 12 is a block diagram showing a configuration of the video signal processing device according to the seventh embodiment. As shown in the figure, the video signal processing device of the seventh embodiment
Picture extracting means 1202, first data amount reducing means 1
203, a first memory 1204, a second data amount reducing unit 1205, a second memory 1206, a timing signal generating unit 1207, a first memory control unit 1208, and a second memory control unit 1208. Similarly to the device of the fifth embodiment, a bit stream signal which is a device input of the video signal processing device is input from an input terminal 1201, and two types of high-speed signals which are device outputs of the video signal processing device are input from an output terminal 1210. It outputs reproduction data, TPH data and TPL data. And Embodiment 7
The video signal processing device of the first
A first data amount input terminal 1211 for inputting a first data amount value to the third data amount, and a second data amount reduction unit 120
5 is provided with a second data amount value input terminal 1212 for inputting a second data amount value. That is,
The video signal device according to the sixth embodiment has a configuration in which a first data amount value input terminal 1211 and a second data amount value input terminal 1212 are added.

The first data amount reduction means 1203
A data amount reduction process is performed in accordance with the first data amount value input from the data amount value input terminal 1211 of (1). The second data amount reduction unit 1205 performs a data amount reduction process corresponding to the second data amount value input from the second data amount value input terminal 1212. I picture extraction means 1202,
First memory 1204, second memory 1206, timing signal generating means 1207, first memory control means 12
08 and the second memory control means 1208
1102, 1 included in the video signal processing device of the sixth embodiment
104, 1106, and 1107 to 1109.

The operation of the video signal processing apparatus of the seventh embodiment configured as described above when processing the input bit stream signal is such that the first and second data amount values are externally set to the first and second data amount values. , And second data amount reducing means 1
203 and 1205, except that the first and second data amount reduction means 1203 and 1205 determine and process the data reduction amount corresponding to the input data amount value, respectively. This is the same as the video signal processing device according to the sixth embodiment. The amount of data input from outside can specify the amount of data to be reduced or the amount of data after reduction, and should be input before processing or at any time during processing. Can be done.

As described above, according to the video signal processing device of the seventh embodiment, the video signal processing device of the sixth embodiment has:
A first data amount value input terminal 1211 and a second data amount value input terminal 1212 are added. Like the video signal processing device according to the sixth embodiment, respective high-speed reproductions in which different image qualities are desired. Can reduce the amount of data reduction and adjust the playback image quality of each high-speed playback data by performing the reduction process suitable for the data for use and inputting the data amount value at any time. Becomes

In the video signal processing apparatus according to the seventh embodiment, the data amount reduction means (1203, 1205) is similar to the video signal processing apparatuses according to the fifth and sixth embodiments.
It can have the same internal configuration as the video signal processing device of any of the first to fourth embodiments.

Embodiment 8 FIG. The video signal processing apparatus according to the eighth embodiment of the present invention can set a reduction amount corresponding to the required reproduction image quality for each of the two types of data similarly to the seventh embodiment, Can be set. FIG. 13 is a block diagram showing a configuration of a video signal processing device according to the eighth embodiment. As shown in the figure, the video signal processing device of the eighth embodiment
Picture extraction unit 1302, memory 1303, data amount reduction unit 1304, memory control unit 1305, data amount selection unit 1306, and timing signal generation unit 130
7, a bit stream signal that is a device input of the video signal processing device is input from an input terminal 1301, and two types of high-speed reproduction data that are device outputs of the video signal processing device are output from an output terminal 1310; It outputs TPH data and TPL data. Also, in the eighth embodiment, the first and second
Data amount value input terminals 1308 and 1309 of
Although the first and second data amount values are input from outside the device, in the video signal processing device of the eighth embodiment, the first and second data amount values are: All are input to the data amount selection means 1305.

The I picture extracting means 1302 extracts I picture data from the bit stream signal to be processed. The memory 1303 stores the I picture extracting means 13
02 holds the extracted I picture data. The data amount reducing unit 1304 holds the I picture data stored in the memory 1303 under the control of the memory control unit 1305 described later based on the data amount value input from the data amount selecting unit 1306 described later. The amount of data is reduced by removing the area component, and reduced data is generated. In the eighth embodiment, the reduced data is output as TPH data or TPL data.

The data amount selecting means 1306 determines whether or not it is the timing of the TPH data in accordance with a timing signal input from a timing signal generating means 1307 described later.
Depending on the timing of the TPL data, an appropriate data amount value is selected from the input first and second data amount values, and this is output to the data amount reduction unit 1304. The memory control unit 1305 controls data input / output in the memory 1303 according to a timing signal generated by a timing signal generation unit 1307 described later.
The timing signal generation unit 1307 generates a timing signal that specifies a timing at which data stored in the memory 1303 is read. In the eighth embodiment, the timing signal generated by the timing signal generating means 1307 is input to the memory control
In addition to being used for data read control from the data 03, the data is also input to the data amount selection unit 1305 and used for selecting a data amount value.

The operation of the video signal processing apparatus thus configured according to the eighth embodiment when processing a bit stream signal will be described below. Embodiment 8
As a device input of the video signal processing device, a bit stream signal is input to an input terminal 1301 and input to an I-picture extraction unit 1302 inside the video signal processing device. Also in the eighth embodiment, the input bit stream signal is generated by compression encoding including intra-frame and inter-frame encoding according to a general standard such as MPEG2-TS. This is variable-length codeword data in which I picture data obtained by inner coding and P or B picture data obtained by inter-frame coding are mixed.

The I picture extracting means 1302 specifies I picture data by syntax analysis of the input bit stream signal, extracts the data, and outputs the data to the memory 1303. Also in the eighth embodiment, P
The picture data and the B picture data are not used in the subsequent processing. The I picture data is held in the memory 1303.

The timing signal generating means 1307
A timing signal designating appropriate data read timing for outputting H data or TPL data is generated, and is output to the memory control unit 1305 and the data amount selection unit 1306. The memory control means 1305
Appropriate data is read from the memory 1303 in response to the input timing signal, and the data amount
04 to be input.

On the other hand, the data amount selection means 1306 has first and second data amount input terminals 1308 and 130
9, the first and second data amount values are input from outside the device. Data amount selection means 1306
When a timing signal is input to the
306 is the timing of TPH data or TPL
One of the data amount values is selected according to the data timing, and the selected data amount value is output to the data amount reducing unit 1304.

The data amount reduction means 1304
Data amount selecting means 1 for the data inputted from
The high frequency component is removed from the data so as to realize the data reduction amount determined based on the data amount value input from 306, and the data subjected to the data amount reduction processing is output to the output terminal 1310. As a result, the data output from the output terminal 1310 is recorded as TPH data or TPL data at an appropriate position on the tape recording medium.

As described above, according to the video signal processing apparatus of the eighth embodiment, the I picture extracting unit 1302, the memory 1303, the data amount reducing unit 1304, the memory control unit 1305, the data amount selecting unit 1306, and the timing signal By providing a generating unit 1307, the memory 1303 holds I-picture data instead of the data subjected to the reduction processing, and outputs the data subjected to the reduction processing by the data amount reduction unit 1304. As in the video signal processing apparatus of the seventh embodiment, by performing reduction processing suitable for each piece of high-speed reproduction data for which a different image quality is desired, and by being able to input a data amount value at any time, data The amount of reduction is variable, and it is possible to adjust the reproduction image quality of each high-speed reproduction data, Although interference control becomes complicated, it is capable of downsizing the circuit scale than the apparatus of the seventh embodiment.

In the video signal processing apparatus according to the eighth embodiment, the data amount reducing unit 1304 performs the same operation as the video signal processing apparatus according to any of the first to fourth embodiments, similarly to the video signal processing apparatuses according to the fifth to seventh embodiments. It can have the same internal configuration as the signal processing device.

The video signal processing apparatus according to the eighth embodiment includes a first data amount input terminal 1308 and a second data amount input terminal 1309, and can input a data amount value at any time. However, if it is not necessary to adjust the image quality during the processing, these input terminals are not provided, and the data amount selecting unit 1306 sets the TPH in advance.
It is assumed that the data amount reduction unit 1304 performs the data amount reduction process in accordance with the setting as in the video signal processing device according to the sixth embodiment by instructing the data reduction amount set for the TPL or for the TPL. It is also possible.
In this case, as in the video signal processing device of the eighth embodiment, the circuit scale can be reduced as compared with the video signal processing device of the sixth embodiment.

[0147]

According to the video signal processing apparatus of the first aspect,
A video signal processing apparatus for processing encoded data obtained by compressing and encoding a digitized video signal, comprising a specific component removing means for removing a specific component from the encoded data, It is possible to reduce the amount of encoded data by removing components that have little effect on image quality.

According to the video signal processing apparatus of the second aspect, in the apparatus of the first aspect, the encoded data to be processed is variable-length coded data, and the specific component removing means includes: By removing high-frequency components included in the variable-length encoded data as the specific components, components having little effect on the reproduction image quality in the variable-length encoded data are removed, and the variable-length code is removed. It is possible to reduce the data amount of the coded data.

According to the video signal processing apparatus of claim 3, in the apparatus of claim 2, the specific component removing means performs a variable length decoding process on the variable length coded data. A decoding unit, an inverse quantization unit that performs an inverse quantization process using a first quantization matrix on a processing result of the variable length decoding unit, and an inverse quantization unit that performs processing on the processing result of the inverse quantization unit. And a variable-length coding unit for performing a variable-length coding process on the processing result of the quantization unit using a second quantization matrix. This reduces the amount of variable-length coded data by eliminating components that have little effect on playback image quality in variable-length coded data without performing digital-to-analog conversion that would increase the circuit scale. Can It is capable flexibly make settings in the removal process.

According to the video signal processing apparatus of claim 4, in the apparatus of claim 2, the specific component removing means performs variable length decoding on the variable length coded data. Decoding means, decoding result processing means for performing a process of changing the value of a specific part constituting the processing result with respect to the processing result of the variable length decoding means, The processing result is provided with a variable-length encoding means for performing variable-length encoding processing, so that variable-length encoding can be performed without performing digital-to-analog conversion processing that causes an increase in circuit scale. By removing components having little effect on the reproduction image quality in the data, the data amount of the variable-length coded data can be reduced, and the circuit scale can be made smaller than the device of the fourth aspect.

According to the video signal processing device of the fifth aspect, in the device of the second aspect, the specific component removing means converts the variable-length coded data into the variable-length coded data. Code characteristic detecting means for detecting the characteristic of the variable length code to be constituted; and removing a specific code included in the variable length encoded data based on the characteristic of the variable length code detected by the code characteristic detecting means. With the provision of the specific code removing means, it is possible to remove components having little effect on the reproduction image quality in the variable-length coded data without performing digital-to-analog conversion processing which causes an increase in circuit scale. The data amount of the variable-length coded data can be reduced, and the circuit scale can be reduced more than the device of the fifth aspect.

According to the video signal processing device of claim 6, in the device of claim 5, the specific component removing means reads the code length of a variable length code constituting the variable length coded data. Readout processing, code length summation processing for accumulating code lengths read out in the variable length code length readout processing to obtain a code length summation, and setting the code length sum obtained in the code length summation processing in advance. The specified variable length code by performing a variable length code output process of outputting a variable length code having a code length not exceeding the threshold value according to the result of the comparison. By removing it, the data amount is reduced so that it has a code length within a predetermined code length, so it is required that the data amount be kept within the set value. It is possible to perform appropriate processing in the case.

According to the video signal processing device of claim 7, in the device of claim 5, the specific component removing means obtains the number of unit data included in the variable length code constituting the variable length coded data. The number of unit data obtained in the above-mentioned number-of-units acquisition process, the unit-data-number-sum calculation process of cumulatively adding the number of unit data obtained in the above-mentioned number-of-units acquisition process, and the unit data obtained in the above-mentioned unit-data-number-sum calculation process Performing a variable-length code output process of outputting a variable-length code having a unit data number not exceeding the threshold value according to a result of the comparison by comparing the total number with a preset threshold value. By removing the specific variable length code, the data amount is reduced so that the unit data (DCT coefficient) number is within a predetermined number. Less playback quality distortion can be appropriately processed when the requested.

According to the video signal processing apparatus of claim 8, in the apparatus of claim 2, the specific component removing means generates a digital video signal from the variable length coded data. A digital video signal generated by the digital video signal generating means, a specific digital signal removing means for removing a specific part of the digital video signal, and a variable Variable length coded data generating means for generating long coded data, quantization matrix holding for holding a quantization matrix used for processing in the digital video signal generating means, and processing in the variable length coded data generating means Means between digital and analog, which increases the circuit scale. A component that has little effect on the reproduction image quality in the variable-length coded data can be removed without performing the conversion process, and the data amount of the variable-length coded data can be reduced, and the setting can be performed more flexibly than the apparatus of claim 1. It becomes possible.

According to the video signal processing apparatus of the ninth aspect, in the apparatus of the first aspect, the coded data to be processed is data that has been subjected to intra-frame coding and inter-frame coding. The component removing means removes, as the specific component, a high-frequency component contained in the intra-frame encoded data in the encoded data, so that the reproduction image quality in the intra-frame encoded data is reduced. It is possible to reduce a data amount of the data by removing a component having little influence on the data.

According to the video signal processing device of the tenth aspect,
10. The apparatus according to claim 9, wherein the intra-frame coded portion extracting means for extracting intra-frame coded data from the coded data to be processed, a data holding means for temporarily holding data, and the data holding means. Read instruction signal generating means for generating a signal for instructing a read timing for the held data, and reading of the data held in the data holding means based on the signal generated by the read instruction signal generating means And a data readout control unit for controlling the data readout, so that the data amount can be reduced, and it is possible to generate data that can be appropriately recorded outside the device in accordance with the readout timing.

According to the video signal processing apparatus of claim 11,
The apparatus according to claim 10, wherein the specific component removing unit includes:
The specific component is removed from the processing result of the intra-frame coded part extracting means, and the data holding means holds the processing result of the specific component removing means. The effect is obtained.

According to the video signal processing apparatus of claim 12,
The apparatus according to claim 11, wherein the specific component removing unit includes:
A first specific component removing unit that removes the specific component based on a first characteristic value from a processing result of the intra-frame encoded part extracting unit; and a processing result of the intra-frame encoded part extracting unit. And a second specific component removing unit that removes the specific component based on a second characteristic value. The data holding unit stores a processing result of the first specific component removing unit. And a second data holding unit for holding a processing result of the second specific component removing unit. The data read control unit includes a first data holding unit for holding the first data. A first data read control unit that controls reading from the holding unit; and a second data read control unit that controls reading from the second data holding unit. In the degree of reduction of the amount of data it is possible to generate the two different data.

According to the video signal processing apparatus of claim 13,
11. The apparatus according to claim 10, wherein the data holding unit holds a processing result of the intra-frame coded part extracting unit, and the specific component removing unit performs processing on the data held by the data holding unit. The above effects can be obtained by removing the specific component.

According to the video signal processing apparatus of claim 14,
14. The apparatus according to claim 13, further comprising a removal characteristic determining unit that determines a characteristic value used for removing the specific component in the specific component removing unit, wherein the specific component removing unit includes:
Since the specific component is removed based on the characteristic value determined by the removal characteristic determining unit, it is possible to generate data with different degrees of reduction in the data amount.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a video signal processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a video signal processing device according to a third embodiment of the present invention.

FIG. 4 is a diagram for explaining data reduction processing in the video signal processing device according to the embodiment;

FIG. 5 is a diagram showing an AC included in the video signal processing apparatus according to the embodiment;
It is a flowchart figure which shows the processing procedure in the 1st mode of a component reduction means.

FIG. 6 shows an AC included in the video signal processing apparatus according to the embodiment.
It is a flowchart figure which shows the processing procedure in the 2nd mode of a component reduction means.

FIG. 7 illustrates an AC included in the video signal processing device according to the embodiment;
It is a flowchart figure which shows the processing procedure when a component reduction means switches a mode and performs a process.

FIG. 8 is a block diagram illustrating a configuration of a video signal processing device according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a video signal processing device according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram illustrating an internal configuration of a data amount reducing unit included in the video signal processing device according to the embodiment.

FIG. 11 is a block diagram showing a configuration of a video signal processing device according to a sixth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a video signal processing device according to a seventh embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a video signal processing device according to an eighth embodiment of the present invention.

FIG. 14 is a diagram for explaining a recording format of data for special reproduction on a tape recording medium.

FIG. 15 is a diagram for explaining a header section in a recording format of special reproduction data on a tape recording medium.

[Explanation of symbols]

101,201,301,801,901,1101,
1201, 1301 input terminals 108, 205, 304, 810, 907, 1110,
1210, 1310 output terminals 102, 202, 802, 1002 VLD means 103, 803, 1003 Inverse quantization means 104 First quantization matrix means 106 Second quantization matrix means 808, 1008 Quantization matrix means 105, 807, 1007 Quantization means 107, 204, 809, 1009 VLC means 203, 303 AC component reduction means 805, 1005 Filter means 302 Code length analysis means 902, 1102, 1202, 1302 I picture extraction means 903, 1304 Data amount reduction means 1103, 1203 First Data amount reducing means 1105, 1205 second data amount reducing means 904, 1104 memory 1104, 1204 first memory 1106, 1206 second memory 906, 1305 memory control means 1108 , 1208 First memory control means 1109, 1209 Second memory control means 905, 1107, 1207, 1307 Timing signal generation means 1306 Data amount selection means

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kuji Murata 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (14)

[Claims] 1. A video signal processing apparatus for processing encoded data obtained by compressing and encoding a digitized video signal, comprising a specific component removing means for removing a specific component in the encoded data. A video signal processing device. 2. The video signal processing apparatus according to claim 1, wherein the coded data to be processed is a variable-length coded data, and the specific component removing unit performs the variable-length coded data. A video signal processing device for removing a high-frequency component included in data obtained as the specific component. 3. The video signal processing device according to claim 2, wherein the specific component removing unit performs a variable length decoding process on the variable length coded data; The processing result of the variable length decoding means is
An inverse quantization means for performing an inverse quantization process using the quantization matrix of, a quantization means for performing a quantization process on the processing result in the inverse quantization means using a second quantization matrix, A video signal processing apparatus comprising: a variable-length encoding unit that performs a variable-length encoding process on the processing result of the quantization unit. 4. The video signal processing device according to claim 2, wherein the specific component removing unit performs a variable length decoding process on the variable length coded data; A decoding result processing unit that performs a process of changing a value of a specific part constituting the processing result with respect to a processing result obtained by the variable length decoding unit; And a variable-length encoding unit for performing a variable-length encoding process. 5. The video signal processing device according to claim 2, wherein the specific component removing unit is configured to generate a variable length code for the variable length coded data with respect to the variable length coded data. Code characteristic detecting means for detecting the characteristic of the variable length code detected by the code characteristic detecting means, and a specific code removal for removing a specific variable length code included in the variable length encoded data. A video signal processing apparatus comprising: 6. The video signal processing device according to claim 5, wherein the specific component removing unit reads out a code length of a variable length code constituting the variable length encoded data; A code length summation process for accumulating code lengths read out in the variable length code length readout process to obtain a code length summation, and a code length sum acquired in the code length summation process and a preset threshold value And performing a variable-length code output process of outputting a variable-length code having a code length not exceeding the threshold value according to a result of the comparison, thereby removing the specific variable-length code. A video signal processing device characterized by the above-mentioned. 7. The video signal processing apparatus according to claim 5, wherein the specific component removing unit obtains a number of unit data included in a variable length code included in the variable length coded data; The total number of unit data obtained by cumulatively adding the number of unit data obtained in the above number obtaining process to obtain the total number of unit data, and the total number of unit data obtained in the above total number of unit data calculation process are set in advance. And performing a variable-length code output process of outputting a variable-length code having a unit data number that does not exceed the threshold according to the result of the comparison. A video signal processing device for removing a video signal. 8. The video signal processing device according to claim 2, wherein the specific component removing unit includes: a digital video signal generating unit configured to generate a digital video signal from the variable length encoded data; A specific digital signal removing means for removing a specific part constituting the digital video signal from the digital video signal generated by the signal generating means; and a variable length coded data from the processing result of the specific digital signal removing means. Variable length coded data generating means for generating; and a quantization matrix holding means for holding a quantization matrix used for processing in the digital video signal generating means and processing in the variable length coded data generating means. A video signal processing device. 9. The video signal processing apparatus according to claim 1, wherein the coded data to be processed is data obtained by intra-frame coding and inter-frame coding. A video signal processing device for removing a high-frequency component contained in intra-frame encoded data in the encoded data as the specific component. 10. The video signal processing apparatus according to claim 9, wherein an intra-frame encoded portion extracting means for extracting intra-frame encoded data from the encoded data to be processed, and data for temporarily storing data. Holding means; read instruction signal generating means for generating a signal for instructing read timing for data held in the data holding means; and the data based on a signal generated by the read instruction signal generating means. A video signal processing device, further comprising: data read control means for controlling reading of data held in the holding means. 11. The video signal processing device according to claim 10, wherein the specific component removing unit removes the specific component from a processing result of the intra-frame coded part extracting unit. The video signal processing device, wherein the data holding means holds the processing result of the specific component removing means. 12. The video signal processing apparatus according to claim 11, wherein the specific component removing unit is configured to determine the processing result of the intra-frame coded part extracting unit based on a first characteristic value based on a first characteristic value. And a second specific component removing unit that removes the specific component based on a second characteristic value with respect to the processing result of the intra-frame encoded part extracting unit. Wherein the data holding means includes a first data holding means for holding a processing result in the first specific component removing means, and a second data holding means for holding a processing result in the second specific component removing means. 2 data holding means, wherein the data reading control means comprises: first data reading control means for controlling reading from the first data holding means; and A video data processing device comprising: a second data read control unit that controls reading from the data holding unit. 13. The video signal processing device according to claim 10, wherein said data holding means holds a processing result of said intra-frame coded part extracting means, and said specific component removing means holds said data. A video signal processing apparatus for removing the specific component from data held by a holding unit. 14. The video signal processing device according to claim 13, further comprising: a removal characteristic determination unit that determines a characteristic value used for removal of the specific component in the specific component removal unit. A video signal processing apparatus for removing the specific component based on the characteristic value determined by the removal characteristic determining means.