JPH11330929A - Circuit and method for controlling switching speed of inverter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the switching speed of the inverter 12 and to hold its switching threshold value nearly constant. SOLUTION: An FET 11a charges the output capacitor 16 of the inverter 12 and an FET 11b discharges this output capacitor. An FET 18a limits the discharging current to a 1st specific level on receiving a 1st control signal at its gate and an FET 18b limits the discharging current to a 2nd specific level on receiving a 2nd control signal at its gate. Those 1st and 2nd specific levels are nearly equal in the control range of the current and the switching threshold values of the FETs 11a and 11b are held almost constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a delay circuit used for timing interpolation, and more particularly to a circuit and a method for controlling the switching speed of a CMOS inverter used for such a delay circuit.

[0002]

BACKGROUND OF THE INVENTION In electronic devices, it is often desirable to control the delay. The controlled delay is
There are many advantages, such as obtaining a timing resolution that can be controlled by the system clock, which is useful. For example, an event driven timing analyzer generates a predetermined signal at a selected time. If the selected point occurs during a clock cycle, the clock period must be interpolated. Such interpolation can be performed properly in a delay line having a delay locked to the clock period. (Note that in this specification, a circuit using an actual delay line, a delay circuit including a circuit element such as an amplifying element that functions as a delay line, and the like are collectively referred to as a delay line.) A tap is provided at a selected location to generate an output signal at a time delayed from the last clock pulse by a desired division of the clock period.

In order to lock a delay to a clock, a ring oscillator constituted by an inverter (phase inverter) is adjusted to oscillate at the frequency of a clock signal supplied from the outside. The control mechanism used to vary the frequency of the ring oscillator is used to vary the delay of a timing interpolator composed of cascaded inverters. U.S. Pat. No. 5,576,657 to Fristi (corresponding to JP-A-7-191095) describes this type of timing interpolator. Another example of a phase locked delay line is described in U.S. Pat.
No. 141 (hereinafter referred to as 141 patent).

To perform the function of timing interpolation, the individual delay elements are "tapped" (tapping from each of the cascaded delay elements) to provide a fraction of the total delay of the delay line. Do a delay. All of the delays of these delay elements must be equal and provide a delay corresponding to an exact submultiple of the total delay. That is, if the delays of all delay elements are equal, the delay at a particular delay element will be part of the total delay. The portion of the delay corresponds to the ratio of the number of delay elements up to that particular delay element to the total number of delay elements in the delay line, ie, a fraction.

[0005]

The delay line is a CMO.
An S (Complementary Metal-Oxide Semiconductor) inverter may be used. These CMOS inverters repeat an operation of sending (sourcing) current to an output node capacitance (output capacitance) and an operation of drawing (sinking) current from the node capacitance. The output capacity is
Even if a capacitor as an element is not connected, it is inevitably present at the output node of each inverter as stray capacitance. These inverters receive power via power supply lines + V and -V. As the voltage on the power supply line decreases, the peak current that the inverter sends or draws decreases, the rate at which the output node capacitance is charged decreases, and the propagation delay time of the inverter increases. Therefore, when the voltage of the power supply line is reduced, the switching speed of the inverter is controllably reduced to perform a desired function.

However, simply lowering the effective power supply line voltage of the inverters shifts the switching thresholds of these inverters. This has a particularly undesirable effect on the timing interpolator. Here, other logic devices that are not voltage controlled have switching thresholds that are not shifted, but there is a general "switching skew" between signals at the interface between the voltage controlled inverter and the uncontrolled logic device. Due to the switching skew, the state of the inverter switches between before and after the logic element that pulls out the tap. Due to the effects of such switching skew, there is a problem that the exact divisor of the delay cannot be obtained from the delay line.

[0007] A method for partially remedying this problem is described in US Pat. No. 5,576,657 to Fristi (hereinafter referred to as 65).
7 patents). In the '657 patent, a circuit maintains the switching threshold at a predetermined value, such as VCC / 2, while allowing the power supply voltages + V and -V to drop from the maximum power supply voltage VCC. on the other hand,
The '141 patent uses similar concepts in different applications.

This improvement is partial, because the switching threshold of the inverter is artificially maintained at a predetermined level. There is no guarantee that the switching thresholds of uncontrolled logic elements will always be at the same predetermined level. Therefore, switching skew may remain.

Furthermore, this improvement is difficult to improve at low power voltages, high switching speeds, or both. The power supply voltage must be reduced for small gate dimensions to prevent breakdown between oxide gates. For example, a 3.3 volt power supply has been used instead of a 5 volt power supply for gate dimensions significantly less than about 65 microns. The switching threshold of the logic element must be lowered on the same basis. However, the same or large peak currents must be used to maintain the switching speed, or, if often desirable, to increase the switching speed. Large peak currents and low voltage thresholds significantly reduce (deteriorate) the signal-to-noise ratio in the inverter.

Thus, there is a need for an improved method and circuit for controlling the switching speed of a CMOS switching element and maintaining its switching threshold. This improved circuit must operate over a wide range of supply voltages. This wide range of supply voltages includes C with logic elements with very small gate dimensions.
A relatively low power supply voltage typically used in MOS logic circuits is also included. The improved circuit must provide such control, maximize the signal-to-noise ratio, minimize signal degradation, and reduce the likelihood of switching skew. With such an improved circuit, a delay is obtained that corresponds to an exact submultiple of the total delay of the delay line.

Accordingly, the present invention provides a switching speed control circuit and method for controlling the switching speed of an inverter and maintaining its switching threshold substantially constant.

[0012]

SUMMARY OF THE INVENTION An improved method and circuit of the present invention for controlling the switching speed of a CMOS inverter and maintaining its switching threshold is provided.
By providing a pair of current limiting elements outside the CMOS inverter pair, the above-mentioned problem is solved and the above-mentioned need is satisfied. Note that one of the pair of current limiting elements is connected in series with a first current sourcing transistor of the inverter, and the other current limiting element is connected in series with a complementary second current sourcing transistor of the inverter. These current limiting elements control the rate at which the first and second current delivery elements (transistors) of the inverter charge and discharge the node capacitance of the inverter to adjust the switching speed and propagation delay of the inverter. I do. By controlling these current-sourcing elements (transistors) so that the currents that they can output are the same selectable value, the "natural" switching of the inverter is determined by the dimensions of the elements and the processing parameters Prevent threshold changes. The accuracy of timing interpolation is improved because the original switching threshold is maintained, allowing the inverter to interface with other uncontrolled logic elements and preventing switching skew. It is important to note that the inverter "sees" the maximum voltage on the power supply line that is substantially independent of the selected switching speed. This function prevents the signal-to-noise ratio from further deteriorating. Without this feature, the signal-to-noise ratio would be degraded if the switching speed was reduced.

By switching the phase of a ring oscillator composed of a plurality of cascaded inverters to an external reference frequency, the switching speed of the inverter can be conveniently managed.

It is desirable to have a delay that exactly corresponds to a submultiple of the clock period, and the present invention is particularly useful when an inverter is used in a timing interpolator.

The above and other concepts, features and advantages of the present invention will be understood from the following detailed description, taken in conjunction with the accompanying drawings.

[0016]

FIG. 1 is a block diagram of one or more timing interpolators for calibrating delay with a ring oscillator in accordance with the present invention. In the figure, an FET (field effect transistor) with a circle added to the gate is a p-channel FET, and an FET with a vertical line added to the gate.
Is an n-channel FET, and a straight line passing through the gate of each FET indicates a connection line commonly connected to the gate. The ring oscillator 20 is used as a means for calibrating the delay of one or more timing interpolators 50. This ring oscillator includes a plurality of (N) delay elements 20 (j) each composed of four transistors (FETs).
Individual). In this specification, the delay element 20 (j) is also referred to as an inverter, because the inverter (phase inverter) also functions as a delay element. Note that i
Is an integer from 1 to N. Here, each delay element 2
0 (j) is the upper two p-channel FEs in the figure.
T and the lower two n-channel FETs are sequentially connected, a common input signal is supplied to the gates of the middle two FETs, and an inverted output signal is supplied from a commonly connected source of these two FETs. To generate a typical inverter. Using the phase and frequency error detector 2, the oscillation frequency of this ring oscillator is phase-locked to a reference frequency φref supplied from outside. The phase and frequency error detector 2 includes a phase gate that operates a charge pump to generate an error signal "e" proportional to both the phase error and the frequency error. The output of the charge pump is amplitude-processed and supplied to the ring oscillator as a voltage control signal “Vc”. This voltage control signal Vc is further processed to obtain two control signals Vcp and Vc.
generate n. These two control signals are passed to the delay element 20
(J) to the outer p-channel and n-channel control elements (FETs), as described below.
In addition to controlling the propagation delay time of (j), the frequency is locked to the reference frequency φref. In addition, between the phase and frequency error detector 2 and the ring oscillator 20,
A comparator 60 that compares the error signal “e” with a reference voltage Vref, and receives a control signal V
A mirror circuit 24 for generating cp and Vcn is coupled. This mirror circuit 24 will also be described later with reference to FIG.

[0017] Ring oscillators are well known in the art. The ring oscillator comprises an odd number of inverting stages (inverters), but may include any number of non-inverting stages, for example, to provide buffering and additional delay. The inverters are connected in a chain (connected like a continuous loop), so that each input node of each inverter is connected to the output node of the preceding inverter, and each output node of each inverter is connected to the next inverter. Connected to the input node. Therefore, a state where the delay elements 20 (j) as a plurality of inverters are sequentially coupled in the ring oscillator 20 is indicated by a dotted line, and a state where the output terminal 21 of the ring oscillator 20 is coupled to the input terminal is indicated by a solid line. , And a chain-like connection is performed. The output 21 of the ring oscillator 20 is obtained from one output node of the inverter. The odd number of inverters in the ring oscillator can delay the oscillation frequency by half the period Tref. Note that Tref = 1 / φref. Therefore, as an oscillation condition, the sum of the delays of the individual inverters becomes one half of the delay, and
The cycle is 360 degrees of delay. That is, Tref / 2 + N × (propagation delay time of each inverter) =
Tref. Therefore, the propagation delay time of each inverter is Tr
ef / 2N. Control signals Vcp and V
cn is automatically adjusted to provide an accurate propagation delay.

To lock the ring oscillator 20 to the reference frequency φref, first, the phase and frequency error detector 2 generates an error signal “e”. The error signal “e” is proportional to a frequency error between the reference frequency φref and the oscillation frequency of the ring oscillator 20. If this frequency error is small, this error signal “e” is proportional to the phase error between the output 21 of the ring oscillator 20 and the reference frequency φref. In the locked state, the error signal “e” indicates that the reference frequency φref and the ring oscillator 20
Is a DC voltage representing a small steady state phase difference with the output signal of

The timing interpolator 50 controls the delay element 20
It includes a delay element 120 (j) configured similarly to (j). Note that j is an integer from 1 to n. In the figure, a dotted line in the timing interpolator 50 indicates that a plurality of delay elements (inverters) 120 (j) are
(J), but the chain is not closed (that is, the output terminal of the last inverter does not return to the input terminal of the first-stage inverter), and the control signals Vcp and Vcn are output from each inverter. Are supplied in common. The propagation delay of delay element 120 (j) is determined by controlling signals Vcp and Vcp.
cn, the delay element 1
The delay of each of 20 (j) is the same as Tref / 2N. The input signal “In” is supplied to the timing interpolator 50, and the delayed output signal is supplied to each delay element (inverter) 1
A delay (j / n) × Tref / 2 extracted from the output terminal “Out (j)” of 20 (j) via a tap and quantized.
Achieve N.

In the prior art, in order to adjust the switching speed of a typical CMOS inverter pair, the voltage supplied between the p-channel element and the n-channel element constituting the inverter pair is set to the maximum voltage of the power supply voltage supply line. The difference was adjusted from the difference to a smaller value. To facilitate understanding of the present invention, the prior art will be further described with reference to FIG. FIG. 2 shows a p-channel device and an n-channel device.
A conventional configuration 4 for controlling the switching speed of a delay element formed by a CMOS inverter having a channel element is shown. A model or dummy inverter 8 is used and its input Vi is combined with its output Vo. Variable voltages + V and -V are generated from the first differential amplifier 7 and the second differential amplifier 9, respectively, and are supplied to other inverters (not shown). The first differential amplifier 7 generates + V equal to the desired voltage Vin. The second differential amplifier 9 drives the element 8b so that the output of the inverter element 8 is always equal to the reference voltage Vref. This reference voltage Vref is equal to the assumed switching threshold of the inverter, for example 5
Preset to 2.5 volts for volt logic. Thus, the voltage on the voltage line is reduced from the maximum voltage to the value required to maintain the switching threshold at the preset level.

However, this reduction in voltage results in poor (lowered) signal-to-noise ratios of components, especially at high switching speeds and low supply voltages. Further, techniques for fixing the threshold voltage of a controlled inverter result in switching skew between controlled and uncontrolled logic elements in the same circuit. As a result,
The ability of the tapped ring oscillator to provide an exact submultiple of the entire period of oscillation is compromised.

FIG. 3 is a circuit diagram of a CMOS inverter including a current limiting element according to the present invention. Note that CMOS
The inverter 12 and the mirror circuit 24 correspond to the delay element (inverter) 20 (j) and the mirror circuit 24 in the ring oscillator 20 in FIG. 1, respectively, but the connection with the comparator 60 in FIG. 1 is omitted. Although the arrangement of the ring oscillator 20 and the mirror circuit 24 on the drawing is different, it should be noted that they are electrically the same. The circuit 10 according to the invention
Controlling the switching speed of the CMOS inverter 12;
Maintain that switching threshold. This circuit is particularly advantageous when the switching speed and the resulting noise current are relatively large, or when obtaining a perfect submultiple of the entire time interval as provided by a ring oscillator phase locked to a reference frequency. . CMOS inverter 1
It will be appreciated that the symmetry of the two is well known and, for example, that the carrier types and voltage level polarities described herein may be interchanged without departing from the principles of the present invention.

Inverter 12 typically includes a plurality of elements for sending current to node capacitance (output capacitance) 16. One end of the node capacitance 16 is connected between the plurality of elements, and the other end is grounded. Typically, p
The channel MOS current sending element 11a supplies a charging current (first current) to the capacitor 16 in the active state, and
The channel MOS current sending element 11b supplies (pulls in) a discharge current (second current) to the capacitor 16 in the active state.

In general, the switching speed of the inverter 12 depends on the rate at which the capacitor 16 is charged and discharged. The capacitor 16 is charged by a sending (source) current from the upper power supply line VDD via the element 11a, and is discharged by a drawing (sink) current from the lower power supply line VSS via the element 11b.

According to the present invention, the current limiting elements 18a, 1
A complementary pair of 8b is provided between the elements 11a, 11b and the upper and lower power supply lines, respectively. That is, the current limiting element 1
8a is coupled between the p-channel element 11a and the power supply line VDD, and the current limiting element 18b is connected to the n-channel element 1
1b and the power supply line VSS. The delay element 20 composed of four transistors (FETs) includes a current sending element 11a, 11b and a current limiting element 18a, 18
b. FIG. 1 is referred to again. A plurality of delay elements consisting of four transistors are connected to a ring oscillator 2
Used as element 20 (i) of 0. Note that each stage of the ring oscillator may include a non-inverting element (ie, a buffer). These non-inverting elements are not shown for clarity because they are not required for the present invention.

The current limiting elements 18a, 18b are activated when the associated current delivery elements 11a, 11b are short-circuited.
A selectable current “Ic” can be passed. Therefore, the current “Ic” is supplied to the current sending elements 11 a and 11
b is the maximum current that can pass. The current “Ic” has the same magnitude as the limited current (predetermined level) in the current limiting elements 18a and 18b. In this state, it can be recognized that the directions in which the charge (discharge) carriers of the n-channel element and the p-channel element flow are symmetric.

The current limiting elements 18a, 18b are preferably MOS transistors, and in this embodiment, p and n
It is a channel transistor. Gates (control input terminals) 22a, 22 of these transistors of the current limiting element
b is selectively maintained at a corresponding voltage, respectively, and supplies a current "Ic" from the source to the drain of the p-channel current limiting circuit 18a and from the drain to the source of the n-channel current limiting element 18b, respectively.

The current mirror circuit 24 includes gates 22a, 2a
2b is selectively maintained. This current mirror circuit includes a diode-connected p-channel MOS transistor 26. Gate 26 of transistor 26
a is also connected to the gate of element 18a and the drain 26b of transistor 26. In contrast, the mirror circuit 24 is a diode-connected n-channel MOS.
A transistor 28 is also included. This transistor 28
Is coupled to gate 22b of element 18b and drain 28b of transistor 28. The mirror circuit 24 includes a reflection (reflection) transistor 30.
The gate 30a of the transistor is coupled to the gate 26a of the transistor 26 and the drain 30
b is coupled to the drain 28b of transistor 28.
The reflection transistor 30 reflects (reflects) the current of the transistor 26 on the transistor 28.

The drain 26b of transistor 26 can be coupled to a controlled current source "CSS" to provide a current "Ic" in response to a phase / frequency error signal generated by phase and frequency error detector 2. To do. Suitable phase and frequency error detectors are well known, for example, in US Pat. No. 3,610,954 to Treadway, "Phase Comparator Using Logic Gates." The phase and frequency error detector of this patent produces an output signal in response to a trailing edge of the input waveform. This output signal is related to the input repetition rate and relative phase. The duty cycle of the input waveform is not important. This is because the circuit responds only to the trailing edge transition of the input waveform. Thus, the phase and frequency detectors of the aforementioned U.S. patents are not sensitive to variations in duty cycle.

A delay element 20 consisting of four transistors
Each of (i) has a current limiting element 18a coupled to the gate 26a of transistor 26. Current limiting element 1
8b is connected to the gate 28 of the transistor 28.
a. Therefore, the current is equal to all delay elements 2
Through 0 (i), a mirror image (mirror) relationship is established.

The current flowing through the inverter 12 is limited by each of the current limiting elements 18a and 18b and always has substantially the same magnitude. Therefore, it can be understood that the switching threshold of the inverter 12 does not change regardless of the value of the current “Ic”. It has been found that the circuit described above allows the delay of the inverter to be controlled over a range of over 100: 1 without switching skew.

One example of an advantage of the present invention is that, for example, a phase locked loop can be used to control the ring oscillator of the inverter of the present invention to oscillate at a reference frequency, thereby delaying other chains of the inverter. Can be generated to function as a precise variable active delay line or timing interpolator. Further, the output signal from this can interface standard logic without timing skew.

Although a particular method and circuit for controlling the switching speed of a CMOS inverter and maintaining its switching threshold has been described as a preferred embodiment, it should be understood that other configurations than those described above may be used without departing from the spirit of the invention. It will be appreciated that other configurations can be used.

The terms and expressions used in the above description are for explanation, and do not limit the present invention. Such terms and expressions do not exclude equivalents to the illustrated or described functions or portions thereof. Therefore, the gist of the present invention is determined by the appended claims.

[0035]

As described above, according to the present invention, the switching speed of the inverter can be controlled, and the switching threshold can be maintained substantially constant.

[Brief description of the drawings]

FIG. 1 is a block diagram of one or more timing interpolators for calibrating delay with a ring oscillator in accordance with the present invention.

FIG. 2 is a block diagram of a conventional CMOS inverter applied to keep a switching threshold of another control inverter constant during an adjustment period of a power supply voltage.

FIG. 3 is a circuit diagram of a CMOS inverter including a current limiting element according to the present invention.

[Explanation of symbols]

 2 Phase and frequency error detector 11a, 11b Current sending element 12 Inverter (delay element) 16 Output capacity 18a, 18b Current limiting element 20 Ring oscillator 20 (j) Inverter (delay element) 24 Mirror circuit 50 Timing interpolator 120 (j Inverter (delay element)

Claims (3)

[Claims] A circuit for controlling a switching speed of an inverter, comprising: an output capacitor coupled to the inverter; and a first current coupled to the output capacitor to charge the output capacitor in an active state. A first current delivery element to generate; a second current delivery element coupled to the output capacitance for generating a second current that discharges the output capacitance in an active state; and a control input receiving a first control signal. A first current limiting element coupled between a first power supply and the first current sending element for limiting the first current to a first predetermined level in response to the first control signal; A second current limiting element coupled between a second power supply and the second current delivery element for limiting the second current to a second predetermined level in response to the second control signal; With Over a predetermined range of controlled current, the magnitude of the first predetermined level is substantially equal to the magnitude of the second predetermined level, and the switching thresholds of the first and second current delivery elements are maintained substantially constant. A switching speed control circuit for an inverter. 2. A control current coupled to said control inputs of said first and second current limiting elements, said control current being applied to said first current limiting element at said first predetermined level when said first current delivery element is active. Generating the second current limiting element when the second current sending element is active.
The circuit of claim 1 further comprising a current mirror circuit for generating a control current at a predetermined level. 3. A method for controlling a switching speed of an inverter, comprising: generating a first current for charging a capacity when a first current sending element is active; Generating a second current for discharging the capacitance, limiting the first current to a first predetermined level when the first current sending element is active, and controlling when the second current sending element is active; Over a predetermined range of the applied current, the second predetermined level having a magnitude substantially equal to the magnitude of the first predetermined level.
A switching speed control method for an inverter, comprising: limiting a current; and maintaining each switching threshold of the first and second current sending elements at a substantially constant level.