JPH11328978A - Drive circuit for non-volatile ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify constitution by arranging first and second signal lines for selecting a first cell array section and third and fourth signal lines for selecting a second cell array section between these two cell arrays, and by connecting a first split word line drive signal output section to first and third signal lines and a second split word line drive signal output section to second and fourth signal lines. SOLUTION: The respective signal lines 100, 100a, 111, 111a are connected respectively to the common gates of PMOS transistors and NMOS transistors of the respective split word line drive signal output sections 112, 113. When the output signal of an X address signal generating section 114, which decodes and outputs X1, X2 address signals in the low state of the PS1 signal and PS2 signal impressed via the first and second signal lines 100, 100a, turns to an active state, the first and second split word line drive signal output section 112, 113 which are the first among plural pairs of the drive signal output sections are activated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory, and more particularly, to a driving circuit for a nonvolatile ferroelectric memory device.

[0002]

2. Description of the Related Art Generally, a ferroelectric memory (FRA) having a data processing speed comparable to that of a DRAM often used as a semiconductor memory device and storing data even when a power supply is turned off.
M) has attracted attention as a next-generation storage device. FRRA
M uses a capacitor as a storage element, similar to a DRAM, but uses a ferroelectric as a dielectric material of the capacitor and removes an electric field by using a high remanent polarization, which is a ferroelectric characteristic, to remove data. This is a storage device that is not lost.

FIG. 1A is a characteristic diagram showing a hysteresis loop of a general ferroelectric, and FIG. 1B is a configuration diagram of a unit capacitor of a general ferroelectric memory. That is, FIG.
As shown in the hysteresis loop of a, the polarization induced by the electric field is maintained by a certain amount (d, a state) without disappearing due to the existence of spontaneous polarization even when the electric field is removed. The d and a states corresponded to 1 and 0, respectively, and were applied as storage elements.

A state in which a positive (+) voltage is applied to the node 1 in FIG. 1B is a state c in FIG. 1A, and a state in which no voltage is applied thereafter is a state d. Conversely, when a negative (-) voltage is applied to the node 1, the node moves from the d state to the f state. If a voltage is not applied to the node 1, the state becomes the state a, and the node 1
When a positive voltage is applied to, the state changes to the c state via the b state. After all, even if there is no voltage across the capacitor, data is stored in a stable state of a and d. On the hysteresis loop, states c and d are states of logical value “1”, and states a and f are states of logical value “0”.

[0005] As a method of reading data stored in the capacitor, a method of destroying the d state is used.
The prior art uses a sense amplifier for determining data using a voltage generated by a reference voltage generator and a voltage generated by a main cell array. In a ferroelectric reference cell, a reference voltage is generated on a reference bit line using two mode states of one polarity and zero polarity. The sense amplifier compares the bit line voltage of the main cell with the bit line voltage of the reference cell, so that information of the main cell can be read. The read data must be rewritten in the same cycle to recover the corrupted data. In particular, the related art includes a sense amplifier circuit technology related to a plurality of ferroelectric cells for supplying a reference voltage, a sense amplifier that senses and amplifies data stored in a main cell in a main memory cell array, and a main cell array circuit. Technology is important. Although the number of the plurality of ferroelectric reference cells is an even number, half is in the one polarity state and half is in the zero polarity state.

Hereinafter, a conventional ferroelectric memory device will be described with reference to the accompanying drawings. FIG. 2 is a diagram showing a cell array configuration of a conventional ferroelectric memory. The configuration of a conventional ferroelectric memory cell will be described with an example in which a unit cell includes two transistors and two capacitors.
That is, a plurality of word lines W / L are formed in one direction at regular intervals, and a plurality of plate lines (P / L) are arranged between the word lines (W / L) in parallel with the word lines (W / L). ) Is formed. A plurality of bit lines (B_n, B_n + 1,...) Are arranged at regular intervals in a direction perpendicular to each word line (W / L) and plate line (P / L).
.) And bit bar lines (BB_n, BB_n + 1...)
・) Are alternately formed. Then, the unit memory cell 1
Are connected in common to one word line (W / L), and the source electrode of each transistor has an adjacent bit line (B_n) and a bit bar line (BB_n). ), The drain electrodes of the transistors are respectively connected to the first electrodes of two capacitors, and the second electrodes of the two capacitors are connected to an adjacent plate line (P / L).
Is commonly linked to Note that the unit cell does not mean a storage unit, but means a unit formed together in manufacturing. It may also be a storage unit depending on how it is used.

Next, the driving circuit and operation of the conventional ferroelectric memory cell will be described. Conventional ferroelectric memory cells write and read logic values "1" or "0" as follows. That is, as shown in FIG.
In the write mode, an external chip enable signal C
SBpad changes from “high” to “low” and is enabled, and the write enable signal WEBpad is enabled.
Is transitioned from “high” to “low”. At the same time,
“High” and “low” or “low” and “high” signals are applied to the bit line and the bit bar line, respectively, based on a logic value to be written. And
When the decoding of the address starts, a "high" signal is applied to the word line of the selected cell to select the cell. While the word line is maintained at "high", a "high" signal for a certain period and a "low" signal for a certain period are sequentially applied to the corresponding plate line (P / L). That is, a "high" signal is applied to the bit line (B_n) to write a logic value "1", and a "low" signal is applied to the bit bar line (BB_n). A “low” signal may be applied to (B_n) and a “high” signal may be applied to the bit bar line (BB_n). The logic value “1” or “0” is written by such a method. When a bit line and a bit barrant are formed in this way, a state where “1” is stored in the capacitor connected to the bit line and “0” is stored in the capacitor connected to the bit bar line is a logic “1”. In the opposite case, “0” is stored. In this example, the unit cell is a storage unit.

The operation for reading data stored in a cell will be described below. As shown in FIG.
SBpad is enabled from "high" to "low",
WEBpad has transitioned from "low" to "high". When the read mode starts, all bit lines are set to low V by an equalizer signal before the corresponding word line is selected.
The potential is made equal to ss. After completing the equipotential to low voltage,
Decode the address. The signal applied to the corresponding word line is changed from "low" to "high" according to the decoded address, and the corresponding cell is selected. A "high" signal is applied to the plate line of the selected cell to destroy data on the bit line or bit bar line.
That is, when the logic value “1” is recorded, the data of the capacitor connected to the bit line is destroyed, and when the logic value “0” is recorded, the data of the capacitor connected to the bit bar line is destroyed. Data is destroyed.

As described above, depending on which data of the bit line and the bit bar line is destroyed, different values are output according to the above-described hysteresis loop principle. Therefore, when the sense amplifier senses data output through the bit line and the bit bar line, it senses a logic value “1” or “0”. As described above, after the sense amplifier amplifies and outputs the data of the memory cell, the data must be restored to the original data.
The plate line is inactivated from “high” to “low” with the voltage applied.

[0010]

The conventional ferroelectric memory device has the following problems. Although there is an advantage that data is stored even when the power is turned off, in the conventional FRAM, the cell plate line must be separately configured, so that the layout is complicated and the manufacturing process is complicated. This is disadvantageous in terms of mass production. In order to use a separate plate line, a control signal must be supplied to the plate line when data is read or written. For this reason, the operation efficiency of the storage device decreases. The integration of the conventional ferroelectric memory cell cannot be solved unless a new electrode material and a barrier material are proposed. Another problem with integration aspects is that capacitors cannot be formed directly on a silicon substrate or polysilicon because techniques for forming ferroelectrics directly on the silicon surface are not yet sufficient. Therefore, the required area is larger than that of a DRAM having the same capacity. Since the word line and the cell plate line are controlled separately, it is difficult to control accurately due to a difference in a control signal transmission path.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional nonvolatile ferroelectric memory device, and has as its object to simplify the structure of a word line driving unit. Another object of the present invention is to provide a driving circuit of a nonvolatile ferroelectric memory device which can reduce a layout area.

[0012]

According to the present invention, a certain number of memory cells connected to a first split word line and a second split word line is formed as a block, and a certain number of memory cells are arranged in a horizontal direction. 1 cell array section,
This is a nonvolatile ferroelectric memory device including a local control signal generation unit that outputs a signal for selecting a second cell array unit similarly formed. First and second signal lines for transmitting a signal output from a local control signal generator for selecting a first cell array unit of the two cell array units, and a local signal line for selecting a second cell array unit. Third and fourth signal lines for transmitting a signal output from the control signal generator, a first split word line driving signal output unit connected to the first and third signal lines, respectively, and a second and fourth signal A second split word line driving signal output unit connected to each of the lines;
An X address signal output unit for outputting a control signal for activating any of the first and second split word line drive signal output units among the first and second split word line drive signal output units. And

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A drive circuit of a nonvolatile ferroelectric memory device according to an embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 4 is a diagram showing a basic configuration of a drive circuit of the nonvolatile ferroelectric memory device according to the present invention. That is, an X address buffer 11 for buffering an X address signal among X, Y, and Z addresses input from the outside, an X predecoder 12 for predecoding a signal output from the X address buffer 11, X, Y, Z
A Z address buffer 13 for buffering a Z address among addresses, a Z predecoder 14 for predecoding a signal output from the Z address buffer 13,
X, Z_ATD generation unit 15 that detects and outputs an address transition point of the X address and Z address signals output from X address buffer 11 and Z address buffer 13
And an output signal of the X, Z_ATD generation unit 15 and a CSBpad signal input from the outside, generate a power-up detection signal, and generate a memory according to the X, Z_ATD signal, the CSBpad signal, and the power-up detection signal. Global control signal generator 1 for outputting basic pulses related to control
6 and Y among X, Y and Z addresses inputted from outside
Y address buffer 17 for buffering addresses
A Y predecoder 18 for predecoding a signal output from the Y address buffer 17, a Y_ATD generation unit 19 for detecting and outputting an address transition point of the Y address signal output from the Y address buffer 17, The signal output from the signal generator 16, the Z predecode signal output from the Z predecoder 14, and Y_AT
A local control signal generator 20 for synthesizing the output signal of the D generator 19 to generate a pulse required for each memory block
And an X post decoder 21 that combines the X predecode signal and the Z predecode signal output from the X predecoder 12 and the Z predecoder 14 to select a corresponding memory cell block, and an X postdecoder 21 and a local control signal. A split word line driving unit 22 for synthesizing a signal output from the generation unit 20 and applying a driving signal to each split word line of each cell array block 23;
A column controller 24 that combines output signals of the predecoder 18 and the local control signal generator 20 to select a corresponding bit line, and combines an output signal of the local control signal generator 20 and an output signal of the column controller 24. Amplifier and input / output control unit 25 for controlling the operation and input / output (I / O) of the sense amplifier, and input / output bus control for interfacing an external data bus with the sense amplifier and input / output control unit 25 And a part 26. The Z address is an address for selecting a memory block.

Hereinafter, a memory cell array using the nonvolatile ferroelectric memory device of the present invention having the above-described basic configuration will be described in more detail. FIG. 5 is a configuration block diagram simply showing the overall configuration of the drive circuit of the nonvolatile ferroelectric memory device of the present invention. The chip of the ferroelectric memory device of the present invention has a large size, a split word line driving unit 41 for driving a split word line (SWL), a cell array unit 42 for storing data, and a sense for sensing data. It comprises an amplifier block, a bit line control block for controlling the bit lines, and a core unit 43 including a local control signal generator (not shown). The split word line SWL means a word line including two word lines arranged in parallel and accessible by one address. The cell array units 42 are arranged on the left and right sides with one split word line driving unit 41 as a center, and the core units 43 are arranged between the cell array units 42 in the vertical direction of each cell array unit 42.
The sense amplifiers arranged in the core unit 43 are arranged by the number of bit lines, and are connected to the bit lines and the corresponding bit bar lines.

Hereinafter, the unit cells constituting the memory cell array as described above will be described in more detail. FIG. 6 is a configuration diagram of a unit cell in the nonvolatile ferroelectric memory device of the present invention. FIG. 6 is a configuration diagram of a basic memory cell.
An NMOS first transistor (T1) 92 having a gate connected to a first split word line (SWL1) 90
And an NMOS second transistor T2 having a gate connected to the second split word line SWL2 91.
One electrode is connected to the source of the first transistor 92 and the other electrode is connected to the second split word line 9.
1 connected to the first ferroelectric capacitor (FC1) 94
And a second ferroelectric capacitor (FC2) 95 having one electrode connected to the first split word line 90 and the other electrode connected to the source of the second transistor 93. In this embodiment, one transistor and one capacitor constitute a memory unit. However, the present invention stores two transistors and two capacitors as in the above-described conventional example. It can also be used for a unit composed of units. The drain of the first transistor 92 is connected to the bit line (Bit_n), and the drain of the second transistor 93 is connected to the next bit line (Bit_n +).
1). Such unit memory cells can store two data, and a pair of first and second split word lines (SWL1, SWL2) can be accessed by one row address. A pair of bit lines (Bit_n, Bit_n + 1) forms two columns. That is, the present embodiment has a split word line configuration in which word lines are used as a pair without using a conventional plate line. This 2
The set, ie, the paired word lines, has the same address as described above. However, signals for driving this are provided separately.

The operation of such a memory cell will be described with reference to the timing chart of FIG. 7 and FIG. Using the waveforms of the first split word line SWL1 and the second split word line SWL2 as shown in FIG. 7, reading and writing can be operated in the same manner. When both the first split word line SWL1 and the second split word line SWL2 are high, if the bit line is "1", that is, high, both ends of the ferroelectric capacitor are not charged at the same potential. On the other hand, if the bit line has "0", the second ferroelectric capacitor is negatively charged. That is, “0” is stored. On the other hand, if the first split word line SWL1 is low and the second split word line SWL2 is high and there is "1" data in the bit line Bit_b + 1, "1" is stored in the second ferroelectric capacitor FC2. . In this way, they can be stored in FC2. In the read mode, the first and second ferroelectric capacitors (FC1, FC1
The data stored in 2) is transferred to the bit line (B_n)
And the bit line (B_n + 1).

Here, logic "0" is stored in the first ferroelectric capacitor FC1, and the second ferroelectric capacitor F1
When logic "1" is stored in C2, the voltage applied to the bit line (B_n) is
_N + 1) has a smaller voltage rise value. That is, when the logic "1" is stored in the second ferroelectric capacitor FC2, a large amount of remnant polarization charges are loaded on the bit line (B_n + 1) while the logic "1" changes to the logic "0" state. This is because the voltage is further increased. Therefore, logic "1"
Since the polarization destruction from logic to logic “0” occurs, the second
It must be stored again in the ferroelectric capacitor. Conversely, the logic "1" is applied to the first ferroelectric capacitor FC1.
However, when logic "0" is stored in the second ferroelectric capacitor FC2, when both the first and second split word lines are high, the first ferroelectric capacitor FC1
Is destroyed and changes to logic "0".

Here, in order to restore the logic "1" destroyed in the first and second ferroelectric capacitors, the following additional pulse is required. When the logic “1” is stored in the first ferroelectric capacitor and the logic “0” is stored in the second ferroelectric capacitor, the logic “1” must be stored again in the first ferroelectric capacitor. A high signal must be applied to one split word line, and a low signal must be applied to the second split word line. That is, a high voltage (that is, high data of the bit line (B_n)) is applied to one electrode of the first ferroelectric capacitor FC1 via the NMOS transistor T1 turned on by the first split word line,
By applying a low voltage through the second split word line serving as the opposite electrode, the logic "1" can be restored in the first ferroelectric capacitor FC1. When the logic “0” is stored in the first ferroelectric capacitor FC1 and the logic “1” is stored in the second ferroelectric capacitor FC2, the logic “1” is stored again in the second ferroelectric capacitor. For this, a low voltage must be applied to the first split word line SWL1 and a high voltage must be applied to the second split word line SWL2. That is, a high voltage (high data of the bit line (B_n + 1)) is applied to one electrode of the second ferroelectric capacitor FC2 via the NMOS transistor T2 turned on by the second split word line, and the other electrode is turned on. By applying a low voltage according to the signal of the first split word line that plays the role of
Logic "1" can be stored again in the second ferroelectric capacitor (FC2).

The operation in the read mode can be similarly applied to the write mode. That is, to store logic "1" in the first ferroelectric capacitor FC1, a high signal is applied to the first split word line SWL1 and a low signal is applied to the second split word line SWL2. Bit line B_n has a "1". In order to store logic "1" in the second ferroelectric capacitor FC2, a low signal is applied to the first split word line while "1" is placed on the bit line B_n + 1, and the second split is performed. A high signal is applied to the word line.

FIG. 8 is a configuration diagram of a memory cell array according to the nonvolatile ferroelectric memory device of the present invention. As shown in FIG. 8, a plurality of first split word lines (SWL1_n, SWL1_n + 1, SWL1_n +
, SWL1_n + 3,... Are arranged in parallel with the second split word lines (SWL2_n, SWL).
2_n + 1, SWL2_n + 2, SWL2_n + 3,.
・) Is arranged. A plurality of bit lines (B_B_B) are arranged in a direction intersecting the first and second split word lines.
n, Bn + 1, B_n + 2, B_n + 3,...) are arranged in parallel with each other. Memory cells are connected between these word lines and bit lines. Here, this memory cell is connected to the first split word line SW
For L1_n, bit lines B_n, B_n + 2 ·
Is connected to the intersection of the odd-numbered bit line from the left in the figure, and the second split word line is connected to the intersection of the even-numbered bit line.
That is, from the viewpoint of a specific split word line, it can be seen that memory cells are arranged on every other bit line, and that a folded bit line configuration is formed. Therefore, each split word line is configured to have memory cells divided into even or odd bit lines. This means that only one split word line cannot be enabled, and the first and second split word lines (SWL1, SWL) must be enabled.
2) means accessing simultaneously.

FIG. 9 is a block diagram of the global control signal generator 16 shown in FIG. The configuration of the global control pulse generator 16 is CSBpad input from outside.
Signal, the X, Z_ATD signal of the X, Z_ATD generation unit 15, or at least the CSB of the power-up detection signal.
an input buffer unit 31 that receives a signal including a pad signal and generates first and second synchronization signals;
A low-voltage detection signal for receiving a first synchronization signal and a feedback signal to disable operation at a low voltage;
The low-voltage operation and noise prevention unit 32 outputs a noise removal signal for filtering the noise of the synchronization signal and a pre-activation pulse for pre-charging the bit line and the like. Further, first to fourth controllers 33 to 36 that output various control signals are prepared. The first controller 33 receives a noise-free signal when a normal power supply voltage is supplied from the low-voltage operation and noise prevention unit 32, and is used to generate a signal for adjusting the enable time of the sense amplifier. A first internal signal, a second internal signal used to generate a signal for adjusting a column selection enable time point and adjusting a pull-up of a bit line, an input signal of the SWL driver, and other control signals. And a third internal signal used to generate a signal at the time of generation. The second controller receives the third internal signal of the first controller 33, and generates a drive signal of SWL1 for generating a drive signal of SWL1 and a signal S2 for generating a drive signal of SWL2. A pulse signal P2 as an interlock signal for compensating so that the normal operation of the signals (S1, S2) does not interfere with the driving capability and improving the driving capability is output to the local control pulse generator 20, and the signal (S1
A fourth internal signal, which is a basic pulse signal for adjusting the activation period of (1, S2), is output to the third controller 35, and is output as a feedback signal of the low voltage operation and noise prevention unit 32. The third controller 35 receives the first and second synchronizing signals of the input buffer unit 31 and the fourth internal signal of the second controller 34, and outputs the signals S1 and S2 when the CSBpad signal is disabled. A fifth internal signal for disabling all but excluded signals;
With signals S1 and S2 enabled, C
When the SBpad signal is disabled, the signals S1 and S for shutting off the SBpad signal and generating SWL1 are output.
And a sixth internal signal for extending the enable state until the operation of the signal S2 for generating WL2 is normally completed.
The fourth controller 36 receives the fifth and sixth internal signals of the third controller 35, the first, second, and third internal signals of the first controller 33, the low-voltage operation, and the preliminary activation pulse of the noise prevention unit 32. And the sense amplifier nMO
S element enable signal SAN, pMOS element enable signal SAP, first control signal C1 for connecting the bit line of the main cell and the input / output terminal of the sense amplifier, second input / output node of the bit line and the sense amplifier , A third control signal C3 for adjusting the low voltage precharge of the bit line of the main cell and the node of the sense amplifier, and a fourth control signal for adjusting the pull-up when the column selection is enabled. Control signal C
4 is output.

If external input signals (CSBpad signal, X, Z_ATD signal, and power-up detection signal) are stably input from the global control signal generation unit, even if there is no low-voltage operation and noise prevention unit. Works well. The global control signal generation unit configured as described above generates a third control signal C for generating a control signal (C3_C) applied to the sense amplifier and the input / output control unit 25.
3. Signals (S1, S2) used to generate signals (PS1, PS2) applied to the split word line driving unit 22, and a signal C4N applied to the column control unit 24
And the first and second control signals C1 and C2 used to generate a signal for controlling the connection between the bit line and the input / output terminal of the sense amplifier. , And these signals are input to the local control signal generator 20.

Here, the local control signal generator is configured as follows. FIG. 10 is a configuration diagram of a local control signal generator of the drive circuit of the nonvolatile ferroelectric memory device according to the present invention. S1, S2, P2, C1, C2, C3, C4, SA input to the local control pulse generator 20
The N and SAP signals are output signals of the global control pulse generator 16 described above. The Y_ATD signal is an address transition detection signal generated when the Y address transitions.
It becomes high by detecting. The WEBpad signal is a signal of the write enable pad, and becomes a low state in the write mode, and defines the low state as an active state. Z_Add1, Z_Add2, Z_Add3, Z_
Add4 is a signal output from the Z address predecoder 14.

The local control pulse generator 20 of this embodiment shown in FIG. 10 will be described as an example in which a control signal for selecting a memory cell on the left side with respect to the split word line driver in FIG. 5 is output. . Here, the local control signal generator for outputting the control signal for selecting the right memory cell has the same configuration as the local control signal generator for outputting the control signal for selecting the left memory cell. Local control pulse generator 2
0 denotes a first control pulse generator 200 that generates a signal input to the sense amplifier / input / output controller 25, a second control pulse generator 201 that generates a signal input to the column controller 24, and the SWL driver 22. And a third control pulse generator 202 for generating a signal to be input to the third control pulse generator.

The first control pulse generating section 200 includes SAP,
SAN, Z_Add3, Z_Add4, third control signal C
3 to calculate SAP_C, SAN_C, C3N_
C, first logical operation unit 203 that outputs C3P_C signal
And the first and second control signals (C1, C2), Z_Add
1, control pulses C1P_T, C1N_T, C2P for controlling the upper block using the Z_Add2 signal as input
_T, C2N_T, and a second logical operation unit 204 that outputs C3N_T signals. In addition, in each signal in this specification, N indicates that it is for driving the NMOS, T indicates that the upper block is controlled, and B indicates that the lower block is controlled (FIG. 10). Is only the upper side). Also, the last C means that the signal is used commonly in the upper and lower directions.

The configuration of the local control pulse generator 20 thus configured will be described in more detail below.
First logical operation unit 203 of first control pulse generation unit 200
Performs a logical operation on the Z_Add3 and Z_Add4 signals,
A first NAND gate 203-1 for outputting a signal related to generation of a control signal applied to the lower block;
A second NAND gate 203-2 that performs a logical operation on the output signal of the AND gate 203-1 and the Z_Add1 and Z_Add2 signals that have undergone the NAND operation, and outputs the result.
A third NAND gate 203-3 for calculating and outputting an AP signal and an output signal of the second NAND gate 203-2,
The output signal of the third NAND gate 203-3 is inverted to S
First inverter 203-4 that outputs AP_C signal
And a fourth NAND gate 20 that performs a logical operation on the SAN signal and the output signal of the second NAND gate 203-2 and outputs the result.
3-5 and a second inverter 2 which inverts an output signal of the fourth NAND gate 203-5 and outputs a SAN_C signal.
03-6, the third control signal C3 inverted by the third inverter 203-7, and the second NAND gate 203-2.
A fifth NAND gate 203-8 for performing a logical operation on the output signal of the fifth NAND gate 203-8, a fourth inverter 203-9 for inverting an output signal of the fifth NAND gate 203-8 and outputting a C3P_C signal, and a fourth inverter 203- And a fifth inverter 203-10 for inverting the output signal of No. 9 and outputting a C3N_C signal.

The second logical operation unit 204 of the first control pulse generation unit 200 performs a logical operation on the Z_Add1 and Z_Add2 signals and outputs a signal related to generation of a control signal applied to the upper block. Gate 2
04-1, a sixth inverter 204-2 for inverting the output signal of the sixth NAND gate 204-1, and the output signal of the sixth inverter 204-2 and the first control signal C1 are set to N.
Seventh NAND gate 204-3 for performing AND operation and outputting
And C1 from the output signal of the seventh NAND gate 204-3.
Seventh and eighth inverters 204 that output the P_T signal
4, 204-5, a ninth inverter 204-6 that inverts an output signal of the seventh NAND gate 204-3 and outputs a C1N_T signal, and an output signal of the sixth inverter 204-2 and the second control signal C2. An eighth NAND gate 204-7 for performing a logical operation and outputting, and an eighth NAND gate 2
The first for outputting the C2P_T signal from the output signal of 04-7
0, the output signals of the eleventh inverters 204-8 and 204-9 and the eighth NAND gate 204-7 are inverted to obtain a signal C2.
A twelfth inverter 204-10 that outputs an N_T signal
And a ninth NA that performs a logical operation on the output signal of the sixth inverter 204-2 and the inverted third control signal C3 and outputs the result.
ND gate 204-11 and ninth NAND gate 204
The first to output the C3N_T signal from the output signal of −11
3. Fourteenth inverters 204-12 and 204-13.

Then, the second control pulse generator 201
Fifteenth inverter 201 for inverting the WEBpad signal
-1, the sixteenth inverter 201-2 for inverting the output signal of the fifteenth inverter 201-1, the seventeenth inverter 201-3 for inverting the fourth control signal C4, and the first
6. A tenth NAND gate 201- which calculates and outputs output signals of the seventeenth inverters 201-2 and 201-3.
4, an eighteenth inverter 201-5 for inverting and outputting the output signal of the tenth NAND gate 201-4, and a third inverter 201-5.
A first NOR operation unit that NOR-operates and outputs the control signal C3, the output signal of the eighteenth inverter 201-5, and the output signal of the sixth NAND gate 204-1 of the second logic operation unit 204 of the first control pulse generation unit 200 201-6
And a nineteenth inverter 201-which inverts an output signal of the NOR operation unit 201-6 and outputs a C4P_T signal.
7, and a twentieth inverter 20 that inverts the output signal of the nineteenth inverter 201-7 and outputs a C4N_T signal.
1-8.

Then, the third control pulse generator 202
A twenty-first inverter 202-1 for inverting the P2 signal;
The Y_ATD signal, the output signal of the twenty-first inverter 202-1, the fourth control signal C4, and the inverted WEBpa
An eleventh NAND gate 2 that performs a logical operation on the signal d and outputs the result
02-2, a twenty-second inverter 202-3 for inverting the output signal of the eleventh NAND gate 202-2, and a twenty-second inverter 202-3.
Second to delay the output signal of inverter 202-3
3, 24th, 25th, 26th inverters 202-4,
202-5, 202-6, and 202-7, a second NOR gate 202-8 that calculates and outputs the S1 signal and an output signal of the twenty-second inverter 202-3, and an output signal of the second NOR gate 202-8. The sixth of the second logical operation unit 204
A third NOR gate 202-9 for performing a NOR operation on an output signal of the NAND gate 204-1 and outputting the result, and a third NOR gate
A 27th inverter 202-10 for inverting the output signal of the gate 202-9 and outputting the PS1_T signal, and a fourth NOR gate 202 for calculating and outputting the second control signal S2 and the output signal of the 26th inverter 202-7. -11
And a fifth NOR gate 20 that NOR-operates the output signal of the fourth NOR gate 202-11 and the output signal of the sixth NAND gate 204-1 of the second logical operation unit 204 and outputs the result.
2-12, and a 27th inverter 202-13 for inverting the output signal of the fifth NOR gate 202-12 and outputting the PS2_T signal.

As described above, the local control signal generator of the present embodiment is different from the first embodiment in that the first logical operation unit 203 of the first control signal generator 200 uses the control signal commonly used for the upper memory cell and the lower memory cell. And the first control signal generator 2
The second logical operation unit 204 and the second and third control signal generation units 201 and 202 generate a signal for controlling the upper memory cell. Here, the PS1_T and PS2_T signals are control signals for selecting the upper memory cell.
The B and PS2_B signals are control signals for selecting the lower memory cell, and the split word line driving unit 41
Is the signal applied to.

Up to now, the split word line driving unit 2
The output process of the control signal for selecting the memory cell on the left side with respect to 2 has been described. As described above, the output process of the control signal for selecting the right memory cell is the same as the output process of the control signal for selecting the left memory cell. Accordingly, the local control signal generator 20 on the right side also outputs the split word line driver 2 at the center.
1, PS1_T, PS2_T signals, PS1_B, PS2
_B signal is output. Of course, PS1_B, PS2_
The output process of the B signal is the same as the output process of the PS1_T and PS2_T signals. Therefore, depending on which local control signal generator 20 activates the PS1 and PS2 signals,
Naturally, one of the left cell array and the right cell array is selected.

On the other hand, FIG. 11 shows a first embodiment of a split word line drive unit using a drive circuit of a nonvolatile ferroelectric memory device according to the present invention. As shown in FIG. 11, the split word line driving unit of the present embodiment includes a local control signal generating unit 20 that outputs a signal for selecting a cell array unit on the left side with respect to the split word driving unit. PS2 signal (where P
The S1 and PS2 signals may be PS1_T and PS2_T signals, and may be PS1_B and PS2_B signals).
And PS1, which is output from a local control signal generator that outputs a control signal for selecting the cell array on the right side,
PS2 signal (where the PS1 and PS2 signals are PS1
_T, PS2_T, PS1_B, PS2
_B signal), the third signal line 111, the fourth signal line 111a, and the first signal line 100,
A plurality of first split word line driving signal output units 112 respectively connected to the signal lines 111, and a second split word line driving signal output unit 1 respectively connected to the second signal line 100a and the fourth signal line 111a.
13 and a plurality of first and second split word line drive signal output units 11 by decoding an input X address.
And an X address signal output unit 114 that outputs a signal for selecting a pair of first and second split word line drive signal output units 112 and 113 among the two.

Here, the X address signal output unit 114
It comprises a decoder 114a for inputting and decoding two or more X addresses and an inverter (INV) for inverting an output signal of the decoder 114a. The X address signal output unit 114 outputs a signal for selecting a pair of first and second split word line drive signal output units 112 and 113. That is, if the first and second split word line drive signal output units 112 and 113 are formed of a plurality of pairs, a plurality of X address output units 114 are also prepared. For example, if the first and second split word line drive signal output units 112 and 113 are composed of eight pairs, eight X address signal output units 114 are also composed. Therefore, the first, second,
Split word line drive signal output unit pair 112, 11
3, only the X address output unit 114 connected to the pair of first and second split word line driving signal output units 112 and 113 to be selected is activated. At this time, the number of X addresses input to the decoder unit 114a depends on the first and second split word line drive signal output units 11
2, 113 are determined by the configured pair.

In the split word line driver configured as above, the first and second signal lines 100, 1
When 00a is simultaneously activated to a low state, a driving signal is applied to the left cell array unit. When the third and fourth signal lines 111 and 111a are simultaneously activated to a low state, the right cell array is activated. A drive signal is applied to the unit. That is, the first and second signal lines 100 and 100a
Is activated, or the third and fourth signal lines 11
A drive signal is applied to the cell array in the corresponding direction (left or right) depending on whether 1, 111a is activated.

The first and second split word line drive signal output units 112 and 113 output drive signals to the left and right cell array units. Whether to select the two split word line drive signal output units 112 and 113 is determined based on whether or not the output signal of the X address signal output unit 114 can be activated. That is, the first and second signal lines 100 and 100a, the third and fourth signal lines 11
Even if one of the left cell array and the right cell array is selected based on the activation state of 1, 111a, the plurality of first and second split word line pairs of the selected cell array are not changed. They cannot be activated together. Therefore, in order to selectively apply a drive signal to one of the first and second split word line pairs among the plurality of first and second split word line pairs, only one X address signal output unit 114 is provided. Must be activated. As described above, the split word line driving unit shares the left cell array unit and the right cell array unit, and includes a plurality of first split word lines (SWL1_n, SWL1_n + 1, SW).
L1_n + 2,...) And second split word lines (SWL2_n, SWL2_n + 1, SWL2_n + 2).
...), The driving signal is output only to the pair of first and second split word lines.

Hereinafter, the split word line drive signal output unit will be described in more detail. As shown in FIG. 11, each split word line driving signal output unit 112,
Reference numeral 113 denotes a PMOS transistor and an NMOS transistor connected in series, and the gate of each transistor is connected in common. First signal line 100 and third signal line 1
A plurality of first split word line driving signal output units 112 are connected to the second and fourth signal lines 100.
A second split word line driving signal output unit 113 is connected to each of the first and second split word line driving signal output units 112. Therefore,
A first split word line driving signal output unit 112 and a second split word line driving signal output unit 113 connected to the first signal line 100 and the second signal line 100a respectively output a driving signal to the left cell array unit. The first split word line driving signal output unit 112 and the second split word line driving signal output unit 113 connected to the third signal line 111 and the fourth signal line 111a respectively output driving signals to the right cell array unit.

As described above, each of the split word line drive signal output units 112 and 113 is composed of a PMOS transistor and an NMOS transistor, and each of the signal lines 100, 100a, 111 and 111a has a PM level.
It is connected to a common gate of the OS transistor and the NMOS transistor. First and second signal lines 100 and 100a
When the PS1 signal and the PS2 signal applied through the X are in a low state and the output signal of the X address signal output unit 114 that decodes and outputs the X1 and X2 address signals is activated, a plurality of signals arranged on the left side The first and second split word line drive signal output units 112 and 113 of the pair of first and second split word line drive signal output units 112 and 113 are activated, and the first and second split word line drive units are activated. (L_SWL1_n, L_SWL2_
n) is activated. Conversely, the PS1 signal, PS1 applied through the third and fourth signal lines 111, 111a
2 signal is in a low state, and when the output signal of the X address signal output unit 114 for decoding and outputting the X1 and X2 address signals is in an activated state, a plurality of pairs of first and second splits arranged on the right side Word line drive signal output unit 11
2 and 113, the first and second split word line driving signal output units 112 and 113 are activated, and the first and second split word lines (R_SWL1) are activated.
_N, R_SWL2_n) are activated.

On the other hand, the first and second signal lines 100, 10
When the PS1 signal and the PS2 signal applied via Oa are in a low state and the output signal of the X address signal output unit 114 that decodes and outputs the X3 and X4 address signals is activated, the left side is configured. The second first and second split word line drive signal output units 112 and 113 of the plurality of pairs of first and second split word line drive signal output units 112 and 113 are activated, and the first and second split word are output. Line (L_SWL1_n + 1, L_SW
L2_n + 1) is activated. Conversely, the third and fourth
PS1 applied via signal lines 111, 111a
Signal and PS2 signal are in a low state, and an X address signal output unit 1 that decodes and outputs X3 and X4 address signals
When the 14 output signals are activated, the second first and second split word line driving signals of the plural pairs of the first and second split word line driving signal output units 112 and 113 arranged on the right side. The output units 112 and 113 are activated, and the first and second split word lines (R
_SWL1_n + 1, R_SWL2_n + 1) are activated.

As a result, whether to select the left cell array or the right cell array among the left and right cell arrays is determined by the first and second signal lines 10.
0, 100a and the third and fourth signal lines 111, 111
It is determined by the PS1 signal and the PS2 signal applied via a. As described above, when one of the left and right sides is selected, the order of the first and second split word lines of the selected cell array unit is determined by the input signals (X1, X1) of the decoder unit 114a. X2, X3, X
4).

Here, the first and second signal lines 100, 1
FIG. 12 shows timings of the PS1 and PS2 signals applied via the 00a, third and fourth signal lines 111 and 111a, and the output signals of the split word line drive signal output units 112 and 113. As shown in FIG.
PS1 signal and first split word line signal SWL1
And the same transition timing. The PS2 signal and the second split word line signal SWL2 have opposite phases and have the same transition timing.

As shown in the timing chart, the PS1 signal,
Until t1 when both PS2 signals are high, the first
The second split word line signal (SWL1, SWL)
2) are all kept low. PS1 signal, PS2
In a period t1 when the signal changes from the high state to the low state, the first and second split word lines (SWL1, SWL) are used.
2) are all transited to the high state. PS1 signal, PS2
In a period t2 when the signals are in a high state and a low state, respectively, the first split word line signal SWL1 is maintained in a low state and the second split word line signal SWL2 is maintained in a t1 state. In a period t3 when the PS1 signal and the PS2 signal are in the low state and the high state, respectively, the first split word line signal SWL1 is changed from the previous low state to the high state, and the second split word line signal SWL is changed.
WL2 transitions from a previous high state to a low state. Thereafter, both the PS1 signal and the PS2 signal are set to the high state.
In the fourth section, the first split word line signal SWL1
Is changed from the previous high state to the low state, and the second split word line signal is maintained in the state of the low state t3 section.

On the other hand, FIG. 13 shows a second embodiment of a split word line driving section using a nonvolatile ferroelectric memory device and a driving circuit according to the present invention. In the split word line driving unit according to the second embodiment of the present invention shown in FIG. 13, each of the split word line driving signal output units 112 and 113 is NOR compared with the first embodiment of the present invention.
X address signal output unit 114 is configured by NAN
It consisted of only the D gate. For example, the first, second
Split word line drive signal output units 112 and 113
That is, the output signal of the X address signal output unit 114 is applied to one input terminal of a NOR gate constituting the first split word line drive signal output unit 112, and the first signal is input to the other input terminal. Line 100 is connected. The output signal of the X address signal output unit 114 is applied to one input terminal of the NOR gate constituting the second split word line drive signal output unit 113, and the second signal line 100a is applied to the other input terminal. Are linked.

As described above, the structure of the first and second split word line drive signal output units 112 and 113 for outputting a drive signal for selecting the left cell array unit, and the drive for selecting the right cell array unit. First and second split word line drive signal output units 11 for outputting signals
2 and 113 are the same. Simply, the input terminals of the NOR gates constituting the first split word line drive signal output units 112 and 113 on the right are connected to the third signal line 111 together with the output signal of the X address signal output unit 114.
Is connected to the input terminal of the NOR gate constituting the second split word line drive signal output unit 113.
The fourth signal line 111a is connected with the output signal of the address signal output unit 114.

FIG. 14 is a block diagram of a split word line driving unit according to a third embodiment of the present invention. The split word line driving unit shown in FIG. 14 includes first and second signal lines 100 and 100a, third and fourth signal lines 111,
The PS1 and PS2 signals applied via the first and second split word line drive signal output units 112 and 113
It is configured to pass through the inverter 130 before being applied to the. Then, the X address signal output unit 114
NAN that decodes two or more input X addresses
A decoder 114a composed of a D gate;
and an inverter (INV) for inverting the output signal a of FIG. 3A, which is the same as the configuration of the X address signal output unit 114 of the first embodiment. Further, each of the split word line drive signal output units 112 and 113 is configured as a NAND gate instead of the NOR gate, as compared with the second embodiment, and an inverter is configured at an output terminal of each NAND gate.

In the third embodiment of the present invention, the PS1 signal and the P1 signal applied through the first and second signal lines 100 and 100a, and the third and fourth signal lines 111 and 111a are used.
The S2 signal is inverted by the inverter 130 and is used as a control signal for selecting the cell array on the left and a control signal for selecting the cell array on the right. Here, when the PS1 signal and the PS2 signal applied to the third signal line 111 and the fourth signal line 111a are activated and the output signal of the X address signal output unit 114 is activated to a high state, 1. The second split word line driving signal output units 112 and 113 are activated. Accordingly, when the first and second split word lines connected to the first and second split word line driving signal output units 112 and 113 are activated, data is written to the corresponding memory cell or data of the memory cell is written. Can be read.

[0046]

According to the present invention, in one split word line driving section, the X address signal output section is configured to be able to share two cell array sections, and the first split word line driving signal and the second split word line driving signal are shared. Since the word line driving signal is separately applied to each cell array unit, the layout of the nonvolatile memory device can be reduced. Furthermore, since a split word line cell that does not require another plate line is configured, the configuration of a split word line driving unit required to activate two split word lines can be further simplified. According to the fifth and sixth aspects of the present invention, only one of the two cell array units is selectively activated. Therefore,
For each of the first and second split word line drive signal output units forming a pair to drive any first and second split word line drive signal output units among the plurality of first and second split word line drive signal output units Constitute an X address signal output unit. Accordingly, it is possible to select an arbitrary memory cell such that the corresponding pair of first and second split word line drive signal output units output a drive signal according to whether the corresponding X address signal output unit is activated. it can.

According to the seventh aspect of the present invention, the X address signal output section can reduce the number of transistor elements in each split word line drive signal output section to reduce the layout. According to the eighth aspect of the present invention, it is possible to improve the driving capability of the split word line driving unit and to effectively drive the split word line driving unit even when the RC loading on each split word line is large. it can.

[Brief description of the drawings]

FIG. 1A is a characteristic curve of a nonvolatile ferroelectric memory device, and b is a ferroelectric capacitor using a nonvolatile ferroelectric memory.

FIG. 2 is a diagram showing a cell array configuration of a conventional nonvolatile ferroelectric memory device.

3A is a timing chart for explaining a writing operation of a conventional 2T / 2C ferroelectric memory cell, and FIG. 3B is a timing chart for explaining a reading operation of a conventional 2T / 2C ferroelectric memory cell. Timing diagram.

FIG. 4 is a block diagram showing a configuration of a drive circuit using the nonvolatile ferroelectric memory device of the present invention.

FIG. 5 is a configuration block diagram of a split word line driving unit and a cell array in the nonvolatile ferroelectric memory device of the present invention.

FIG. 6 is a configuration diagram of a unit cell of the nonvolatile ferroelectric memory device of the present invention.

FIG. 7 is a timing chart of each control signal by the nonvolatile ferroelectric memory device of the present invention.

FIG. 8 is a configuration diagram of a memory cell array by a drive circuit of the nonvolatile ferroelectric memory device according to the present invention.

FIG. 9 is a configuration diagram of a global control signal generation unit by the drive circuit of the nonvolatile ferroelectric memory device according to the present invention.

FIG. 10 is a configuration diagram of a local control signal generation unit by a drive circuit of the nonvolatile ferroelectric memory device of the present invention.

FIG. 11 is a configuration diagram showing a first embodiment of a split word line drive unit using a drive circuit of the nonvolatile ferroelectric memory device of the present invention.

FIG. 12 is an operation timing chart of an input signal and an output signal of the split word line driving unit of the present invention.

FIG. 13 is a configuration diagram illustrating a split word line driving unit according to a second embodiment of the present invention using a driving circuit of the nonvolatile ferroelectric memory device.

FIG. 14 is a configuration diagram showing a third embodiment of a split word line driving unit using the driving circuit of the nonvolatile ferroelectric memory device of the present invention.

[Explanation of symbols]

 Reference Signs List 16 global control signal generation unit 20 local control signal generation unit 22 split word line drive unit 23, 42 cell array unit 24 column control unit 25 sense amplifier and input / output control unit 43 core unit 200 first control signal generation unit 201 second control signal Generation unit 202 Third control signal generation unit 203 First logical operation unit 204 Second logical operation unit 100, 100a First, second signal line 111, 111a Third, fourth signal line 112 First split word line drive signal output Unit 113 second split word line drive signal output unit 114 X address signal generation unit 114a decoder 130 inverter

Claims (8)

[Claims] 1. A first cell array section and a second cell array, wherein a certain number of memory cells connected to a first split word line and a second split word line are formed as a block, and are arranged in a horizontal direction. A non-volatile ferroelectric memory device including a local control signal generation unit for outputting a signal for selecting a unit, wherein the local control signal generation unit selects a first cell array unit of the two cell array units. First and second signal lines for transmitting output signals; third and fourth signal lines for transmitting signals output from the local control signal generator to select a second cell array unit; A first split word line driving signal output unit connected to the first and third signal lines, respectively; A second split word line drive signal output unit connected to the first and second split word line drive signal output units for activating any one of the first and second split word line drive signal output units; A drive circuit for a nonvolatile ferroelectric memory device, comprising: an X address signal output unit that outputs a control signal. 2. A first cell array section and a second cell array section, wherein a certain number of memory cells connected to a first split word line and a second split word line are formed as a block, and the first cell array section and the second cell array section are arranged in a horizontal direction. A non-volatile ferroelectric memory device comprising a local control signal generating unit for outputting a signal for selecting the first cell array unit from among the two cell array units. First and second signal lines for transmitting output signals; and third and fourth signal lines for transmitting signals output from the local control signal generator to select the second cell array unit.
A plurality of first split word line driving signal output units, wherein a signal line, a PMOS transistor and an NMOS transistor are connected in series, each gate is connected in common, and the gates are connected to the first and third signal lines; A plurality of second split word line driving signal output units, wherein a PMOS transistor and an NMOS transistor are connected in series, each gate is connected in common, and the gates are connected to the second and fourth signal lines; An NAND gate for performing a logical operation on the X address signal, and an inverter for inverting an output signal of the NAND gate, wherein any one of the first and second split word line driving signal output units is provided. Each of the PMOS transistors is used to activate the two-split word line drive signal output section. Driving circuit of a nonvolatile ferroelectric memory device characterized in that it comprises an X address signal output unit for outputting a control signal to the source terminal. 3. When the first signal line and the second signal line are activated and an output signal of the X address signal output unit is activated, a first signal for outputting a driving signal to the first cell array unit. 3. The driving circuit of claim 2, wherein the second split word line driving signal output unit is activated. 4. When the third signal line and the fourth signal line are activated and the output signal of the X address signal output unit is activated, a first signal for outputting a driving signal to the second cell array unit. 3. The driving circuit of claim 2, wherein the second split word line driving signal output unit is activated. 5. A plurality of X address signal output units are prepared, and as the output signal of an arbitrary X address signal output unit is activated, the corresponding first and second split word line drive signal output units are activated. 3. The driving circuit for a nonvolatile ferroelectric memory device according to claim 2, wherein: 6. An X-address signal output unit, comprising:
A control signal is commonly output to first and second split word line drive signal output units for outputting a drive signal to the cell array unit and first and second split word line drive signal output units for outputting a drive signal to the second cell array unit. 3. The driving circuit for a nonvolatile ferroelectric memory device according to claim 2, wherein: 7. An N address constituting said X address signal output section.
3. The drive circuit for a nonvolatile ferroelectric memory device according to claim 2, wherein each of the split word line drive signal output sections is constituted by a NOR gate, and is constituted by only a NAND gate instead of the AND gate and the inverter. 8. An inverter is provided for each of the first, second, third, and fourth signal lines, and each of the split word line driving signal output units includes a control signal of the X address signal output unit and a corresponding signal line. 3. A NAND gate for inputting a signal applied through said inverter to perform a logical operation, and an inverter for inverting an output signal of said NAND gate.
A driving circuit for the nonvolatile ferroelectric memory device according to claim 1.