JPH1132431A - Power on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a stabilized operation regardless of fluctuation or variation in the rising rate or the magnitude of power supply voltage by providing a power on reset circuit with a capacitor and a resistor having resistance variable monotonously as the power supply voltage increases. SOLUTION: The power on reset circuit P divides the power supply voltage through a capacitor C and a variable resistor VR and inverts the output from an inverter INV. Consequently, the potential level of a low potential side power supply VSS is inputted surely to the inverter INV and fluctuation in the rising rate of power supply voltage simply causes a slight timing shift and causes no problem in the operation. Since the resistance of the capacitor C is infinite, it is higher than the resistance of the variable resistor VR, and the potential at the joint of the capacitor C and the variable resistor VR is equalized surely to that of the low potential side power supply VSS and fluctuation in the magnitude of power supply voltage causes no problem.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to portable telephones and portable telephones having a function of periodically stopping power supply in portable equipment.
In a temperature-compensated crystal oscillator used as a reference signal source of a mobile communication device typified by an HS or the like, the present invention relates to a configuration of a power-on reset circuit that sets an initial state of a circuit system when power is turned on.

[0002]

[Prior art]

[Explanation of Background Description] In recent years, by lowering the power supply voltage of electronic equipment components such as a digital temperature-compensated crystal oscillator mounted on mobile communication devices such as a mobile phone and a PHS to reduce power consumption during operation. There is a great demand for extending the operation time of portable devices.

Further, as with general electronic equipment, in mobile communication equipment, the operating time and the standby time can be divided by turning the power switch “ON” or “OFF”. Therefore, power consumption can be reduced to almost zero by completely stopping the operation during the standby time.

However, in the case of a mobile phone, there are a talk time and a standby time in the operation time, and it is not possible to completely stop the operation by turning off the power switch during the standby time like the standby time. Further, since the standby time occupies a longer time than the talk time of the mobile phone, the time during which the mobile phone can be used is determined by the power consumption of the standby time.

Here, in order to reduce the power consumption during the standby time, there are further operation times and standby times within the standby time, and these times are hereinafter referred to as standby operation time and standby standby time. In the standby operation time, an incoming call check is performed to determine whether or not a signal is being transmitted to the mobile communication device. If it is confirmed that the signal is being transmitted, the call time, which is the operation time, is reached.

[0006] However, if it is not possible to confirm that the signal is being transmitted during the standby operation time, the standby standby time is resumed. In this standby standby time, the supply of the power supply voltage to circuits other than the circuit for measuring the elapsed time is stopped in order to reduce power consumption as much as possible.

That is, the mobile communication device repeats the standby operation time and the standby standby time within the standby time, confirms the signal transmission only during the standby operation time, switches to the talk time, and does not confirm the signal transmission. Returns to the standby time.

As described above, since the operation time and the standby time are alternately performed even during the standby time, when the standby standby time is shifted to the standby operation time, the power supply voltage is stopped during the standby standby time. The supply of the power supply voltage is started.

At this time, a power-on reset circuit is used to set the initial state of the circuit system after the supply of the power supply voltage is started. If it depends, the circuit system cannot be started in a stable state.

If it takes too much time from the start of the supply of the power supply voltage until the operation becomes stable and the arrival of the signal can be confirmed, the standby operation time becomes longer as a result. Power consumption over time also increases.

As described above, in order to reduce the power consumption during the standby time, the supply of the power supply voltage is started at any rise within the power supply voltage for compensating the operation of the electronic device components used in the mobile communication device. After that, it is required to have a specification that is stable in a short time.

[Description of Prior Art: FIG. 7] Next, the configuration of a power-on reset circuit according to the prior art will be described with reference to FIG. FIG. 7 shows a conventional power-on reset circuit P.
FIG.

The configuration of the prior art power-on reset circuit P shown in FIG. 7 is such that a capacitor C and a resistor R are connected in series between a high-potential power supply VDD and a low-potential power supply VSS, and the capacitor C and the resistor R are connected in series. The connection point is connected to the input of the inverter INV, and the output of the inverter INV is used as the signal output section OUT. In FIG. 7, the capacitor C is connected to the high-potential power supply VDD, and the resistor R is connected to the low-potential power supply VSS. There is also a configuration in which the capacitor C is connected to the potential-side power supply VDD and the capacitor C is connected to the low-potential-side power supply VSS.

Next, the operation of the conventional power-on reset circuit P shown in FIG. 7 will be described. However, the potential of the high-potential-side power supply VDD is set to “high” and the low-potential-side potential VS
S is called "low".

When the supply of the power supply voltage is started, in the initial state, the capacitor C is charged with the electric charge which is the potential of the high-potential-side power supply VDD, a "high" signal is input to the inverter INV, and the output is the output of the inverter INV. The signal output section OUT outputs a "low" signal.

Next, the electric charge, which is the potential of the high-potential power supply VDD charged in the capacitor C, is discharged to the low-potential power supply VSS via the resistor R, and the signal level input to the inverter INV is a "high" signal. Changes to a “low” signal,
The signal output section OUT, which is the output of the inverter INV, outputs a "high" signal. At this time, the signal output unit O
The signal level at the UT is inverted from a "low" signal to a "high" signal when the input signal passes the threshold potential of the inverter INV.

Here, if the logic of the peripheral circuit is designed so that the initial state of the circuit system is set while the signal level at the signal output section OUT of the power-on reset circuit P of the prior art is set to the "low" signal, The initial state of the circuit system can be set while the signal level at the signal output section OUT of the power-on reset circuit P of the related art is inverted from the "low" signal to the "high" signal after the supply is started.

In order for the prior art power-on reset circuit P to set the initial state of the circuit system, the signal level at the signal output section OUT of the power-on reset circuit P always becomes a "low" signal, and the power supply voltage It is necessary to invert to a “high” signal according to the rise. In order to surely set the initial state of the circuit system, the rise of the power supply voltage and the signal level at the signal output section OUT of the power-on reset circuit P of the prior art are “ The timing of inverting a "low" signal to a "high" signal is important.

The timing at which the signal level at the signal output section OUT of the conventional power-on reset circuit P is inverted from the "low" signal to the "high" signal depends on the resistance value of the resistor R, the capacitance value of the capacitor C, and the inverter INV. Can be changed arbitrarily to some extent by changing the threshold voltage. At this time, the threshold voltage of the inverter INV is equal to the P-channel M of the inverter INV.
It can be adjusted by changing the size and threshold voltage of the OS transistor and the N-channel MOS transistor.

For example, considering the case where the rising speed of the power supply voltage and the threshold voltage of the inverter INV are constant, the capacitor C is charged with the electric charge which is the potential of the high potential side power supply VDD in the initial state when the power supply voltage is started. I do. At this time, if the capacitance value of the capacitor C increases, the amount of charge charged to the capacitor C increases, and if the capacitance value of the capacitor C decreases, the amount of charge charged to the capacitor C decreases. The amount of charge to be charged can be increased or decreased.

Next, the electric charge which is the potential of the high-potential power supply VDD charged in the capacitor C is discharged to the low-potential power supply VSS via the resistor R. At this time, if the resistance value of the resistor R increases, the time until the electric charge is completely discharged from the capacitor C via the resistance R increases, and if the resistance value of the resistor R decreases, the electric charge is discharged from the capacitor C via the resistance R. The time to complete the discharge is shortened. This is because the electric charge that is the potential of the high-potential power supply VDD charged in the capacitor C is discharged as a current to the low-potential power supply VSS. This is because the amount of current is limited by the size.

That is, the resistor R and the capacitor C are connected in series between the high potential power supply VDD and the low potential power supply VSS,
When the resistor R is connected to the high-potential power supply VDD and the capacitor C is connected to the low-potential power VSS, the resistor R
And the potential at the connection point of the capacitor C changes according to a time constant defined by the product of the resistance value of the resistor R and the capacitance value of the capacitor C.

For this reason, when the rising speed of the power supply voltage and the threshold voltage of the inverter INV are constant, the potential at the connection point between the resistor R and the capacitor C, that is, the potential of the input signal to the inverter INV becomes higher than the potential of the high potential side power supply VDD. The timing of passing the threshold voltage of the inverter INV can be changed while changing from the potential to the potential of the low potential side power supply VSS.

The rising speed of the power supply voltage and the resistance R
Considering the case where the resistance value of the inverter C and the capacitance value of the capacitor C are constant, changing the threshold voltage of the inverter INV allows the signal output portion OUT to respond to the input potential of the inverter INV, which is the potential at the connection point between the resistor R and the capacitor C. The timing at which the signal level is inverted can be adjusted.

That is, the timing at which the signal level at the signal output portion OUT of the power-on reset circuit P of the prior art is inverted from the "low" signal to the "high" signal is determined by the resistance of the power-on reset circuit P of the prior art. R, the capacitor C, and the inverter INV can be changed to some extent arbitrarily. If a resistance value, a capacitance value, and a threshold voltage suitable for a circuit system using the power-on reset circuit P of the related art are selected, the power supply at the start of power supply can be obtained. You can set the initial state.

However, when the rising speed of the power supply voltage varies due to factors described later, the resistance value of the resistor R, the capacitance value of the capacitor C, the threshold voltage of the inverter INV, and the threshold voltage of the inverter INV constitute the power-on reset circuit P of the prior art. And the timing at which the signal level at the signal output section OUT of the power-on reset circuit P is inverted from a "low" signal to a "high" signal cannot be adjusted. .

Here, the rising speed of the power supply voltage is
It means the time from the start of power supply until the potential of the power supply voltage reaches a stable potential.However, a normal battery is used as the power supply for mobile communication equipment. Power is supplied to the circuit system via the circuit. Therefore, when the rising characteristics of the battery and the regulator circuit are different, the time required for the power supply voltage to rise varies.

The timing at which the signal level at the signal output section OUT of the conventional power-on reset circuit P is inverted from a "low" signal to a "high" signal is determined by a time constant of a resistor R and a capacitor C. For this reason, if the rise time of the power supply voltage varies, the timing at which the signal level at the signal output portion OUT reverses also varies.

Also, the power source of the mobile communication device is usually
A circuit called a decoupling circuit for preventing mutual interference caused by noise or the like in each circuit block is provided. The decoupling circuit has a configuration of an integrating circuit using a resistor and a capacitor. For this reason, the rise of the power supply voltage is further slowed down by the influence of the integration circuit.
The potential at the connection point between the capacitor C and the low-side power supply V
The potential of the signal changes to be equal to the potential of SS, and the signal output unit OU
The signal level at T outputs a "high" signal after power supply is started.

That is, the power-on reset circuit P of the prior art depends on the rising speed of the power supply voltage. For this reason, in order to use the power supply having different rising characteristics, it is necessary to adjust the circuit constant to be suitable for the power supply, and the circuit system lacks versatility when used in many mobile communication devices.

[Description of Other Prior Art: FIG. 8] A conventional power-on reset circuit different from the above description will be described. FIG. 8 is a circuit diagram showing another conventional power-on reset circuit P. The other conventional power-on reset circuit P shown in FIG. 8 does not depend much on the rising speed of the power supply voltage.

The configuration of the prior art power-on reset circuit P shown in FIG. 8 is such that a resistor R and an N-channel MOS transistor NMS are composed of a high potential power supply VDD and a low potential power supply VS.
S are connected in series, the connection point of the resistor R and the N-channel MOS transistor NMS is connected to the gate of the N-channel MOS transistor NMS and the input of the inverter INV, and the output of the inverter INV is used as the signal output section OUT. Here, the N-channel MOS transistor NMS has a diode connection of the MOS transistor to which the gate and the drain are connected.

In FIG. 8, the resistor R is connected to the high potential side power supply VD.
N side MOS transistor NMS connected to D side
Are connected to the low-potential-side power supply VSS side.
However, the P-channel MOS transistor PMS is connected to the high-potential power supply VDD, and the resistor R is connected to the low-potential power supply VS.
Connected to the S side, and the connection point between the resistor R and the P-channel MOS transistor PMS is the P-channel MOS transistor PMS.
There is also a configuration to connect to the MS gate. Here, the gate and the drain of the P-channel MOS transistor PMS are diode-connected to the MOS transistor.

There is also a configuration in which the diode connection of the MOS transistor in which the gate and the drain of the N-channel MOS transistor NMS are connected or the diode connection of the MOS transistor in which the gate and the drain of the P-channel MOS transistor PMS are connected are replaced with a diode.

Next, the operation of another conventional power-on reset circuit P shown in FIG. 8 will be described. Note that the potential of the high-potential-side power supply VDD is called “high” and the low-potential-side potential VSS is called “low”.

When power supply is started, the resistor R and the N-channel MOS transistor NMS are initially set.
Is the potential of the high-potential-side power supply VDD, the "high" signal is input to the inverter INV, and the signal output section OUT, which is the output of the inverter INV, is "low".
Output a signal. Next, since the N-channel MOS transistor NMS used in the power-on reset circuit P of the prior art is a diode connection of a MOS transistor in which the gate and the drain of the N-channel MOS transistor NMS are connected, the resistance R and the N-channel M
When the potential at the connection point of the OS transistor NMS is the potential of the high-potential-side power supply VDD, a forward current flows through the diode connection of the N-channel MOS transistor NMS.

Therefore, the potential at the connection point between the resistor R and the N-channel MOS transistor NMS changes from the potential of the high potential power supply VDD to the potential of the low potential power supply VSS. Therefore, the signal level input to the inverter INV also changes from the "high" signal to the "low" signal, and the signal output section OUT, which is the output of the inverter INV, outputs the "high" signal. At this time, the signal level at the signal output section OUT is inverted from the “low” signal to the “high” signal when the input signal passes the threshold potential of the inverter INV.

Here, if the logic of the peripheral circuit is designed so that the initial state of the circuit system is set while the signal level at the signal output section OUT of the power-on reset circuit P of the prior art is set to a "low" signal, The initial state of the circuit system can be set while the signal level at the signal output OUT of the other conventional power-on reset circuit P is inverted from the "low" signal to the "high" signal after the supply is started.

This prior art power-on reset circuit P
In order to set the initial state of the circuit system, the signal level at the signal output section OUT of the power-on reset circuit P must be a "low" signal, and must be inverted to a "low" signal as the power supply voltage rises. In order to surely set the initial state of the circuit system, the rising of the power supply voltage and the signal level at the signal output section OUT of the other conventional power-on reset circuit P are inverted from a "low" signal to a "high" signal. Timing is important.

This prior art power-on reset circuit P
The timing at which the signal level at the signal output section OUT changes from a "low" signal to a "high" signal is changed by changing the resistance value of the resistor R, the size and threshold voltage of the N-channel MOS transistor NMS, and the threshold voltage of the inverter INV. Can be changed to some extent. At this time, the threshold voltage of the inverter INV is changed to the P-channel MO constituting the inverter INV.
It can be adjusted by changing the size and threshold voltage of the S transistor and the N channel MOS transistor.

FIG. 8 shows an N-channel MOS
Although only one stage of the diode connection of the transistor NMS is used, the timing at which the signal level at the signal output section OUT of the other conventional power-on reset circuit P is inverted can be changed by increasing the number of stages.

For example, considering the case where the rising speed of the power supply voltage and the threshold voltage of inverter INV are constant, the potential at the connection point between resistor R and N-channel MOS transistor NMS is high in the initial state of starting the supply of the power supply voltage. This is the potential of the potential side power supply VDD.
In the initial state, the voltage applied between the source and the drain of the N-channel MOS transistor NMS is small.
Does not allow current to flow in the forward direction.

When the power supply voltage increases with the passage of time, the voltage applied between the source and the drain of the N-channel MOS transistor NMS also increases, and the diode connection of the N-channel MOS transistor NMS is turned on in the forward direction. Therefore, a forward current flows, and the potential at the connection point between the resistor R and the N-channel MOS transistor NMS becomes the potential of the lower potential power supply VSS.

At this time, the potential at the connection point between the resistor R and the N-channel MOS transistor NMS is determined by dividing the power supply voltage by the resistor R and the N-channel MOS transistor NMS. Therefore, if the resistance value of the resistor R is large,
The potential at the connection point between the resistor R and the N-channel MOS transistor NMS becomes closer to the low potential power supply VSS, and the voltage applied between the source and the drain of the N-channel MOS transistor NMS becomes smaller. The time required for the forward current to flow through the diode connection increases.

Conversely, if the resistance value of the resistor R is small, the potential at the connection point between the resistor R and the N-channel MOS transistor NMS becomes far from the low-potential-side power supply VSS, and the potential between the source and the drain of the N-channel MOS transistor NMS is reduced. Also increases. Therefore, N
The time required for a forward current to flow through the diode connection of the channel MOS transistor NMS is reduced.

The N-channel MOS transistor N
If the size is increased by changing the channel length or channel width of the MS, the N-channel MOS transistor N
The time required for the forward current to flow through the diode connection of the MS becomes longer.
The time required for a forward current to flow through the diode connection of the transistor NMS is reduced.

When the threshold voltage of N-channel MOS transistor NMS is increased, N-channel MOS
The time required for a forward current to flow through the diode connection of the transistor NMS becomes longer, and when the threshold voltage is reduced, the time required for a forward current to flow through the diode connection of the N-channel MOS transistor NMS becomes shorter.

The N-channel MOS transistors NMS are connected in series and provided between the resistor R and the low-potential-side power supply VSS, and the number of diode-connected N-channel MOS transistors NMS connected in series is increased.
N-channel MOS transistor N connected in series
The forward current flowing through the diode connection of the MS can be reduced and the time can be prolonged.

That is, the resistor R and the N-channel MOS transistor NMS are connected in series between the high-potential power supply VDD and the low-potential power supply VSS, and the resistor R is connected to the high-potential power supply VMS.
N-channel MOS transistor NMS connected to DD side
Is connected to the low-potential-side power supply VSS side, the potential at the connection point between the resistor R and the N-channel MOS transistor NMS is obtained by dividing the power supply voltage by the resistor R and the N-channel MOS transistor NMS.

For this reason, when the rising speed of the power supply voltage and the threshold voltage of the inverter INV are constant, the potential at the connection point between the resistor R and the N-channel MOS transistor NMS, that is, the potential of the input signal to the inverter INV becomes higher than the power supply voltage. The timing of passing the threshold voltage of the inverter INV can be changed while the potential of VDD changes to the potential of the lower potential power supply VSS.

The rising speed of the power supply voltage and the resistance R
Considering the case where the resistance of the inverter INV and the characteristics of the N-channel MOS transistor NMS are constant, changing the threshold voltage of the inverter INV changes the input potential of the inverter INV, which is the potential at the connection point between the resistor R and the N-channel MOS transistor NMS. Signal output section O
The timing at which the signal level of the UT is inverted can be adjusted.

That is, the timing at which the signal level at the signal output OUT of the other prior art power-on reset circuit P is inverted from a "low" signal to a "high" signal is determined by the configuration of the prior art power-on reset circuit P. By selecting a circuit constant that can be arbitrarily changed to some extent by the resistor R, the N-channel MOS transistor NMS, and the inverter INV, and is suitable for other circuit systems using the power-on reset circuit P of the related art, an initial value at the start of power supply can be obtained. You can set the state.

The power-on reset circuit P of the prior art shown in FIG.
Since the output of the NV is inverted, even if the rising speed of the power supply voltage changes, only a slight shift in timing occurs, and no problem occurs in the operation of the power-on reset circuit.

However, when the magnitude of the power supply voltage varies, a resistor R and an N-channel MOS transistor NMS constituting another power-on reset circuit P of the prior art are used.
It is not possible to adjust the rise speed of the power supply voltage and the timing at which the signal level at the signal output section OUT of the power-on reset circuit P is inverted from a "low" signal to a "high" signal by setting the circuit constant of the inverter INV. .

Here, the variation in the power supply voltage means that a battery is usually used as the power supply of the mobile communication device, and the power supply from the battery is used directly or the power is supplied to the circuit system via a regulator circuit. The power supply voltage supplied to the circuit system varies due to manufacturing variations and mounting of the regulator circuit.

The signal level at the signal output section OUT of the other conventional power-on reset circuit P is "low".
Since the timing at which the signal is inverted to a "high" signal is determined by the voltage division of the power supply voltage by the resistor R and the N-channel MOS transistor NMS, when the power supply voltage varies, the timing at which the signal level at the signal output section OUT inverts also varies. .

This is because the voltage dependence of the diode connection of the N-channel MOS transistor NMS is large. It is desirable that the power-on reset circuit sets the initial state of the circuit system as long as possible while the power supply voltage is rising. For example, when the power supply voltage is 5.
If the power-on reset circuit for setting the circuit constants for 0 V is used as it is when the power supply voltage is 3.0 V, the forward current flowing through the diode connection of the N-channel MOS transistor NMS is small and the resistor R and the N-channel MOS transistor The potential at the connection point of the NMS does not pass through the threshold voltage of the inverter INV, and the signal level at the signal output section OUT outputs a "low" signal even when the power supply voltage rises.

In other words, since the power-on reset circuit P of the other prior art depends on the power supply voltage, if the power supply voltage is different or the power supply voltage varies, it is necessary to adjust the circuit constant to a circuit constant suitable for the power supply. When the circuit system is used for many mobile communication devices, it lacks versatility. Furthermore, if the power supply voltage is reduced in order to reduce the power consumption of the mobile communication device in the future, no forward current flows through the diode connection of the N-channel MOS transistor NMS, and the other conventional power-on reset circuit P cannot operate. .

[0059]

When the current consumption is reduced in a mobile communication device such as a mobile phone or a PHS, in order to reduce the power consumption during the standby time, the power supply to the electronic device components is performed during the standby time during the standby time. In the voltage supply stop and the standby operation time, the power supply to the electronic device components is repeatedly started to minimize power consumption.

FIG. 7 shows that the rising speed of the power supply voltage varies or changes with respect to the specification in which the electronic device components used in the mobile communication device become stable in a short time after the power is turned on. In the power-on reset circuit P of the related art, the output signal largely depends on the variation of the rising speed of the power supply voltage, and when the rising speed of the power supply voltage is reduced, the power-on reset circuit P of the related art cannot operate. is there.

When the magnitude of the power supply voltage varies or changes, in the other conventional power-on reset circuit P shown in FIG. 8, the output signal greatly depends on the variation in the magnitude of the power supply voltage. When the power supply voltage decreases in order to reduce the power consumption of the device, there is a problem that the power-on reset circuit P of the second related art cannot operate.

[Purpose of the Invention] An object of the present invention is to satisfy the requirement that a stable state can be achieved in a short time after starting supply of power supply voltage to electronic equipment parts used in mobile communication equipment. An object of the present invention is to provide a power-on reset circuit capable of performing a stable operation even when the rising speed or the magnitude of the power supply voltage varies or changes.

[0063]

In order to achieve the above object, the configuration of a power-on reset circuit according to the present invention is as follows.

The power-on reset circuit according to the present invention
It is characterized by having a capacitor and a variable resistor whose resistance value changes monotonically with an increase in the power supply voltage.

The power-on reset circuit according to the present invention
It is characterized by having a capacitor and a variable resistor whose resistance value changes monotonically with an increase in the power supply voltage, wherein the variable resistor is constituted by a MOS transistor.

The power-on reset circuit according to the present invention
It has a capacitor and a variable resistor whose resistance value changes monotonously with an increase in power supply voltage, and the variable resistor is configured by a diode connection of a MOS transistor.

The power-on reset circuit according to the present invention
It has a capacitor and a variable resistor whose resistance value changes monotonically with an increase in the power supply voltage. The variable resistance is constituted by a MOS transistor and a potential level that changes monotonically with an increase in the power supply voltage.

The power-on reset circuit according to the present invention
It has a capacitor and a variable resistor whose resistance value changes monotonically with an increase in the power supply voltage, and the variable resistance uses a potential level that changes monotonically with an increase in the power supply voltage as a gate voltage of the MOS transistor.

[Operation] The power-on reset circuit of the present invention has a capacitor and a variable resistor whose resistance value changes monotonically with an increase in the power supply voltage. The resistance of MOS is a potential level that changes monotonically with the increase of the power supply voltage.
The gate voltage of the transistor.

With this configuration, the power-on reset circuit of the present invention can stably set the initial state of the circuit system even if there is variation or fluctuation in the rising speed of the power supply voltage and the magnitude of the power supply voltage.

[0071]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a power-on reset circuit according to an optimum embodiment of the present invention will be described below with reference to the drawings.

[Description of First Embodiment of the Present Invention: FIG.
FIG. 2] First, a first embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a circuit diagram showing a configuration of the power-on reset circuit P according to the first embodiment of the present invention.

A power-on reset circuit P according to the first embodiment of the present invention shown in FIG. 1 connects a high-potential power supply VDD to one terminal of a capacitor C, and connects the other terminal of the capacitor C to an N-channel MOS transistor. The source and the bulk of the N-channel MOS transistor NMS are connected to the lower potential power supply VSS, the drain of the N-channel MOS transistor NMS is connected to the input of the inverter INV, and the inverter INV
Is provided with a signal output section OUT.

Next, the operation of the power-on reset circuit P according to the first embodiment of the present invention shown in FIG. 1 will be described.

When the supply of the power supply voltage is started, in the initial state, the capacitor C is charged with the electric charge which is the potential of the high-potential-side power supply VDD, a "high" signal is input to the inverter INV, and the output is the output of the inverter INV. The signal output section OUT outputs a "low" signal. Next, capacitor C
Is discharged to the low-potential power supply VSS via the diode-connected N-channel MOS transistor NMS, and the signal level input to the inverter INV changes from the “high” signal to the low-potential power supply VDD. The signal changes to a “low” signal, and the signal signal output section OUT, which is the output of the inverter INV, outputs a “high” signal. At this time, the signal level at the signal output unit OUT is inverted from the “low” signal to the “high” signal when the input signal passes the threshold potential of the inverter INV.

In the variable resistor VR used in the power-on reset circuit P according to the first embodiment of the present invention, the N-channel MOS transistor NMS has a diode connection of a MOS transistor whose gate and drain are connected. Therefore, when the potential at the connection point between the capacitor C and the variable resistor VR is the potential of the high-potential-side power supply VDD, a forward current flows through the diode connection of the N-channel MOS transistor NMS.

Therefore, the capacitor C and the variable resistor VR
At the connection point of the inverter INV changes from the potential of the high-potential power supply VDD to the potential of the low-potential power supply VSS.
Also changes from a "high" signal to a "low" signal, and the signal output section O which is the output of the inverter INV.
The UT outputs a "high" signal. At this time, the signal level at the signal output section OUT changes from the “low” signal to the “high”
Inversion to a signal occurs when the input signal passes through the threshold potential of the inverter INV.

Here, the logic of the peripheral circuit is set such that the initial state of the circuit system is set while the signal level at the signal output section OUT of the power-on reset circuit P in the first embodiment of the present invention is a "low" signal. When designing
The initial state of the circuit system is changed while the signal level at the signal output section OUT of the power-on reset circuit P of the first embodiment of the present invention is inverted from the "low" signal to the "high" signal after the power supply is started. Can be set.

In order for the power-on reset circuit P of the first embodiment of the present invention to set the initial state of the circuit system, the signal output section OUT of the power-on reset circuit P of the first embodiment of the present invention requires The signal level always becomes a "low" signal, and must be inverted to a "low" signal in accordance with the rise of the power supply voltage. In order to reliably set the initial state of the circuit system, the rise of the power supply voltage and the present invention The timing at which the signal level at the signal output portion OUT of the power-on reset circuit P of the first embodiment is inverted from a “low” signal to a “high” signal is important.

The timing at which the signal level at the signal output section OUT of the power-on reset circuit P of the first embodiment of the present invention is changed from a "low" signal to a "high" signal depends on the capacitance value of the capacitor C and the N-channel MOS. It can be arbitrarily changed by changing the size of the transistor NMS, the threshold voltage, and the threshold voltage of the inverter INV. At this time, the threshold voltage of the inverter INV can be adjusted by changing the size and threshold voltage of the P-channel MOS transistor and the N-channel MOS transistor constituting the inverter INV.

Although only one diode connection of the N-channel MOS transistor NMS is used in FIG. 1, the signal output section OUT of the power-on reset circuit P according to the first embodiment of the present invention can be increased by increasing the number of stages. The timing at which the signal level is inverted can be changed.

For example, considering the case where the rising speed of the power supply voltage and the threshold voltage of inverter INV are constant, the potential at the connection point between capacitor C and variable resistor VR is high on the high potential side in the initial state of starting the power supply. This is the potential of the power supply VDD. In the initial state, the voltage between the source and the drain of the N-channel MOS transistor NMS is small, so that the diode connection of the N-channel MOS transistor NMS does not allow a current to flow in the forward direction.

When the power supply voltage increases with the passage of time, the voltage between the source and drain of N-channel MOS transistor NMS also increases, and the diode connection of N-channel MOS transistor NMS turns on in the forward direction, so that a forward current flows. , Capacitor C and variable resistor VR
Becomes the potential of the lower potential power supply VSS.

At this time, the potential at the connection point between the capacitor C and the variable resistor VR is determined by the amount of charge which is the potential of the high-potential power supply VDD charged in the capacitor C and the potential of the N-channel M
It is determined by the amount of current flowing through the variable resistor VR formed by the diode connection of the OS transistor NMS. For this reason, when the capacitance value of the capacitor C is large, a forward current flows through the diode connection of the N-channel MOS transistor NMS, and the time required for the potential at the connection point between the capacitor C and the variable resistor VR to reach the low-potential-side power supply VSS becomes long. Become.

Conversely, if the capacitance value of the capacitor C is small, a forward current flows through the diode connection of the N-channel MOS transistor NMS, and the potential at the connection point between the capacitor C and the variable resistor VR changes to the low potential side power supply VSS. The time to become shorter.

The N-channel MOS transistor N
If the size is increased by changing the channel length or channel width of the MS, the N-channel MOS transistor N
A forward current flows through the diode connection of the MS, and the time required for the potential at the connection point between the capacitor C and the variable resistor VR to reach the low-potential-side power supply VSS is prolonged. Forward current flows, capacitor C and variable resistor VR
The time required for the potential at the connection point to become the low potential power supply VSS is shortened.

When the threshold voltage of N-channel MOS transistor NMS is increased,
When a forward current flows through the diode connection of the transistor NMS, the time required for the potential at the connection point between the capacitor C and the variable resistor VR to reach the low-potential-side power supply VSS increases, and when the threshold voltage is reduced, the diode connection of the N-channel MOS transistor NMS increases. , The time required for the potential at the connection point between the capacitor C and the variable resistor VR to reach the low-potential-side power supply VSS is shortened.

Then, an N-channel MOS transistor NMS is connected in series, and a capacitor C and a low potential side power source VS
S, an N-channel MOS transistor NMS
By increasing the number of serially connected diode connections, the forward current flowing through the diode connection of the N-channel MOS transistors NMS connected in series can be reduced and the time can be prolonged.

Here, the capacitor C and the N-channel MO
The diode connection of the S transistor NMS is connected in series between the high-potential power supply VDD and the low-potential power supply VSS, the capacitor C is connected to the high-potential power supply VDD, and the N-channel MOS transistor NMS is connected to the low-potential power supply VSS. , The potential at the connection point between the capacitor C and the variable resistor VR depends on the amount of current flowing through the variable capacitor VR.

Therefore, when the rising speed of the power supply voltage and the threshold voltage of the inverter INV are constant, the potential at the connection point between the capacitor C and the variable resistor VR, that is, the potential of the input signal to the inverter INV becomes higher than that of the high-potential-side power supply VDD. While the potential changes from the potential to the potential of the low potential power supply VSS, the timing of passing the threshold voltage of the inverter INV can be changed.

Further, considering the case where the rising speed of the power supply voltage, the capacitance value of the capacitor C, and the characteristics of the N-channel MOS transistor NMS are constant, changing the threshold voltage of the inverter INV changes the capacitor C and the variable resistor VR. The timing at which the signal level of the signal output unit OUT is inverted with respect to the input potential of the inverter INV, which is the potential at the connection point, can be adjusted.

In the power-on reset circuit P according to the first embodiment of the present invention, the power supply voltage is divided by the capacitor C and the variable resistor VR to invert the output of the inverter INV. Does not cause a problem in the operation of the power-on reset circuit, even if the power-on reset circuit surely becomes the low-potential-side power supply VSS and the rising speed of the power supply voltage changes.

Further, since the resistance value of the capacitor C constituting the power-on reset circuit P of the first embodiment of the present invention is infinite, it always works as a resistance value larger than the resistance value of the variable resistor VR. Even if the potential level at the connection point between the capacitor and the variable capacitor VR surely becomes the lower potential power supply VSS and the magnitude of the power supply voltage varies, no problem occurs in the operation of the power-on reset circuit.

If the power-on reset circuit P of the first embodiment of the present invention is used, there is a demand that a stable state can be attained in a short time after the supply of the power supply voltage to the electronic equipment parts used in the mobile communication equipment is started. It is possible to provide a circuit system which satisfies and can perform a stable operation even if the rising speed of the power supply voltage or the magnitude of the power supply voltage varies or changes.

The power-on reset circuit P according to the first embodiment of the present invention shown in FIG. 2 connects the high-potential-side power supply VDD to the source and the bulk of the P-channel MOS transistor PMS, and Is connected to the gate and the drain of the P-channel MOS transistor PMS, and the other terminal of the capacitor C is connected to the low potential side power supply V.
SS, P-channel MOS transistor PMS
Is connected to the input of the inverter INV, and the output of the inverter INV is provided with a signal output section OUT.

The power-on reset circuit P of the first embodiment of the present invention shown in FIG.
Has the same effect as the power-on reset circuit P of the first embodiment of the present invention.

[Description of Second Embodiment of the Invention: FIG.
FIG. 4] Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 is a circuit diagram showing a configuration of the power-on reset circuit P according to the second embodiment of the present invention.

As shown in FIG. 3, in the power-on reset circuit P according to the third embodiment of the present invention, the high-potential power supply VDD is connected to one terminal of the capacitor C, and the other terminal of the capacitor C is connected to the other terminal. The drain of the N-channel MOS transistor NMS is connected, the source and bulk of the N-channel MOS transistor NMS are connected to the low-potential power supply VSS, and the first resistor R1 is connected between the high-potential power supply VDD and the low-potential power supply VSS. A second resistor R2 is connected in series, and a connection point between the first resistor R1 and the second resistor R2 is connected to the gate of the N-channel MOS transistor NMS.
The drain of the channel MOS transistor NMS is connected to the input of the inverter INV, and a signal output section OUT is provided at the output of the inverter INV.

Next, the operation of the power-on reset circuit P according to the second embodiment of the present invention shown in FIG. 3 will be described.

When the supply of the power supply voltage is started, in the initial state, the capacitor C is charged with the electric charge which is the potential of the high-potential-side power supply VDD, a "high" signal is input to the inverter INV, and the output is the output of the inverter INV. The signal output section OUT outputs a "low" signal. Next, the electric charge, which is the potential of the high-potential power supply VDD charged in the capacitor C, is discharged to the low-potential power supply VSS via the N-channel MOS transistor NMS, and the signal level input to the inverter INV is a “high” signal. Changes to a “low” signal,
The signal output section OUT, which is the output of the inverter INV, outputs a "high" signal. At this time, the signal output unit O
The signal level at the UT is inverted from a "low" signal to a "high" signal when the input signal passes the threshold potential of the inverter INV.

The variable resistor VR used in the power-on reset circuit P according to the second embodiment of the present invention is configured such that the N-channel MOS transistor NMS uses the power supply voltage as the first resistor R
The voltage is divided by the first and second resistors R2, applied to the gate of the N-channel MOS transistor NMS, and used as the MOS transistor resistance. Therefore, the capacitor C and the variable resistor V
If the potential at the connection point of R is the potential of the high-potential-side power supply VDD, a current flows through the N-channel MOS transistor NMS.

Therefore, the potential at the connection point between the capacitor C and the variable resistor VR changes from the potential of the high-potential power supply VDD to the potential of the low-potential power supply VSS.
The signal level input to NV also changes from a “high” signal to a “low” signal.
The signal output section OUT, which is the output of the inverter INV, outputs a "high" signal. At this time, the signal level at the signal output section OUT is inverted from the “low” signal to the “high” signal because the input signal is inverted by the inverter I.
This is when passing the threshold potential of NV.

Here, the logic of the peripheral circuit is set such that the initial state of the circuit system is set while the signal level at the signal output section OUT of the power-on reset circuit P in the second embodiment of the present invention is a "low" signal. When designing
After the power supply is started, the initial state of the circuit system is changed while the signal level at the signal output section OUT of the power-on reset circuit P of the second embodiment of the present invention is inverted from a “low” signal to a “high” signal. Can be set.

In order for the power-on reset circuit P according to the second embodiment of the present invention to set the initial state of the circuit system, the signal output section OUT of the power-on reset circuit P according to the second embodiment of the present invention is required. The signal level always becomes a "low" signal and must be inverted to a "low" signal according to the rise of the power supply voltage. In order to surely set the initial state of the circuit system, the rise of the power supply voltage and the second embodiment of the present invention The timing at which the signal level at the signal output section OUT of the power-on reset circuit P of the fifth embodiment is inverted from a "low" signal to a "high" signal is important.

The timing at which the signal level at the signal output section OUT of the power-on reset circuit P of the second embodiment of the present invention is inverted from a "low" signal to a "high" signal depends on the capacitance value of the capacitor C and the N-channel MOS. It can be arbitrarily changed by changing the size of the transistor NMS, the threshold voltage, and the threshold voltage of the inverter INV. At this time, the threshold voltage of the inverter INV can be adjusted by changing the size and threshold voltage of the P-channel MOS transistor and the N-channel MOS transistor constituting the inverter INV.

Although only one stage of the N-channel MOS transistor NMS is used in FIG. 1, the signal level at the signal output section OUT of the power-on reset circuit P according to the second embodiment of the present invention can be increased by increasing the number of stages. Can be changed.

For example, considering the case where the rising speed of the power supply voltage and the threshold voltage of inverter INV are constant, the potential at the connection point between capacitor C and variable resistor VR is high in the initial state when the power supply is started. This is the potential of the side power supply VDD. Further, in the initial state, since the gate voltage of the N-channel MOS transistor NMS and the voltage between the source and drain are small, current cannot flow through the N-channel MOS transistor NMS.

When the power supply voltage increases with the passage of time, the voltage between the source and the drain of N-channel MOS transistor NMS also increases, and the power supply voltage is reduced by first resistor R
N-channel MOS divided by 1 and second resistor R2
The gate voltage of the transistor NMS also increases,
The N-channel MOS transistor NMS is turned “on”, the resistance value as the MOS transistor resistance decreases and a current flows, and the potential at the connection point between the capacitor C and the variable resistor VR becomes the potential of the low potential power supply VSS.

At this time, the potential at the connection point between the capacitor C and the variable resistor VR is determined by the amount of charge that is the potential of the high-potential power supply VDD charged in the capacitor C, the first resistor R1 and the second resistor Since it is determined by the amount of current flowing through the variable resistor VR formed by R2 and the N-channel MOS transistor NMS, if the capacitance value of the capacitor C is large, a current flows through the N-channel MOS transistor NMS and the capacitor C
The potential at the connection point between the power supply and the variable resistor VR is the low potential side power supply V.
The time to become SS becomes longer.

Conversely, if the capacitance value of the capacitor C is small, a current flows through the N-channel MOS transistor NMS, and the time required for the potential at the connection point between the capacitor C and the variable resistor VR to reach the low-potential-side power supply VSS is obtained. Be shorter.

The N-channel MOS transistor N
If the size is increased by changing the channel length or channel width of the MS, the N-channel MOS transistor N
A longer time is required for the current to flow through MS until the potential at the connection point between the capacitor C and the variable resistor VR becomes the low-potential-side power supply VSS. When the size is reduced, a current flows through the N-channel MOS transistor NMS and the capacitor C and the variable resistor VR The time required for the potential at the connection point to become the low potential power supply VSS is shortened.

When the threshold voltage of N-channel MOS transistor NMS is increased,
When a current flows through the transistor NMS, the potential at the connection point between the capacitor C and the variable resistor VR is reduced to the lower potential power supply VS.
When the threshold voltage is reduced, the time required for the current to flow through the N-channel MOS transistor NMS decreases, and the time required for the potential at the connection point between the capacitor C and the variable resistor VR to reach the low-potential-side power supply VSS decreases.

Then, an N-channel MOS transistor NMS is connected in series, and a capacitor C and a low-potential-side power supply VS are connected.
S, an N-channel MOS transistor NMS
By increasing the number of serially connected diode-connected stages, the current flowing through the N-channel MOS transistors NMS connected in series can be reduced and the time can be prolonged.

The power supply voltage is divided to obtain an N-channel MO.
A first resistor R applied to the gate of the S transistor NMS
Even if the ratio between the first and second resistors R2 is changed, the N channel M
The time flowing can be changed by adjusting the current flowing through the OS transistor NMS.

Here, the capacitor C and the N-channel MO
The MOS transistor resistance of the S transistor NMS is connected in series between the high-potential power supply VDD and the low-potential power supply VSS, the capacitor C is connected to the high-potential power supply VDD, and the N-channel MOS transistor NMS is connected to the low-potential power supply VS.
In the case of connecting to the S side, the potential at the connection point between the capacitor C and the variable resistor VR depends on the amount of current flowing through the variable capacitor VR.

For this reason, when the rising speed of the power supply voltage and the threshold voltage of the inverter INV are constant, the potential at the connection point between the capacitor C and the variable resistor VR, that is, the potential of the input signal to the inverter INV becomes the potential of the high potential power supply VDD. From the threshold voltage of the inverter INV to the low-potential-side power supply VSS.

Considering the case where the rising speed of the power supply voltage, the capacitance value of the capacitor C, and the characteristics of the variable resistor VR are constant, the connection point between the capacitor C and the variable resistor VR is changed by changing the threshold voltage of the inverter INV. The timing at which the signal level of the signal output section OUT is inverted with respect to the input potential of the inverter INV, which is the potential at the point, can be adjusted.

The power-on reset circuit P according to the second embodiment of the present invention uses a power supply voltage of a capacitor C and a variable resistor VR.
And the output of the inverter INV is inverted. Therefore, the potential level input to the inverter INV surely becomes the low-potential-side power supply VSS, and even if the rising speed of the power supply voltage changes, only a slight shift occurs in the timing, and there is no problem in the operation of the power-on reset circuit. Does not happen.

Further, since the resistance value of the capacitor C constituting the power-on reset circuit P of the second embodiment of the present invention is infinite, it always acts as a resistance larger than the resistance value of the variable resistor VR, and Even if the potential level at the connection point between the capacitor and the variable capacitor VR surely becomes the lower potential power supply VSS and the magnitude of the power supply voltage varies, no problem occurs in the operation of the power-on reset circuit.

When the power-on reset circuit P according to the second embodiment of the present invention is used, there is a demand that a stable state can be attained in a short time after the supply of the power supply voltage to the electronic device components used in the mobile communication device is started. It is possible to provide a circuit system which satisfies and can perform a stable operation even if the rising speed of the power supply voltage or the magnitude of the power supply voltage varies or changes.

The power-on reset circuit P according to the second embodiment of the present invention shown in FIG.
DD is connected to one terminal of a capacitor C, and the other terminal of the capacitor C is connected to an N-channel MOS transistor NM.
S, the source and bulk of the N-channel MOS transistor NMS are connected to the low-potential power supply VSS, the high-potential power supply VDD is connected to the gate of the N-channel MOS transistor NMS, and the drain of the N-channel MOS transistor NMS is connected. Is connected to the input of the inverter INV, and a signal output section OUT is provided at the output of the inverter INV.

When the configuration of the power-on reset circuit P according to the second embodiment of the present invention shown in FIG. 3 is used, the first resistor R
By appropriately selecting the ratio of the first resistor R2 to the second resistor R2, the magnitude of the power supply voltage for ending the setting of the initial state and the time after the supply of the power supply voltage is started can be arbitrarily set. Power-on reset circuit P according to the second embodiment of the present invention
When the configuration described above is used, the circuit scale can be reduced because there is no need to use a resistor.

Further, the configuration of the power-on reset circuit P of the second embodiment of the present invention shown in FIGS. 3 and 4 and the configuration of the power-on reset circuit P of the other second embodiment of the present invention, It is also possible to provide a capacitor between the input and either or one of the high-potential-side power supply VDD and the low-potential-side power supply VSS, and delay the output of the power supply voltage detecting means with respect to the rise of the power supply voltage. .

[Description of Third Embodiment of the Present Invention: FIG.
FIG. 6] Next, a third embodiment of the present invention will be described. FIG.
FIG. 9 is a circuit diagram illustrating a configuration of a power-on reset circuit P according to a third embodiment of the present invention.

As shown in FIG. 5, in the power-on reset circuit P according to the third embodiment of the present invention, a high-potential power supply VDD is connected to the source and bulk of a P-channel MOS transistor PMS, and the P-channel MOS transistor PMS Is connected to one terminal of the capacitor C, the other terminal of the capacitor C is connected to the low-potential power supply VSS, and the first resistor R1 and the first resistor R1 are connected between the high-potential power supply VDD and the low-potential power supply VSS. , The connection point of the first resistance R1 and the second resistance R2 is connected to the gate of the P-channel MOS transistor PMS, and the drain of the P-channel MOS transistor PMS is connected to the input of the inverter INV. Then, a signal output section OUT is provided at the output of the inverter INV.

Even when the power-on reset circuit P according to the third embodiment of the present invention shown in FIG. 5 has the same configuration, the same effect as that of the power-on reset circuit P according to the second embodiment of the present invention shown in FIG. There is.

FIG. 6 is a circuit diagram showing a configuration of a power-on reset circuit P according to another third embodiment of the present invention.

In the power-on reset circuit P according to the third embodiment of the present invention shown in FIG. 6, the high-potential-side power supply VDD is connected to the source and bulk of the P-channel MOS transistor PMS, and the drain of the P-channel MOS transistor PMS is connected. The capacitor C is connected to one terminal, the other terminal of the capacitor C is connected to the low-potential power supply VSS, the low-potential power supply VSS is connected to the gate of the P-channel MOS transistor PMS, The drain is connected to the input of the inverter INV, and the signal output OUT is provided at the output of the inverter INV.

Even if the power-on reset circuit P of the third embodiment of the present invention shown in FIG.
7 has the same effects as those of the power-on reset circuit P according to the third embodiment of the present invention.

[0130]

As is apparent from the above description, the power-on reset circuit according to the present invention can be used for electronic equipment parts used in mobile communication equipment in a short time after power-on. Even if the rising speed of the power supply voltage or the magnitude of the power supply voltage varies or changes, it has a capacitor and a variable resistor whose resistance value monotonously changes as the power supply voltage increases.

Therefore, in the power-on reset circuit of the present invention, it is possible to provide a highly versatile power-on reset circuit that performs stable operation in a short time after the supply of the power supply voltage is started.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a power-on reset circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a power-on reset circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a configuration of a power-on reset circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a configuration of a power-on reset circuit according to another second embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating a configuration of a power-on reset circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a configuration of a power-on reset circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a configuration of a power-on reset circuit according to the related art.

FIG. 8 is a circuit diagram showing a configuration of a power-on reset circuit according to the related art.

[Explanation of symbols]

 P Power-on reset circuit C Capacitor VR Variable resistance NMS N-channel MOS transistor INV Inverter OUT Signal output section

Claims (5)

[Claims] 1. A power-on reset circuit comprising: a capacitor; and a variable resistor whose resistance value monotonously changes with an increase in power supply voltage. 2. A power-on reset circuit, comprising: a capacitor; and a variable resistor whose resistance value changes monotonically with an increase in power supply voltage, wherein the variable resistor is constituted by a MOS transistor. 3. A power-on reset circuit, comprising: a capacitor; and a variable resistor whose resistance value changes monotonously with an increase in power supply voltage, wherein the variable resistor is configured by a diode connection of a MOS transistor. 4. A semiconductor device comprising: a capacitor; and a variable resistor having a resistance value monotonically changing with an increase in power supply voltage, wherein the variable resistance comprises a MOS transistor and a potential level monotonically changing with an increase in power supply voltage. Characteristic power-on reset circuit. 5. A variable resistor having a capacitor and a variable resistor whose resistance value monotonically changes with an increase in power supply voltage, wherein the variable resistor uses a potential level monotonically changing with an increase in power supply voltage as a gate voltage of a MOS transistor. A power-on reset circuit.