JPH1132038A - Data transmission control circuit for integrated circuit of isdn - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit the data of the block of the respective kinds of interfaces at a high speed between B1 and B2 channels of ISDN by providing a high-speed bus inside an integrated circuit for the ISDN, using the bus in a time division manner and transferring the data. SOLUTION: For a control register CR which is a control circuit, the contents are set by the microprogram of a microprocessor CPU. The register CR controls the connection with the block LY1 of the Layer 1 (B1/B2 channel) of the ISDN through the TBus and RBus of a time division high-speed data bus of the block HDLC1 of a high level data link control circuit, the block PIAFS2 of a PHS internet forum standard and a transparent block Transparent 3 and controls the transmission and reception of the data of the connected block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission control circuit for an integrated circuit for ISDN, and more particularly to a data transmission control circuit for an ISDN B1 and B2 channel in which a time-division high-speed data bus is provided inside the integrated circuit to transmit data. The present invention relates to a data transmission control circuit.

[0002]

The ISDN integrated digital communication network is capable of communicating different media such as telephone voice, data of a computer or a communication terminal, and image data through a single communication line. It is a very convenient system that can communicate at the same time. In order to connect a conventional V interface or X interface communication device such as a voice telephone or a computer to the ISDN, a terminal adapter for converting the conventional standard into the ISDN standard is used.

In order to control communication with an ISDN communication network, this terminal adapter is provided with a data bus inside an integrated circuit to allow communication between data blocks of various interfaces and the B1 and B2 channels of the ISDN communication network. The data transmission is controlled. In the ISDN line, signals such as normal data are transferred at 64 Khz. Therefore, even within the integrated circuit for ISDN, 6
A 4 Khz data bus was used. For this reason, it is necessary to use a complicated circuit when performing a loopback test or the like. Further, when a new block is extended to an integrated circuit for ISDN, a drastic logic change is required.

[0004]

According to the present invention, a high-speed bus of 2.048 Mhz is provided inside an integrated circuit for ISDN, and this bus is used in a time-division manner to transfer data. An integrated circuit for ISDN which makes it possible to easily perform a loopback test of 64 Kbps data of the B2 channel and to enable an external PCM Codec to be directly connected to this high-speed bus, so that the expandability of a 64 Kbps data transfer block is extremely excellent. The data transmission control circuit of FIG.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a block diagram showing a configuration of a data transmission control circuit of an integrated circuit for ISDN of the present invention. FIG.
, The IC is an LSI for ISDN. The CPU is a microprocessor. CR is a control circuit, which is composed of a plurality of registers controlled by a microprocessor CPU. LY1 is an ISDN Lyer1 block. ISDN Lyer1 block LY
1 is connected to the Bl and B2 channels of the ISDN.

[0006] TBus and RBus are time-division high-speed data buses provided in the IC of the LSI for ISDN. Bus is a normal data bus of an ISDN LSI. Reference numerals 1, 2, and 3 denote interface blocks of an ISDN LSI, respectively. Block 1 is an HDLC block having a function of a high-level data link control circuit, and block 2 is a PIAF having a PHS Internet Forum standard function of processing PHS signals.
S block and block 3 have a transparent function of processing instantaneous data such as audio data.
This is a transparent block. Reference numerals 8 and 9 denote external PCM TBus and RBus, respectively.

HDL of high-level data link control circuit
The C block 1, the PIAFS block 2 of the PHS Internet Forum standard, and the transparent Transparent block 3 are respectively ISDN via the time-division high-speed data buses TBus and RBus.
Is connected to the block LY1 of Lyer1. or,
TBus and RBus of the time-division high-speed data bus are connected to TBus8 and RBus9 of the external PCM, respectively.

[0008] Microprocessor C of LSI for ISDN
The PU converts signals of different media such as telephone voice, data of a computer or a communication terminal, image data, etc., into signals corresponding to the ISDN layer 1 protocol, and connects the PU to the ISDN circuit network. The CR is set and its operation is controlled. The microprocessor CPU and the control circuit CR are connected to the HDLC block 1, the PIAFS block 2, and the Transport via the time-division high-speed data buses TBus and RBus.
nt block 3 and block LY of ISDN Lyer1
1 is controlled. .

The operation of the data transmission control circuit of the integrated circuit for ISDN according to the present invention thus constructed will be described below. The register of the control circuit CR is a register whose contents are set by a microprogram of the microprocessor CPU. According to the contents of the setting, the HDLC block 1 of the high-level data link control circuit, the PHS
Internet Forum Standard PIAFS Block 2, Transparent Transparen
t block 3 is a time-division high-speed data bus TBus, R
Block LY1 of ISDN Lyer1 via Bus
To control the transmission and reception of the data of the connected block. The register of the control circuit CR is connected to the high-speed data bus TBus or RBus by an external P bus.
It also controls the transmission and reception of data with the CM's TBus8 and RBus9.

FIG. 2 shows a time-division high-speed data bus TBu.
It is a figure which shows the flow of the signal for demonstrating operation | movement of s, RBus. Time-shared high-speed data bus TBus, RBu
s is a high-speed signal transmission line operating at a transmission speed of 2.048 MHz. Data bus TBus, RBu
s is from channel 0 to channel 31 as shown in FIG. 2A, and is set to transfer 8-bit data per channel. The transmission speed of the high-speed data bus TBus and RBus is 2.048 MHz.
Therefore, as shown in FIG. 2B, each channel can transmit data once every 125 Usec.

Since the amount of data of the data bus TBus and RBus at one time is 8 bits, the data rate of each channel is set to 64 kbps and equal to the transmission rate of the ISDN line B1 / B2 channel. Within the time of 125 us, the normal mode transfers 8-bit data, and the bulk mode transfers 16-bit data.
The transfer speed of the buffer before the PCM bus is 64K
Hz, 128 KHz, PCM bus is a 32 channel time division bus, 3.9 μs per channel, and 1 bit transfer rate is 2.048 Mbps.

In the present invention, TBus is used for transmission and RBus is used for reception. For this reason, the TBus for transmission
Includes HDLC block 1, PIAFS block 2, and Transport of interface blocks, respectively.
The transmission terminal of the nt block 3 is connected, and the ISD
It is controlled to be connected to the receiving terminal of the block LY1Layer1 of the N Lyer1, and the RBus for receiving
Includes DLC block 1, PIAFS block 2, and Transparen of the interface block, respectively.
The receiving terminal of t-block 3 is connected, and ISDN
Is controlled to be connected to the transmission terminal of the block LY1Layer1 of Lyer1. In addition, TBu for transmission
s and RBus for reception are external PCM CODEC
The data of the external PCM buses 8 and 9 that can be directly connected to the IC can also be transmitted. In this case, the external PCM T bus is TB
us and the external PCMR bus are connected only to the RBus.

Each of the blocks 1 and 2 of the above interface
TBu for transmitting and receiving terminals and transmitting data of a few data
Controlling the connection between s and the RBus for reception is a control circuit CR that allows the microprocessor CPU to read / write via the bus Bus. The control circuit CR has a transmission control register and a reception control register for each of the blocks 1, 2, and 3 of the interface, and controls the following contents.

Control contents of transmission control register 1. Transmission mode (normal mode / bulk mode) Designation of bus to send data (TBus or RBu
s) 3. 3. Data transmission permission (determination of data transmission permission / prohibition to Bus specified in 2.) PCM bus channel designation (ch0 to ch3
1) Control contents of reception control register 1. Transmission mode (normal mode / bulk mode) Designation of bus to receive data (TBus or RBu
s) 3. 3. Permission of data reception (determination of whether data reception is possible / impossible to the bus specified in 2.) PCM bus channel designation (ch0 to ch3
1)

In the normal mode, the transmission rate is 64 Kbp
s is a mode in which one of 32 channels is used. The bulk mode is continuous with the specified channel.
In this mode, a transmission rate of 128 kbps is realized using a channel. Block L of Lyner1 of ISDN
These modes are not specified in the control register for controlling the lines B1 / B2 of Y1. For example, in normal keyed,
HDLC block 1 and ISDN Lyer1 line B1
In order to transmit 64 kbps data, the transmission mode of the transmission control register of the HDLC block 1 is set to the normal mode, the bus is designated as TBUS, the data transmission is permitted, and the channel is set to 0ch. On the other hand, the bus specification of the reception control register of the line B1 of the ISDN Lyer1 is set to TBUS, data reception is permitted, and the channel is set to 0ch. This is HD
Data can be transmitted from LC block 1 to line B1 of ISDN Lyer1.

The transmission mode of the reception control register of the HDLC block 1 is a normal mode, and the bus designation is an RBu.
s, data reception is permitted, and the channel is set to 0ch. On the other hand, the bus specification of the transmission control register of the line B1 of the ISDN Lyer1 is set to RBus, data transmission is permitted, and the channel is set to 0ch. With this, the received data can be transmitted from the line B1 of the ISDN Lyer1 to the HDLC. Further, even when it is desired to return data in each of the blocks 1, 2, 3 of the interface, it can be easily realized by setting the control register. FIG. 3 shows a TBus for transmission and a RB for reception.
FIG. 10 is a diagram illustrating a relationship between a USB and an external PCM TBus8 and an RBus9. In FIG. 3, TBus and RBus are time-division high-speed data buses provided in the IC of the LSI for ISDN. 8 and 9 are external PCMs
TBus and RBus.

SL is a selector which is a bus channel ch.
0 and ch1 are connected. PCM is PCM C0DE
The C IC is connected to external PCM TBus8 and RBus9. Slots of channels other than the channel ch0 and ch1 of the RBus of the time-division high-speed data bus are connected to the external PCM RBus9, and the channels ch0 and ch1 of the RBus for reception are connected to the external PCM via the selector SL.
It is connected to CM RBus9. External PCM TB
Slots of channels not used by other blocks of us8 are connected to TBus8 of a time-division high-speed data bus, and channels ch0 and ch1 of TBus8 of external PCM are used.
Is connected to an external PCM RBus9 via a selector SL.

The external PCM TBus8 is a TB for transmission.
us and the external PCM RBus 9 are connected only to the RBus for reception. External PCM TBus8 and RBus9
The microprocessor CPU shown in FIG.
Control circuit CR that can read / write via external PC
There is an M bus control register, which controls the following contents. Control contents of external PCM bus control register 1. Transmission mode (normal mode / return mode) 2. Sync signal transmission permission synchronized with ch0 Sync signal transmission permission synchronized with ch2

In the normal mode, the data of the RBus of the time-division high-speed data bus is sent to the same channel to the external PCM RBus, and is input to the PCM C0DEC IC. Ch0 and ch2 of external PCM T / RBus
Is output from an external terminal, and the PCM C0DEC IC uses this to output ch0.
The data of c or ch2 is used. In the case of the return mode, the external PCM is passed through the selector SL.
Ch0 of TBus8 is the ch of external PCM RBus9
2 and the ch2 of the external PCM TBus8 is connected to the ch0 of the external PCM RBus9. In this way, it is possible to perform an extension call or the like between telephones connected to the ISDN LSI in the return mode.

The external PCM TBus8 sends data to the same channel of the TBus of the time-division high-speed data bus, but the HDLC block 1 of the high-level data link control circuit, the PIAFS block 2 of the PHS Internet Forum standard, and the transparent Tra
Data is not transmitted to the channel used in the nsparent block 3 and the block 1 of the ISDN Bl and B2 channels. As described above, in the present invention, two high-speed buses for transmission and reception are provided inside an LSI for ISDN, and these buses are used in a time-division manner to transfer line data. In this case, data of various interface blocks can be transmitted at a high speed, and a data return test can be easily performed. Further, according to the present invention, an external PCM Codec can be directly connected to the ISDN LSI, and a data transmission control circuit of an ISDN integrated circuit having a very excellent expandability of a 64 Kbps data transfer block can be realized. For this reason, even when adding various blocks, without changing the hardware,
Data transmission is possible.

[0021]

As is apparent from the above description, the data transmission control circuit of the integrated circuit for ISDN of the present invention is an ISD
A high-speed bus for transmitting and receiving 2.048 Mhz is provided inside the integrated circuit for N, and these buses are used in a time-division manner to transfer line data. High-speed transmission can be performed between the B1 and B2 channels.

Further, since the transmission and reception high-speed buses are provided, the data return test can be easily performed, and the external PCM Codec can be directly connected.
It is possible to realize a data transmission control circuit of an ISDN integrated circuit in which the expandability of a 4 Kbps data transfer block is extremely excellent. For this reason, the data transmission control circuit of the integrated circuit for ISDN of the present invention can transmit data without changing hardware even when a block is added. Further, since the setting of the T / R bus to be connected can be changed by the control register, the return mode and the change of the data transmission / reception path can be easily realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data transmission control circuit of an integrated circuit for ISDN of the present invention.

FIG. 2 shows a time-shared high-speed data bus TBus, RBus.
FIG. 3 is a diagram showing a signal flow for explaining the operation of FIG.

FIG. 3 shows a transmission bus, a reception Rbus, and an external P bus.
It is a figure which shows the relationship between CMTBus8 and RBus9.

[Explanation of symbols]

IC: LSI for ISDN, CPU: Microprocessor, CR: Control circuit, LY1
.... Lyser1 block of ISDN, TBus ...
A time-division high-speed data bus provided in an ISDN LSI IC, RBus ... a time-division high-speed data bus provided in an ISDN LSI IC,
1 ... HDLC block, 2 ... PIAFS
Block, 3 ... Transparent block, 8, ... TBus of external PCM,
9: RBus of external PCM, SL: Selector, PCM: PCM C0DEC IC

Claims (8)

[Claims] 1. A microprocessor for controlling connection to a layer 1 of an ISDN network, a register controlled by the microprocessor, and a high-speed time-division data bus whose operation is controlled by the register. A data transmission control circuit for an ISDN integrated circuit, wherein the data transmission control circuit is formed on the integrated circuit and controls a register by a program of a microprocessor to control a high-speed ISDN time-division data bus. 2. A microprocessor for controlling connection with a layer 1 of an ISDN circuit network, a register controlled by the microprocessor, and two high-speed transmission and reception high-speed operation controlled by the register. A time-division data bus is created on a one-chip semiconductor integrated circuit, and a register is controlled by a microprocessor program to control the IS.
I that controls a high-speed time-division data bus for DN
Data transmission control circuit of SDN integrated circuit. 3. A microprocessor for controlling connection with the layer 1 of the ISDN circuit network, a register controlled by the microprocessor, and two 2.048 MHz transmission and reception whose operation is controlled by the register. A high-speed time-division data bus for ISDN is created on a one-chip semiconductor integrated circuit, the time-division data bus is divided into 32 channels, and registers are controlled by a microprocessor program to provide a high-speed time-division data bus for ISDN. A data transmission control circuit of an integrated circuit for ISDN which is controlled. 4. A microprocessor for controlling connection to a layer 1 of an ISDN circuit network, a register controlled by the microprocessor, and two 2.048 Mhz transmitters and receivers whose operations are controlled by the register. A high-speed time-division data bus is formed on a one-chip semiconductor integrated circuit, and the time-division data bus is divided into 32 channels so that 8-bit data is transferred per channel. A data transmission control circuit of an ISDN integrated circuit, wherein a register is controlled by the control circuit to control a high-speed time-division data bus for ISDN. 5. A microprocessor for controlling connection with the layer 1 of an ISDN network, a register controlled by the microprocessor, and two high-speed transmission and reception high-speed transmission / reception controlled by the register. Block of time-division data bus and high-level data link control circuit, P
HS Internet Forum standard blocks and transparent blocks are created on a single-chip semiconductor integrated circuit, and the registers are controlled by a microprocessor program. High-level data link control circuit blocks, PHS Internet Forum standard blocks, and transparent blocks are created. Integrated with the ISDN circuit layer 1 through a time-division high-speed data bus to control the transmission and reception of data in the connected block. Data transmission control circuit of the circuit. 6. A microprocessor for controlling connection with the layer 1 of an ISDN network, a register controlled by the microprocessor, and two high-speed transmission and reception high-speed transmission / reception controlled by the register. Block of time-division data bus and high-level data link control circuit, P
HS Internet Forum standard blocks and transparent blocks are created on a single-chip semiconductor integrated circuit, and the registers are controlled by a microprocessor program. High-level data link control circuit blocks, PHS Internet Forum standard blocks, and transparent blocks are created. Block is connected to the layer 1 block of the ISDN circuit network via a time-division high-speed data bus, so that data transmission and reception of the connected block are controlled and transmitted. A data transmission control circuit of an ISDN integrated circuit in which two high-speed time-division data buses for reliability and reception also control the transmission and reception of data with the bus of an external PCM. 7. A microprocessor for controlling connection with the layer 1 of the ISDN circuit network, a transmission control register and a reception control register controlled by the microprocessor, and its operation is controlled by the transmission control register and the reception control register. Two high-speed time-division data buses for transmission and reception are created on a single-chip semiconductor integrated circuit, and the transmission control register and the reception control register are controlled by a microprocessor program. 1. Designation of transmission mode 2. Designation of bus to send data 3. Determining permission to send data to the specified bus. A high-speed time-division data bus channel is designated to control the high-speed time-division data bus.
Data transmission control circuit of SDN integrated circuit. 8. A microprocessor for controlling connection to a layer 1 of an ISDN circuit network, a transmission control register, a reception control register, an external PCM bus control register, a transmission control register, and a reception control register controlled by the microprocessor. And two high-speed time-division data buses for transmission and reception whose operation is controlled by an external PCM bus control register are formed on a one-chip semiconductor integrated circuit.
For the transmission control register and the reception control register by the program of the microprocessor 1. Designation of transmission mode 2. Designation of bus to send data 3. Determining permission to send data to the specified bus. The channel of the high-speed time-division data bus is specified, and the external P
For CM bus control register 1. Specification of transmission mode to specify normal mode or loopback mode 2. Sync signal transmission permission synchronized with ch0 A data transmission control circuit of an integrated circuit for ISDN that permits a Sync signal transmission synchronized with ch2 and controls a high-speed time-division data bus.