JPH11318080A - On/off circuit for multiple output switching power source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output on/off circuit for a multiple output switching power source, in which the breakdown of a discharge element is prevented by reducing the discharge current of a discharging element for discharging load side capacitance charges, when an output on/off switching element is turned off. SOLUTION: A switching time for a control element Q4, which controls the turning on and off of a discharging element Q3 discharging charges of a load side capacitance C2 by causing a switching element FET Q2 to be turned off with a signal from a load side which is inputted from a signal input terminal 7, is controlled by time constant circuits R2, C4. The breakdown of the discharging element Q3 is prevented by restraining the peak value of a discharging current of the discharging element Q3, when the switching element FET Q2 is turned off. Thus use in the optimum operation region is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output on / off circuit of a multi-output switching power supply in electronic equipment.

In particular, a DC output load having an output on / off circuit is a capacitive load, which is connected to a load (main unit) equipped with a large-capacity capacitor and replaces the load (main unit) before replacing the consumables of the main unit and performing maintenance work. Device), the output voltage is turned off, and the body capacitance accumulated charge is forcibly discharged in a short time.
An output on / off circuit of a multi-output switching power supply having a function of preventing electric shock of a worker or a user, and a control element of the output on / off circuit is a switch element which also serves as a discharge element of the accumulated charge of the main body capacitance. A means for suppressing the discharge current flowing through the discharge element when forcibly discharging the accumulated charge in a short time and preventing the discharge element from being destroyed,
The present invention relates to an output on / off circuit of a multi-output switching power supply using a discharge element in a safer operation area.

[0003]

2. Description of the Related Art A conventional output on / off circuit of a multi-output switching power supply has been configured, for example, as shown in FIG. FIG. 4 is a block diagram of a conventional output on / off circuit of a multiple output switching power supply.

In FIG. 4, an output on / off circuit of a multi-output switching power supply includes a primary winding P1, a control winding P2, a first secondary winding S1, a second secondary winding S2, and a third secondary winding. A transformer 1 having a secondary winding S3 and a control winding P of the transformer 1
2, a field effect transistor (hereinafter referred to as "FET") Q1 as a switching element for switching a DC input voltage, and a control winding P2 of the transformer 1.
Control circuit 8 configured between
A rectifying / smoothing circuit 13 for obtaining a first DC output voltage connected to each of the first secondary winding S1, the second secondary winding S2, and the third secondary winding S3; A multi-output switching power supply having a rectifying / smoothing circuit 14 for obtaining a DC output voltage, a rectifying / smoothing circuit 15 for obtaining a third DC output voltage, and a signal input terminal from the load side. Output terminal 4 that is connected to the load side input terminal 4 ′ and supplies the power of the DC voltage E 4 V to the load side capacitor C 1 and the first load 16.
And an output terminal 5 connected to the load-side input terminal 5 ′ at an output terminal of the second DC output voltage and supplying power of the DC voltage E5 V to the load-side capacitor C2 and the second load 17; The output terminal of the output voltage is connected to the load side input terminal 6 ′, and the DC voltage E 6 is applied to the load side capacitor C 3 and the third load 18.
Output terminal 6 for supplying power of V, and a load-side input terminal 6 ′.
Is connected to a signal output terminal 7 ′, and an input terminal 7 to which a DC voltage E 6 V or 0 V of an output terminal 6 is input.
Consists of

Further, the output switching element 9 is for turning on / off the second DC output voltage, and is inserted in series between the output terminal 5 and the rectifying / smoothing circuit 14 of the second DC output voltage line. Have been. The bias circuit 10 is for applying a bias from the input terminal 4 to the control terminal of the output switch element 9, and is connected between the line of the output terminal 4 and the control terminal of the output switch element 9. The bypass circuit 11
This is for bypassing the charge of the load capacitance C2 to the control terminal of the output switch element 9 when the output switch element 9 is turned on from off, and is connected between the output terminal 5 and the control terminal of the output switch element 9. The control circuit 12 has an input terminal 7
A second control circuit for controlling the control terminal of the output switch element 9 with a signal from the input terminal 7 and a discharge circuit for discharging the electric charge of the load capacitor C2. Connected to.

FIG. 5 is a detailed circuit diagram of FIG. FIG.
, The output switching element 9 is an FET Q2
The drain of Q2 is connected to the rectifying and smoothing circuit 14 of the second DC output voltage line, and the source is connected to the output terminal 5 of the second output voltage. The bias circuit 10 includes a resistor R1, and is connected to the output terminal 4 and the gate of the FET Q2. The bypass circuit 11 includes a diode D1. The cathode is connected to the gate, which is the control terminal of the FET Q2, and the anode is connected to the source of the FET Q2. The control circuit 12 includes a discharge circuit that extracts the gate bias of the FET Q2 and a detection circuit that controls the discharge circuit based on the signal voltage of the input terminal 7.

The detection circuit comprises a transistor Q4 as a second control element and a resistor R2.
Has one connected to the input terminal 7 and the other connected to the base of the transistor Q4. The discharge circuit includes a transistor Q3 as a first control element and a discharge element and a resistor R3. One of the resistors R3 is connected to the collector of the transistor Q4 and the base of the transistor Q3, and the other is connected to the output terminal 6. And the collector of transistor Q3 is
Connected to the gate of FET Q2, the emitter is connected to ground.

Next, the circuit operation will be described with reference to FIG. FIG. 7 is a diagram showing a logic operation state of the output on / off circuit of FIG. In addition, high level (hereinafter, referred to as “H level”), low level (hereinafter, referred to as “L level”)
Is a signal level input to the signal input terminal from the load side. For example, an H level signal is 5V, and an L level is 0V signal.

FIG. 7 shows a signal (H = 5V, L = 0V) input from the third load 18 to the signal input terminal 7 and the FET Q
2. The operation state of the transistors Q3 and Q4 and the output terminal 5
Represents the voltage level of the load-side capacitance C2 connected to the power supply.

When the base current of the transistor Q3 is IB3 = (E6-VB
E3) / R3 When the base current of the transistor Q4 is IB4 = (E6-VB
E4) If the resistors R2 and R3 are set to operate in the saturation region at / R2, the transistor Q4 is turned on for the resistor R2 when the signal input to the input terminal 7 is at the L level. Since the base current does not flow, the transistor Q4 is turned off, and the transistor Q3 is turned on because the base current IB3 flows because the transistor Q4 is turned off.

Since the transistor Q3 is in the ON state, the gate terminal of the FET Q2 is grounded and is
Because of V, the output terminal 5 is off, and no power is supplied to the output terminal 5. Further, the collector current IC3 of the transistor Q3 becomes E4V / R1.

When the signal input to the input terminal 7 switches from the L level to the H level, the base current of the transistor Q4 becomes IB4 = (E6-VBE4) / R2, so that the transistor Q4 is turned on. The base of the transistor Q3 is grounded by the transistor Q4 to turn off the transistor Q3.

Since the transistor Q3 is off, the gate of the FET Q2 is connected to the resistor R1 from the potential of the output terminal 4.
And is turned on. When the FET Q2 is completely on, the gate-source voltage is (E
4-E5) V.

The transient operation when the signal input to the signal input terminal 7 is switched from H level to L level will be described with reference to FIG. FIG. 6 is a diagram showing an operation state of the output on / off circuit of FIG.

The signal input to the signal input terminal 7 is shown in FIG.
Since the base current for turning on the transistor Q4 does not flow through the resistor R2 when the level changes from the H level to the L level as shown in FIG. 6A, the base current between the base and the emitter of the transistor Q4 as shown in FIG. Rapidly drops to the ground level and enters the off state.

Further, since the transistor Q4 is off, the base-emitter voltage of the transistor Q3 rapidly rises to the VBE (sat) level as shown in FIG. 6C, and as shown in FIG. Transistor Q
The collector voltage of No. 3 (gate terminal of FET Q2) drops sharply to the ground level. At this time, since a charge remains in the load side capacitor C2 connected to the output terminal 5, the diode D is connected from the output terminal 5 to the gate of the FET Q2.
6, the residual charge of the load-side capacitor C2 was rapidly discharged as the collector current (discharge current) of the transistor Q3 as shown in FIG.

[0017]

Therefore, in the output on / off circuit of the conventional multi-output switching power supply, when the load side capacitance C2 is large, the load is quickly reduced when the output on / off circuit switches from on to off. When a discharge circuit for extracting the side capacitance charge is configured, the transistor Q4 as a control element for controlling ON / OFF of the transistor Q3 as a control element and a discharge element must be driven (logic operation) in a saturation region. Therefore, when the FET Q2 is turned off, the discharge current of the charge of the load-side capacitor C2 transiently flows as the collector current of the transistor Q3, so that the transistor Q3 has an ASO (Area (Area) shown by a broken line I in FIG.
There is a problem that the operation may deviate from the safe operation area as shown by the solid line II or the transistor Q3 may be destroyed. FIG. 9 shows the AS of the discharge element.
It is a figure showing operation in O safe operation field. In FIG. 9, a polygonal line I indicates the maximum upper limit of the ASO safe operation area.

Further, due to the excessive discharge current, a switch element having a large rated current, which results in an increase in cost, is used, or the discharge current is limited by a resistor having a large power rating, which increases the mounting area.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and reduces the discharge current of a discharge element that discharges a load-side capacitive charge when an output on / off switch element is turned off, thereby destructing the discharge element. It is an object of the present invention to provide an output on / off circuit of a multi-output switching power supply, which prevents the occurrence of the above.

[0020]

To achieve the above object, an output on / off circuit for a multiple output switching power supply according to claim 1 of the present invention comprises at least first and second secondary windings of a transformer. A multi-output switching power supply having a signal input terminal for rectifying output voltages of lines and outputting first and second DC output voltages from different output terminals to supply to a load side and inputting a signal from the load side A switch element for turning on / off the second DC output voltage, bias means for applying a bias to the control terminal of the switch element from the first DC output voltage, A first control element connected to a control terminal to control a bias; and a first control element configured to bypass a load-side capacitive charge of the second DC output voltage terminal to a control terminal of the switch element. And bypass means for discharging the control device, a second control element for on / off control of the first control element by a signal from the signal input terminal, the second
And a time constant circuit for controlling the switch switching time of the control element.

An output on / off circuit for a multiple output switching power supply according to claim 2 is the output on / off circuit for a multiple output switching power supply according to claim 1.
Is characterized by comprising a transistor, and the time constant circuit is constituted by a resistor and a capacitor which determine a bias time constant of the transistor.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an output on / off circuit of a multiple output switching power supply according to the present invention. FIG.
FIG. 2 is a detailed circuit diagram of FIG. 1 and 2, the same components as those in FIGS. 4 and 5 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 1, a time constant circuit 19 is connected to the signal input terminal 7 from the load side of the control circuit 12.
The time constant circuit 19 is connected to the base of the transistor Q4 as shown in FIG.
And a capacitor C4 connected between the base and the emitter of the transistor Q4. Other configurations are the same as those in FIGS.

Next, the circuit operation will be described with reference to FIG. FIG. 3 is a diagram showing an operation state of the output on / off circuit of FIG.

As shown in FIG. 3A, when the signal at the signal input terminal 7 switches from the H level to the L level, the bias between the base and the emitter of the transistor Q4 changes with the resistance R2 of the time constant circuit 19 and the capacitor C4. Fig. 3
As shown in (b), these resistor R2 and capacitor C4
It decreases with the time constant determined by. Therefore,
FIG. 3C also shows the base-emitter voltage of the transistor Q3 and the collector-emitter voltage of the transistor Q4.
As shown in FIG.
3 becomes gentle only for the active region operation period, and the amount of change per hour of the base current of the transistor Q4 becomes small. As shown in FIG. 3D, the voltage of the collector-emitter voltage of the transistor Q3 falls, And FIG.
As shown in (e), the peak value of the collector current (discharge current) of the transistor Q3 can be suppressed only during the active region operation period of the transistor Q3.

As described above, the change in the switching of the base-emitter bias of the transistor Q4 is determined by the time constant circuit 19.
By controlling the increase rate of the base current of the transistor Q4 by giving the falling time constant by the resistor R2 and the capacitor C4, the switching time of the transistor Q4 from off to on is controlled, and the collector current of the transistor Q3 ( Suppress the discharge current) peak value.

As described above, according to the signal from the signal input terminal 7, the output on / off circuit is turned off, and the discharge element (transistor Q3) for discharging the body capacitance (load-side capacitance) charge is turned on / off. By controlling the switch switching time of the control element (transistor Q4), it is possible to control the discharge current, which is the drive current of the discharge element, and to reduce the transient current of the discharge current when extracting the body capacitance charge in a short time. The discharge element (transistor Q3) can be prevented from being damaged, and can be used in a safe operation area.

In this case, although the base current increase rate of the transistor Q3 is controlled to suppress the discharge current peak value, the discharge time becomes longer. If it is not desired to lengthen the discharge time, the switch time can be adjusted by the constant of the resistor R3 which determines the base current of the transistor Q3. If the discharge time is the same, as shown by the broken line III in FIG. Although the effect of suppressing the discharge current peak value is lost,
The operation area of the transistor Q3 is optimized in the ASO safe operation area by the resistor R2 and the capacitor C4 as shown by the broken line III in FIG. 9, and the safety and the selection range of the transistor Q3 as a discharge element are widened. FIG. 8 is a diagram showing discharge current characteristics of the discharge element. In FIG. 8, the solid line II
Shows the discharge current characteristics of the discharge element of the conventional output on / off circuit shown in FIG.

[0030]

As described above, according to the output on / off circuit of the multi-output switching power supply according to the first aspect, the output on / off switch element is turned off by a signal from the load side, and the load side capacitive charge is turned off. The switching time of the second control element that controls the first control element that discharges the first control element is controlled even when the output on / off switch element is turned off even when the load is a large capacitive load. The peak value of the discharge current of the first control can be suppressed, and the first control element can be prevented from being destroyed, and can be used in an optimum operation region. Will be higher.

According to the output on / off circuit of the multi-output switching power supply of the second aspect, the second control element is constituted by a transistor, and the time constant circuit for controlling the switching speed of the transistor determines the bias time constant. With the configuration using the resistor and the capacitor, the configuration can be made with a simple circuit configuration and at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of an output on / off circuit of a multiple output switching power supply according to the present invention.

FIG. 2 is a detailed circuit diagram of FIG.

FIG. 3 is a diagram showing an operation state of the output on / off circuit of FIG. 2;

FIG. 4 is a block diagram of a conventional output on / off circuit of a multiple output switching power supply.

FIG. 5 is a detailed circuit diagram of FIG. 4;

FIG. 6 is a diagram showing an operation state of the output on / off circuit of FIG. 5;

FIG. 7 is a diagram illustrating a logic operation state of the output on / off circuit of FIG. 5;

FIG. 8 is a diagram showing discharge current characteristics of a discharge element.

FIG. 9 is a diagram showing an operation of the discharge element in an ASO safe operation area.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transformer 2, 3 Input terminal 4, 5, 6 Output terminal 7 Signal input terminal 8, 12 Control circuit 9 FETQ2 (switch element) 10 Bias circuit 11 Bypass circuit 13, 14, 15 Rectifying smoothing circuit 16, 17, 18 Load 19 time constant circuit P1 primary winding P2 control winding S1, S2, S3 secondary winding Q1, Q2 FET (field effect transistor) Q3 transistor (control element and discharge element) Q4 transistor (control element element) R1, R2, R3 resistor C4 capacitor D1 diode (bypass circuit)

Claims (2)

[Claims] An output voltage of at least a first and a second secondary winding of a transformer is respectively rectified, and first and second DC output voltages are output from different output terminals and supplied to a load side. In an on / off circuit of a multi-output switching power supply having a signal input terminal for inputting a signal from a load side, a switch element for turning on / off the second DC output voltage; A biasing means for applying a bias to a control terminal of the switch element, a first control element connected to the control terminal of the switch element to control bias, and a load-side capacitive charge of the second DC output voltage terminal, A bypass means for bypassing to a control terminal of the element and discharging by the first control element; and a second control means for controlling on / off of the first control element by a signal from the signal input terminal. An output on / off circuit for a multi-output switching power supply, comprising: a control element; and a time constant circuit for controlling a switch switching time of the second control element. 2. The device according to claim 1, wherein the second control element includes a transistor, and the time constant circuit includes a resistor and a capacitor that determine a bias time constant of the transistor. Output on / off circuit of multiple output switching power supply.