JPH11317760A - Switching hub device and switching processing method therefor, and storage medium recorded with control program therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching hub device which can improve switching performance by shortening the processing time needed to discard packets communicated between LAN terminals present in the same LAN segment. SOLUTION: Port (#1 to #n) transmission reception control circuits 17-1 to 17-n transfer received packets to a packet queue managing circuit 15. The packet queue managing circuit 15 extracts DA from the packets and transfers information on the data and reception port number to a search memory control circuit 12. The search memory control circuit 12 requests a search memory circuit 13 to retrieve only DA information and requests a search memory circuit 14 to perform retrieval using 'DA + port number'. The search memory control circuit 12 indicates the discarding of packets in response to matching state signals from the search memory circuits 13 and 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching hub device, a switching processing method thereof, and a recording medium recording a control program therefor, and more particularly, to a star-type connection form in a local area network called Ethernet (registered trademark). It relates to a line concentrator.

[0002]

2. Description of the Related Art Conventionally, this type of concentrator has been known as an IE.
CSMA / CD (Carr represented by EE802.3)
er Sense Multiple Access
/ Collision Detection) in a local area network (hereinafter, referred to as LAN) [usually called Ethernet (registered trademark)] in a star-type connection form (topology).
(Hereinafter referred to as a hub (HUB)).

As this system, there is a system in which a plurality of LAN segments # 1 to # 4 are connected by one switching hub 3, as shown in FIG. Here, the assumed LAN is a CS represented by IEEE802.3.
An MD / CD LAN with a half-duplex communication speed of 10 Mbps.

The frame format of a packet communicated in this system is, as shown in FIG.
(Destination Address: destination address) (6 octets) and SA (Source Ad)
dress: source address) (6 octets) and T
YPE (frame type) (2 octets) and DAT
A (information data) (46-1500 octets) and F
CS (Frame Check Sequence: check data) (4 octets).

When the switching hub 3 receives a packet from each of the ports to which the LAN segments # 1 to # 4 are connected, the DA of each packet and the address previously held by the LAN segment # 1 to where are stored. The destination port is determined by referring to information on whether the packet exists on # 4, and each packet is transferred. That is, the switching hub 3 is a device that realizes packet switching.

[0006] Between LAN terminals connected to one port of the switching hub 3 and existing in the same LAN segment # 1 to # 4, for example, L in LAN segment # 1
Communication between the AN terminals 41 and 42 is assumed.

In communication from the LAN terminal 41 to the LAN terminal 42, the switching hub 3 does not need to process a packet transmitted at that time. However, after receiving the packet at this time, the switching hub 3 judges the packet to be discarded without switching only by looking at the DA.

That is, the switching hub 3 performs a packet discarding process as shown in FIG. That is,
Upon receiving the packet (step S11 in FIG. 8), the switching hub 3 extracts DA from the packet (FIG. 8).
In step S12, the DA is transferred to the search memory (step S13 in FIG. 8).

The switching hub 3 searches for a DA (step S14 in FIG. 8), and if there is a match, reads the corresponding record address (step S15 in FIG. 8).
The switching hub 3 reads the transfer port number to which the packet is transferred from the read record address (step S16 in FIG. 8), and determines whether the transfer port number is the same as the reception port number (step S8 in FIG. 8). S1
7).

If they match, the switching hub 3 discards the packet from a packet queue (not shown) (step S18 in FIG. 8). If they do not match, the switching hub 3 adds the packet to the packet queue (step S19 in FIG. 8). If there is no compatible hub, the switching hub 3 performs an address resolution process for solving the DA non-adaptation (step S2 in FIG. 8).
0).

[0011]

In the conventional switching hub device described above, it is determined whether a packet should be discarded or a packet to be transferred to an arbitrary port based on the result of address search. Therefore, if transmission port information is newly obtained from the address search result, a process for comparing with the reception port information is required, and the process requires a lot of time.

For this reason, in the prior art, the switching performance in the switching hub device cannot be improved because the address information registered in advance is simply searched.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to reduce the processing time required for discarding a packet communicated between LAN terminals existing in the same LAN segment, and to reduce switching time. It is an object of the present invention to provide a switching hub device capable of improving performance, a switching processing method for the switching hub device, and a recording medium on which a control program for the switching hub device is recorded.

[0014]

A switching hub device according to the present invention is connected to a plurality of local area networks, and a destination address of a packet received via the plurality of local area networks is the same as that of the plurality of local area networks. A switching hub device including a first search memory circuit for preliminarily retaining information indicating which one is present, wherein a second search memory circuit retaining the same contents as the first search memory circuit;
Performing a first search for only the destination address using the first search memory circuit at the time of receiving the packet, and simultaneously using the second search memory circuit with the destination address and the packet using the second search memory circuit; And a determination unit for determining whether to discard the packet based on the results of the first and second searches.

In another switching hub device according to the present invention, in the above configuration, the second search memory circuit can be attached to and detached from its own device.

In the switching processing method according to the present invention, a plurality of local area networks are connected, and the destination address of a packet received via the plurality of local area networks is indicated in any of the plurality of local area networks. A switching processing method for a switching hub device including a first search memory circuit that holds information in advance, wherein a first search for only the destination address is performed using the first search memory circuit when receiving the packet. Performing a second search based on the destination address and the port number at which the packet was received using a second search memory circuit holding the same contents as the first search memory circuit simultaneously with the first search. Discarding the packet based on the results of the first and second searches And a step of determining whether.

In another switching processing method according to the present invention, a plurality of local area networks are connected, and a destination address of a packet received via the plurality of local area networks is present in any of the plurality of local area networks. A switching processing method for a switching hub device including a first search memory circuit that holds information indicating in advance a first address of only the destination address using the first search memory circuit at the time of receiving the packet. The destination address and the packet are searched using a second search memory circuit which retains the same contents as the first search memory circuit at the same time as the first search and is attachable to and detachable from the own device. Performing a second search based on the received port number; And a step of determining whether to discard the packet based on search results.

A recording medium storing the switching control program according to the present invention is connected to a plurality of local area networks, and a destination address of a packet received via the plurality of local area networks is any one of the plurality of local area networks. A switching hub device including a first search memory circuit that previously holds information indicating whether the packet exists in a switching hub device, a recording medium recording a switching process control program for causing a computer to perform a switching process on the packet, The switching processing control program causes the computer to use the first search memory circuit at the time of receiving the packet to store a first address of only the destination address.
Using the second search memory circuit that retains the same contents as the first search memory circuit at the same time as the first search, using the second address based on the destination address and the port number that received the packet. , And whether to discard the packet is determined based on the results of the first and second searches.

A recording medium recording another switching processing control program according to the present invention is connected to a plurality of local area networks, and a destination address of a packet received via the plurality of local area networks is the plurality of local area networks. A switching hub device including a first search memory circuit for preliminarily retaining information indicating which of the packets is present in the switching hub device, the recording medium recording a switching process control program for causing a computer to perform a switching process on the packet. The switching processing control program causes the computer to perform a first search for only the destination address using the first search memory circuit when receiving the packet, and to perform the first search at the same time as the first search. 1 sir A second search is performed using the destination address and the port number at which the packet was received by using a second search memory circuit that retains the same contents as the memory circuit and that can be attached to and detached from the own device. And whether to discard the packet based on the result of the second search.

That is, the switching hub device of the present invention comprises: a transmission / reception control circuit for each port for realizing a packet data transmission / reception operation to a connected LAN line;
A packet memory for storing packet data, a packet queue management circuit having means for managing the address of the packet buffer storing the packet data for each transmission port, and a MAC (Media Access Control).
rol) a search memory circuit in which an address is registered, a search memory circuit which can be attached to and detached from the apparatus, and a search memory control circuit having means for controlling these search memory circuits to realize search of registered contents. I have.

The packet queue management circuit includes means for extracting destination address information from the received packet, and means for transferring the packet information to the search memory control circuit together with the address information and the port number at which the packet was received. In.

An operation of extracting a MAC address, which is destination information, from received packet data, searching a search memory circuit in which information is stored in advance by using the MAC address as a key, and obtaining destination port information as a result is as follows. Since a long time is required for the search, the switching performance of the switching hub device is reduced.

Therefore, two search memory circuits having the same registered contents are provided, and only one of the two search memory circuits is searched for the MAC address, and the other is searched for the MAC address +
By performing a search using the reception port number and judging whether the packet is a discarded packet or a packet requiring switching from the combination of the matching results, it is not necessary to repeatedly access the search memory circuit which requires a long time.

Therefore, it is possible to reduce the processing time required for discarding a packet communicated between LAN terminals existing in the same LAN segment, and to improve switching performance.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a switching hub device according to one embodiment of the present invention. In the figure, a switching hub device 1 is a CPU.
(Central processing unit) 11, search memory control circuit 12, search memory circuit 13, search memory circuit (copy) 14, packet queue management circuit 15, packet memory 16, and ports (# 1 to #n) It comprises transmission / reception control circuits 17-1 to 17-n.

In the switching hub device 1, LA
Portions connected to N (Local Area Network) segments (# 1 to #n) 2-1 to 2-n are called ports, and usually have about 8 to 32 ports.

The port (# 1 to #n) transmission / reception control circuits 17-1 to 17-n of each of the ports # 1 to #n (not shown) perform packet data transmission / reception operations on the connected LAN line. Realize. The main processing in the port (# 1 to #n) transmission / reception control circuits 17-1 to 17-n is to perform serial / parallel conversion between a serial data communication line and serial data and parallel internal data. It is.

The packet queue management circuit 15 is provided for each port #
The packet data received from the port transmission / reception control circuits 17-1 to 17-n of 1 to #n are stored in the packet memory 16, read out again, and the port transmission / reception control circuits 17-1 to 17-1 of the destination ports # 1 to #n are transmitted. 17-n. Therefore, the packet queue management circuit 15 manages the packet storage addresses in queues for each transmission port.

The packet memory 16 has an SRAM (Stat
ic Random Access Memory) or DRAM (Dynamic Random Acc)
ESS Memory)
Holds packet data temporarily. The packet data is stored in a pre-partitioned space called a packet buffer. The address (address) of the packet buffer is managed by the packet queue management circuit 15.

The search memory control circuit 12 searches the search memory circuit 1 based on the address information contained in the packet.
3 and 14, and determines the transfer destination port of the packet data.

The search memory circuit 13 stores CAMs (Con
tent-addressableMemories)
A memory element represented by a device is desired. This memory element is a RAM (Random Access Mem).
CAM device inputs data, the CAM device inputs data, searches the storage status of the data, and outputs state information. (Match or unmatch) and the data storage address are output.

Generally, in this memory element, a searchable data length is about 64 bytes. When reading and writing stored data in this memory element,
As in a normal memory device, a storage address (address) is input, and data is transferred.

The search memory circuit 14 needs to realize the same information content and operation as the search memory circuit 13.
The search memory circuit 14 is configured to be freely attached to and detached from the switching hub device 1. C
The PU 11 manages and updates the contents of the search memory circuits 13 and 14.

FIG. 2 is a diagram showing an attachment structure of the search memory circuit 14 of FIG. In the figure, a search memory circuit 14 is mounted on a daughter card A3 so that only this circuit section can be easily removed, and is connected to a mother card A1 of the main unit in the same manner as a DRAM shim card. They are connected through a component A2 and have the configuration of an apparatus option.

FIG. 3 is a block diagram showing the system configuration of the switching hub device according to one embodiment of the present invention.
In the figure, the switching hub device 1 has a plurality of LANs.
The segments (# 1 to #n) 2-1 to 2-4 are line-connected to form a star LAN topology.

The LAN assumed here is defined as IEEE80.
2.3 CSMA / CD (Carrier
Sense Multiple Access / Col
10 Mbps, 10 Mbps, etc. in a LAN (usually called Ethernet) of the
It has a full-duplex or half-duplex communication speed of 0 Mbps.

LAN segments (# 1 to #n) 2-1
2-4 is a unit that shares a communication band of 10 Mbps or 100 Mbps with the transmission path. LAN segment (# 1 to # 1)
#N) 2-1 to 2-4 have no switching function,
Concentrator with simple repeater function (simply repeater
Each of the LAN terminals 211 to 21 is called a hub.
m, 221-224, 231-231 are also connected in a star configuration.

Further, as shown by the LAN segment (# 2) 2-2, depending on the functions of the repeater hubs 21 to 23, it may be possible to connect the LAN terminals in a partial branch type. In any case, repeater hubs 21-23
CS within one segment constituted by
According to the MA / CD method, all LAs in a segment
N terminals 211 to 21m, 221 to 224, 231 to 23
1 and a port of the switching hub device 1 is a half-duplex communication in which a transmission path and a communication band are shared.

On the other hand, LAN segment (# 4) 2
-4 does not use a repeater hub, and the LAN terminal 24 is connected to the port of the switching hub device 1 on a one-to-one basis, so that full-duplex communication is also possible.

FIG. 4 shows a frame format of a packet transmitted on the LAN. In the figure, the packet is D
A (Destination Address: destination address) (6 octets) d1 and SA (Source)
Address: Source address) (6 octets)
d2 and TYPE (frame type) (2 octets)
d3, DATA (information data) (46 to 1500 octets) d4, and FCS (Frame Check S)
equipment: check data) (4 octets)
d5.

The switching hub device 1 receives packet data having this frame format from one LAN segment and implements a switching operation of transferring the packet data to another LAN segment based on DA information. It is.

Also, one of the important processes of the switching hub device 1 is to constantly monitor the SA information of the received packet, so that a LAN having a MAC address to be managed is provided.
It is necessary to always keep track of the position of the terminal and to automatically follow the state even when the LAN terminal is moved.

FIG. 5 shows the packet queue management circuit 15 of FIG.
FIG. 3 is a diagram showing a detailed configuration of the embodiment. The operation of the embodiment of the present invention will be described with reference to FIGS.

It is assumed that communication is performed between LAN terminals existing in the same LAN segment (# 1 to #n) connected to one port of the switching hub device 1. This is referred to as “assumed case 1”.

The “assumed case 1” is a case of communication from the LAN terminal 211 to the LAN terminal 21m.
In this case, the switching hub device 1 is connected to the LAN terminal 21.
There is no need to perform switching processing on the packet transferred from 1 to the LAN terminal 21m.

However, the switching hub device 1
The operation of this is that once the packet transferred at this time is received,
Only by looking at the DA information will it be determined that the packet should be discarded without switching.

Next, the operation of the switching hub device 1 according to one embodiment of the present invention will be described with reference to FIG. Ports (# 1 to #n) of each port # 1 to #n of the switching hub device 1 Transmission / reception control circuits 17-1 to 17-
n transfers the packets 111 to 11n received from the LAN line to the packet queue management circuit 15.

The packet queue management circuit 15 is provided for each port #
Ports # 1 to #n (# 1 to #n) transmission / reception control circuit 17-
The packet data 107 transferred from 1 to 17-n is temporarily stored in the packet memory 16.

First, the packet queue management circuit 15
The operation of the queue management will be described with reference to FIG. The packet memory 303 is composed of a plurality of packet buffers having a capacity sufficient to store one packet data.

The packet queue management circuit 302 manages all address information of unused packet buffers in the free queue 30. When receiving the packet data a1 (301), the packet queue management circuit 302 takes out one address (address a1) of an empty packet buffer from the free queue 30 and stores the received packet data in the packet buffer according to the address. . Free queue 30
The address of the empty packet buffer managed by (1) is reduced by one.

Next, when the port information 31 of the transmission destination is found, the packet queue management circuit 302 stores the packet data a1 in the transmission queue 332 of the corresponding port (port # 2). The address (address a1) is registered.

The packet queue management circuit 302 reads out the packet data from the packet buffer 303 in the order of registration of the transmission queues 331 to 33n,
Ports # 1 to #n (# 1 to #n) transmission / reception control circuit 17-
1 to 17-n.

Thereafter, the packet data is transferred to ports # 1 to # 1.
From #n to LAN segment (# 1 to #n) 2-1 to 2-
n. The packet queue management circuit 302 executes this transmission operation for each transmission queue as needed.

Referring again to FIG. 1, the operation of search memory control circuit 12 will be described. As described above, the packet queue management circuit 15
7 in the packet memory 16 at the same time as extracting DA (address information) from the packet,
In addition, the port number 102 that has received the packet is transferred to the search memory control circuit 12.

The search memory control circuit 12 outputs "D
A + port number ”is input to the search memory circuits 13 and 14 at the same time, a search request for only DA is made to the search memory circuit 13, and“ D ”is sent to the search memory circuit 14.
A search request is made with “A + port number”.

In the above “assumed case 1”, the state signal 101 indicating that there is a match is returned from the search memory circuit 13, and the state signal 105 indicating that there is a match is also returned from the search memory circuit 14. At this point, the search memory control circuit 12 determines that the currently received packet is a communication between the same LAN segments (# 1 to #n), and passes a packet discard instruction 103 to the packet queue management circuit 15.

Similarly, in the “assumed case 2”, a state signal 101 indicating that there is a match is returned from the search memory circuit 13, and
And the status signal 1 indicating that there is no match from the search memory circuit 14.
05 is returned, the search memory control circuit 12
Determines that the currently received packet is a packet for a LAN segment connected to another port different from the received port.

The search memory control circuit 12 repeatedly accesses the search memory circuit 13 to obtain port information of the transfer destination. First, address information having matching information is read from the search memory circuit 13, and subsequently, information registered in the search memory circuit 13 is read based on the address information. The search memory control circuit 12 obtains the information of the port number corresponding to the MAC address from the information. At this point, the search memory control circuit 12
Transfers the port number information 103 of the transfer destination to the packet queue management circuit 15.

Similarly, in the "assumed case 3", if the non-conforming status signal 101 is returned from the search memory circuit 13, the non-conforming status signal 105 is always returned from the search memory circuit 14. The search memory control circuit 12 determines whether the transfer destination of the received packet is M
It is determined that the switching hub device 1 cannot manage the AC address.

The search memory control circuit 12 uses the MA
The instruction 103 indicating that there is no C address is passed to the packet queue management circuit 15. Upon receiving this, the packet queue management circuit 15 outputs an address solution request 106 to the CPU 11 to ask for an instruction. In contrast, the CPU 11 is an ARP (Address Resolution) which is widely used as a de facto standard in the current LAN environment.
Protocol) [RFC826] or the like to resolve the non-conformity of the destination address.

Here, the case where the search memory circuit 14 is not mounted will be described. In the case of the above “assumed case 1”, the state signal 1 indicating that there is a match from the search memory circuit 13
01 and the search memory circuit 14 does not implement the circuit, so that a non-conforming status signal 105 is always returned.

This is the same operation as the case of the “supposition case 2” described above. At this point, the search memory control circuit 12 has not yet determined whether the currently received packet should be discarded or switched.

The search memory control circuit 12 repeatedly accesses the search memory circuit 13 to obtain port information of the transfer destination. Search memory control circuit 1
2 reads out the address information where the matching information exists from the search memory circuit 13, and subsequently reads out the information registered in the search memory circuit 13 based on the address information.

The search memory control circuit 12 obtains the information of the port number corresponding to the MAC address from the information. The search memory control circuit 12 compares the transfer destination port number with the reception port number, and when it is determined that they match, determines that the packet is a packet to be discarded.

At this point, the search memory control circuit 12 determines that the currently received packet is a communication between the same LAN segments (# 1 to #n), and sends a packet discard instruction 103 to the packet queue management circuit 15. hand over.

FIG. 6 shows the search memory circuits 13 and 14 of FIG.
FIG. 3 is a diagram showing an example of the configuration of FIG. The operation of the embodiment of the present invention will be described with reference to FIGS. In switching hub device 1, port # 1 is LAN segment # 1
Port # 2 is in LAN segment # 2, port # 3
Are connected to the LAN segment # 3, and the port #n is connected to the LAN segment #n.

The switching hub device 1 has the ports (# 1 to #n) of each of the ports # 1 to #n for realizing the operation of transmitting and receiving packet data to and from the connected LAN line.
The transmission / reception control circuits 17-1 to 17-n, the packet memory 16 for storing packet data, the packet queue management circuit 15 for queue management of the address of the packet buffer storing the packet data for each transmission port, and the registration of the MAC address Search memory circuit 13, a search memory circuit 14 which is optionally removable and has the same contents as search memory circuit 13, and a search memory control circuit 1 for controlling these search memory circuits 13 and 14.
2 and a CPU 11.

Normally, the unit of one information record corresponding to a MAC address is about 16 to 64 bytes.
In this embodiment, one record is 16 bytes. The content of the information contained in this one record is a MAC address, a port number, a time stamp, and the like as shown in the data part format.

In this embodiment, the search memory circuits 13 and 14
Information stored in the address 0001 of the MAC address = MAC address =
Information on the LAN terminal having “001020300101”, which indicates that the LAN segment where the LAN terminal exists is connected to port number 01.

In other words, taking the LAN segment connected to port number 01 as an example, a LAN terminal having at least the respective MAC addresses stored in addresses 0001, 0003, and 0FFF is
It represents that it exists.

As other information, when the switching hub device 1 receives a packet transmitted by the LAN terminal, a time stamp for recording the latest arrival time is stored in the MAC address (SA: Source) of the transmitting LAN terminal.
Address).

In FIG. 6, the switching hub device 1 has the SA
= “001020300101” The time stamp when the packet was last received is “01.02.0”
3.04 ".

Each of the search memory circuits 13 and 14 has a mask register and sets a bit position to be collated when searching for input data. Mask register # in FIG.
1 designates a mask instruction for all bits other than the bit position corresponding to the MAC address, and the search memory circuit 13 uses the mask register # 1 to implement a search targeting only the value of the MAC address.

Similarly, the mask register 14 instructs masking except for the bit position corresponding to the MAC address and the port number, and the search memory circuit 14 uses the mask register # 2 to calculate “MAC address + port number”. Is realized.

FIG. 7 is a flowchart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS. Here, it is assumed that a packet of DA = “001020300101” is received from port number 01.

According to the contents of the search memory circuits 13 and 14 shown in FIG. 6, the LAN terminal having this DA exists on the LAN segment # 1 under the port number 01. That is, the switching hub device 1 that has received this packet does not need to perform the switching process on this packet, and performs the discarding process inside the switching hub device 1.

In this case, the port (# 1) transmission / reception control circuit 17-1 transfers the received packet 111 to the packet queue management circuit 15 (step S1 in FIG. 7). The packet queue management circuit 15 stores the received packet 107 in the packet memory 16 and, at the same time,
A is extracted (step S2 in FIG. 7), and the DA and the received port number “0” are stored in the search memory control circuit 12.
The information 102 of "1" is transferred (step S3 in FIG. 7).

The search memory control circuit 12 first inputs "DA + port number" to the search memory circuits 13 and 14 at the same time, and requests the search memory circuit 13 to search only DA information using the mask register # 1. ,
A search request is made to the search memory circuit 14 with “DA + port number” using the mask register # 2.

In this case, the MA corresponding to address 0001
The C address has been registered, and the port number to which the segment in which the MAC address exists is connected is 01. Therefore, the search memory control circuit 12 sends the matching status signal 101 from the search memory circuit 13.
Is the state signal 1 indicating that there is a match from the search memory circuit 14.
05 are returned (step S4 in FIG. 7), it is determined that the currently received packet is a communication between the same LAN segments, and the packet discard instruction 103 is passed to the packet queue management circuit 15 (step S5 in FIG. 7). ).

Upon receiving the packet discard instruction 103, the packet queue management circuit 15 performs a packet discard process. That is, as described above, the packet queue management circuit 15 obtains the packet discard instruction 32 instead of obtaining the transmission port information 31. Therefore, instead of registering the storage address of the packet data in the transmission queues 331 to 33n, , A process of returning to the free queue 30 is performed. As a result, the buffer area storing the packet is treated as an empty buffer, and the packet is discarded without being transferred.

Also, DA = “000” from port number 01
Suppose the case where a packet of the number 40506202 ″ is received.
This means that it exists on the subordinate LAN segment # 2. That is, the switching hub device 1 that has received this packet performs the switching process on this packet to the port number 02.

In this case, port # 2 transmission / reception control circuit 17
-2 transfers the received packet 112 to the packet queue management circuit 15 (step S1 in FIG. 7). The packet queue management circuit 15 stores the received packet 107 in the packet memory 16 and, at the same time, extracts a DA from the packet (step S2 in FIG. 7), and sends the DA and the received port number “02” to the search memory control circuit 12.
Is transferred (step S3 in FIG. 7).

The search memory control circuit 12 first inputs "DA + port number" to the search memory circuits 13 and 14 at the same time, and requests the search memory circuit 13 to search only DA information using the mask register # 1. ,
A search request is made to the search memory circuit 14 with “DA + port number” using the mask register # 2.

In this case, the search memory control circuit 12 returns a state signal 101 indicating that there is a match from the search memory circuit 13 and the search memory circuit 14 returns a state signal 105 indicating that there is no match (step S in FIG. 7).
4) It is determined that the received packet is a packet for a LAN segment connected to another port different from the received port, and the access of the search memory circuit 13 is repeatedly performed to obtain port information of the transfer destination.

That is, the search memory control circuit 12 reads the address information in which the matching information exists from the search memory circuit 13, and obtains the information of the address 0002 (step S6 in FIG. 7). Then, search memory control circuit 1
2 is 000 of the search memory circuit 13 based on the address information.
The information at address 2 is read, and information on the port number corresponding to the MAC address is obtained. The search memory control circuit 12 passes the transfer destination port information 103 to the packet queue management circuit 15 (Step S7 in FIG. 7).

The packet queue management circuit 15 performs a process of registering the storage address of the packet data in the transmission queues 331 to 33n based on the destination port information 103 (step S8 in FIG. 7). As a result, a packet switching operation is realized.

On the other hand, search memory control circuit 12
Are returned from the search memory circuits 13 and 14 when the state signals 101 and 104 indicating that there is no match are returned (step S in FIG.
4), it is determined that a packet addressed to a MAC address not to be managed is received, and an instruction 103 indicating that there is no MAC address is passed to the packet queue management circuit 15 (step S in FIG. 7).
9). The packet queue management circuit 15 receiving this outputs the address resolution request 106 to the CPU 11 and asks for an instruction, and the CPU 11 executes an address resolution protocol execution process.

As described above, "D"
By performing the search for “A + port number” simultaneously with the search for only DA in the search memory circuit 13, the packet is discarded in the case of communication between LAN terminals existing in the same LAN segment # 1 to #n. In performing the processing, FIG.
It is not necessary to read the corresponding record address, read the transfer destination port number, and compare the transfer destination port number and the reception port number in the conventional discard processing shown in FIG.

Therefore, the same LAN segments # 1 to #
In performing the discarding process of the packet communicated between the LAN terminals existing within n, the above-mentioned processes among the conventional processes are not required, so that the processing performance of the switching hub is improved by the amount of these processes. .

Further, when switching normal packets to different LAN segments # 1 to #n, it is not necessary to compare the transfer destination port number and the reception port number before performing the queuing process as in the related art. Becomes

Furthermore, since the search memory circuit 14 is configured as an option card and is mounted on the main body of the apparatus by connecting a connector, when the switching hub apparatus 1 is used in a network environment where communication traffic is relatively low, the search memory circuit 14 is used. Search memory circuit 1 for low performance
4 can be eliminated, and the power consumption of the device can be reduced according to the performance.

[0092]

As described above, according to the present invention, a plurality of local area networks are connected, and a destination address of a packet received via the plurality of local area networks exists in any of the plurality of local area networks. In a switching hub device including a first search memory circuit for preliminarily holding information indicating whether or not the first search memory circuit performs a first search for only the destination address using the first search memory circuit when receiving a packet, and the first search At the same time, a second search is performed using the destination address and the port number at which the packet was received using a second search memory circuit holding the same contents as the first search memory circuit, and based on the results of the first and second searches. To determine whether or not to discard the packet, the LAN terminal existing in the same LAN segment In it is possible to shorten the processing time required to drop the packets to be communicated, there is an effect that it is possible to improve the switching performance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a switching hub device according to one embodiment of the present invention.

FIG. 2 is a diagram showing a mounting structure of a search memory circuit of FIG. 1;

FIG. 3 is a block diagram showing a system configuration of a switching hub device according to one embodiment of the present invention.

FIG. 4 shows a frame format of a packet communicated on a LAN.

FIG. 5 is a diagram showing a detailed configuration of a packet queue management circuit of FIG. 1;

FIG. 6 is a diagram illustrating a configuration example of a search memory circuit in FIG. 1;

FIG. 7 is a flowchart showing the operation of one embodiment of the present invention.

FIG. 8 is a flowchart showing the operation of the conventional example.

FIG. 9 is a block diagram showing a system configuration of a switching hub device according to a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Switching hub device 2-1 to 2-n LAN segment (# 1 to #n) 11 CPU (central processing unit) 12 Search memory control circuit 13, 14 Search memory circuit 15 Packet queue management circuit 16 Packet memory 17-1 To 17-n port (# 1 to #n) transmission / reception control circuit

Claims (21)

[Claims] 1. A method according to claim 1, wherein a plurality of local area networks are connected, and information indicating in advance which one of said plurality of local area networks has a destination address of a packet received via said plurality of local area networks is stored. A switching hub device including a first search memory circuit, wherein the second search memory circuit retains the same contents as the first search memory circuit, and the first search memory circuit is used when receiving the packet. Means for performing a first search for only the destination address and performing a second search using the second address memory and the port number at which the packet was received using the second search memory circuit simultaneously with the first search Determining means for determining whether to discard the packet based on the results of the first and second searches; A switching hub device comprising: 2. The switching hub device according to claim 1, wherein said judging means judges to discard said packet when the results of said first and second searches are both compatible. 3. The method according to claim 1, wherein the determining unit determines to switch the packet when only the result of the first search is appropriate.
A switching hub device as described. 4. The method according to claim 1, wherein the determining unit determines that an address resolution process for resolving the non-conformity of the destination address is performed when the results of the first and second searches are both non-conforming. The switching hub device according to any one of claims 1 to 3. 5. The switching hub device according to claim 1, wherein the second search memory circuit is detachably attached to its own device. 6. A method in which a plurality of local area networks are connected, and information indicating in advance which of the plurality of local area networks a destination address of a packet received via the plurality of local area networks exists is stored. A switching processing method for a switching hub device including a first search memory circuit, the first search memory circuit performing a first search for only the destination address using the first search memory circuit when receiving the packet, and Performing a second search using the destination address and the port number at which the packet was received using a second search memory circuit holding the same contents as the first search memory circuit at the same time as the search; Determining whether to discard the packet based on the result of the second search A switching processing method characterized by the above-mentioned. 7. The step of determining whether or not to discard the packet is characterized in that it is determined that the packet is discarded when both the first and second search results match. The switching processing method according to claim 6. 8. The method according to claim 6, wherein the step of determining whether or not to discard the packet is configured to determine that the packet is to be switched when only the result of the first search matches. Or the switching processing method according to claim 7. 9. The step of determining whether or not to discard the packet is determined to be an address resolution process for resolving the non-conformity of the destination address when the results of the first and second searches are both non-conforming. 9. The switching processing method according to claim 6, wherein the switching processing is performed. 10. A method in which a plurality of local area networks are connected, and information indicating in advance in which of the plurality of local area networks the destination address of a packet received via the plurality of local area networks is stored. A switching processing method for a switching hub device including one search memory circuit,
When the packet is received, a first search for only the destination address is performed using the first search memory circuit, and the same content as the first search memory circuit is held at the same time as the first search. Performing a second search based on the destination address and the port number at which the packet was received using a second search memory circuit that can be attached to and detached from the server, and based on the results of the first and second searches. Determining whether to discard the packet. 11. The step of judging whether or not to discard the packet is characterized in that it is judged that the packet is discarded when the results of the first and second searches both match. The switching processing method according to claim 10. 12. The method according to claim 10, wherein the step of determining whether to discard the packet determines that the packet is to be switched when only the result of the first search matches. Alternatively, the switching processing method according to claim 11. 13. The step of judging whether or not to discard the packet is judged to be an address resolution process for resolving the non-conformity of the destination address when the results of the first and second searches are both non-conforming. The switching processing method according to claim 10, wherein the switching processing is performed. 14. A method in which a plurality of local area networks are connected, and information indicating in advance in which of the plurality of local area networks the destination address of a packet received via the plurality of local area networks is stored. 1. A recording medium storing a switching processing control program for causing a computer to perform a switching processing on the packet in a switching hub device including the search memory circuit according to (1).
The switching processing control program causes the computer to perform a first search of only the destination address using the first search memory circuit at the time of receiving the packet, and to perform the first search simultaneously with the first search. A second search is performed using the destination address and the port number that received the packet using a second search memory circuit holding the same contents as the search memory circuit, and based on the results of the first and second searches. A recording medium on which a switching processing control program is recorded, wherein it is determined whether to discard the packet. 15. The switching processing control program, when causing the computer to determine whether to discard the packet, when the results of the first and second searches are both compatible, discarding the packet. 15. A recording medium on which the switching processing control program according to claim 14 is recorded. 16. The switching process control program, when causing the computer to determine whether to discard the packet, causes the computer to determine that the packet is to be switched when only the result of the first search is appropriate. A recording medium recording the switching processing control program according to claim 14 or claim 15. 17. The switching processing control program, when causing the computer to determine whether to discard the packet, when the result of the first and second searches is not suitable, the destination address is matched. 17. A recording medium on which the switching processing control program according to claim 14 is determined to be an address resolution processing for solving the absence. 18. A method in which a plurality of local area networks are connected, and information indicating in advance in which of the plurality of local area networks the destination address of a packet received via the plurality of local area networks is stored. 1. A recording medium recording a switching processing control program for causing a computer to perform a switching processing on the packet in a switching hub device including the search memory circuit according to (1).
The switching processing control program causes the computer to perform a first search of only the destination address using the first search memory circuit at the time of receiving the packet, and to perform the first search simultaneously with the first search. A second search is performed using the destination address and the port number at which the packet was received using a second search memory circuit that retains the same contents as the search memory circuit and that can be attached to and detached from the own device. A recording medium storing a switching processing control program, wherein a determination is made as to whether or not to discard the packet based on the results of the first and second searches. 19. The switching processing control program, when causing the computer to determine whether or not to discard the packet, when the results of the first and second searches are both compatible, discarding the packet. 19. A recording medium on which the switching processing control program according to claim 18 is recorded. 20. The switching process control program, when causing the computer to determine whether to discard the packet, causes the computer to determine that the packet is to be switched when only the result of the first search matches. 20. A recording medium on which the switching processing control program according to claim 18 or 19 is recorded. 21. The switching processing control program, when causing the computer to determine whether or not to discard the packet, when the result of the first and second searches is not suitable, the destination address is matched. 21. A recording medium on which the switching processing control program according to claim 18 is determined to be an address resolution processing for solving the absence.