JPH1131726A - Evaluation method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make feasible measuring of the insulation breakdown strength under various conditions, by a method wherein multiple times of protective steps, processing steps and measuring steps are repeated toward a wafer with multiple patterns of semiconductor device wherein a conductive film in a specific times of area ratio of a thin film in a specific thickness is formed. SOLUTION: A field insulation film 2 is selectively formed on the surface of a p type silicon substrate 1 as a base electrode so as to form a 10-300 Åthick gate insulation film 3 thinner than the field insulation film 2. Next, a wafer wherein multiple patterns of a semiconductor device forming an upper part electrode 4 as a conductive film in the area ratio of 1 to 10000000 times of the gate insulation film 3 are arranged is prepared. Next, a protective step forming protective films 20a, a processing step by a plasma and a measuring step are repeated so as to make four times of evaluating tests on the same wafer. Through these procedures, the conditions for processing by ions for the tests on the semiconductor device can be pertinently made.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating damage to a thin insulating film (for example, a silicon oxide film) on a semiconductor substrate which occurs during plasma processing when manufacturing a semiconductor device such as an LSI. The present invention relates to a semiconductor device evaluation method capable of evaluating the damage of the thin insulating film a plurality of times on one wafer.

[0002]

2. Description of the Related Art In recent years, in semiconductor manufacturing processes, processes using ions or electrons, such as plasma processing and ion implantation, are often used. And LSI
In the process of treating a semiconductor device with ions or electrons as the pattern becomes finer and thinner, damage due to a charge-up phenomenon, that is, damage such as destruction of a thin insulating film (silicon oxide film) on a semiconductor substrate, is caused. Receiving it is a serious problem.

In order to solve this problem, it is necessary to employ processing conditions that can reduce charge-up damage in each of the processing steps. For that purpose, it is necessary to measure information correlated with charge-up damage and optimize the process based on the information.

In a semiconductor device having a MOS structure, a thin gate insulating film is generally formed on a silicon substrate, and a gate electrode is formed on the gate insulating film. When plasma processing is performed on the silicon substrate configured as described above, the plasma potential on the surface of the silicon substrate becomes non-uniform. As a result, electric charges are transmitted from the electrode to the inside of the silicon substrate, and move from a place where the plasma potential is high to a place where the plasma potential is low. As a result, current flows from the upper electrode to the substrate through the gate insulating film below the upper electrode, and damage due to charge-up occurs.

[0005] As a method of evaluating such damage due to charge-up of an insulating film, a MOS (Metal-Oxide-Semi-
conductor) Method for measuring the dielectric breakdown strength of a device having a capacitor structure (D. Takehara et al .: Proc. Symp.
on Dry Prosess 45 (1993), pp. 51-54, Kazuo Nojiri and others Se
miconductor World (1992.10.) pp.86-93). In this method, as a method of measuring damage due to charge-up, a method of measuring a dielectric breakdown of a MOS capacitor or a voltage value when a constant current is applied to a gate insulating film of a MOS structure is used. After several tens to several hundreds are produced and subjected to the plasma processing to be evaluated on this wafer, the damage is measured for these devices,
evaluate. Since the device used in this method has the same structure as the device actually used, the charge-up damage that occurs is comparable to that of the device actually used.

An EEPROM (Electrically Erasa)
ble Programmable Read-Only-Memory) or MNOS (Me
tal-Nitride-Oxide-Semiconductor) A method of measuring the capacitance-voltage of a structural device (CV measurement method) is also known (Semiconductor World, October 1992, No. 8).
6-93). The CV measurement method freezes the charge-up voltage received in the plasma and calculates CV (capacitance-voltage).
This is a method of evaluating damage due to charge-up of an insulating film by measuring characteristics. Since this measurement method is not a destructive inspection, the device can be reused when the charge-up is reset, and the device can be used a plurality of times until the conductive film on the surface disappears.

[0007]

However, the NMO
In the S or EEPROM CV measurement method, there is a problem that the correlation with the actual damage to the oxide film cannot be uniquely determined because the measurement principle is the measurement of the plasma potential. Also, this damage measuring method has a disadvantage that a dead zone exists. Therefore, there is a disadvantage that the measurement accuracy in the low voltage region and the high voltage region is low.

On the other hand, in the method of measuring damage using a device having a MOS structure, since the damage generated is the same as that of the actual device since it has the same structure as that of the actual device, if this damage is measured, , Can be correlated with the actual device. However, since this method is a destructive inspection, there is a problem that the device cannot be reused.

The present invention has been made in view of the above problems, and can be directly compared with damage caused by charge-up of a device formed in an actual semiconductor device, and can be performed a plurality of times on one wafer. It is an object of the present invention to provide a semiconductor device evaluation method capable of measuring the dielectric breakdown strength.

[0010]

According to a method for evaluating a semiconductor device according to the present invention, a thin insulating film having a thickness of 10 to 300 mm and a thicker insulating film are formed on a semiconductor substrate, and the thin insulating film is formed on the thin insulating film. Preparing a wafer on which a plurality of semiconductor device patterns on which a conductive film is formed at an area ratio of 1 to 10000000 times the insulating film are provided, and covering a part of the pattern on the wafer with a protective insulating film; Treating the wafer with ions or electrons, measuring damage to the thin insulating film of the pattern not covered with the protective insulating film, and removing all or one of the patterns covered with the protective insulating film. A protective step of peeling the protective insulating film from the portion and covering the whole or part of the other pattern with the protective insulating film; a processing step of treating the wafer with ions or electrons; A measuring step of measuring the damage of the thin insulating film of the pattern not covered with the insulating film, wherein a series of steps consisting of the protection step, the processing step and the measuring step is repeated one or more times. I do.

According to the semiconductor device evaluation method of the present invention, a thin insulating film having a thickness of 10 to 300 mm and a thicker insulating film are formed on a semiconductor substrate, and the thin insulating film having a thickness of 1 to 10000000 is formed on the thin insulating film. A step of preparing a wafer on which a plurality of patterns of a semiconductor device having a conductive film formed with a double area ratio are arranged, and covering a part of the pattern on the wafer with a protective insulating film; A step of treating with electrons, a step of peeling the protective insulating film for all or a part of the pattern covered with the protective insulating film, and a step of covering the entire other pattern with the protective insulating film, and ionizing the wafer. Or a step of treating with an electron, and a step of peeling the protective insulating film and measuring damage to the thin insulating film, wherein the protecting step and the processing step are performed one or more times. Characterized in that the return Ri.

Preferably, the protective insulating film is an insulating film selected from the group consisting of silicon oxide, silicon nitride and resist.

In general, a thin gate insulating film of a semiconductor device having a MOS structure has a thickness of 10 to 300.degree., And therefore, in the present invention, a thin insulating film in the above range is added together with a semiconductor device to be evaluated. Form a film. In addition, the area ratio (antenna ratio) of the conductive film to the thin insulating film is set to 1 to 10000000 times in accordance with the antenna ratio of a normal semiconductor device.

In the present invention, a part of a plurality of semiconductor device patterns formed on a wafer is used to
Perform damage measurement twice. That is, only a part of the pattern is exposed, and the other pattern is covered with a protective insulating film so as not to be damaged by the treatment with ions or electrons,
The damage of the exposed pattern of the semiconductor device due to the above processing is measured. After that, treatment with ions or electrons is performed under another condition. In that case, among the patterns of the semiconductor device covered with the protective insulating film in the first treatment,
The protective insulating film of all or a part of the pattern is peeled, and the damage is measured for this pattern. By repeating such a process one or more times, two or three or more damage measurements can be performed on one wafer. The measurement of the damage itself may be performed immediately after each treatment with ions or electrons, or after the treatment with ions or electrons, the pattern after this treatment is covered with a protective insulating film, and Then, all the protective insulating films may be peeled off, and the measurement may be performed on all the patterns at once.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for evaluating a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a sectional view showing a device having a MOS capacitor structure used for evaluating a semiconductor device according to an embodiment of the present invention. FIG. 2A is a plan view showing a wafer on which chips (device groups) are formed,
(B) is an enlarged plan view showing this chip.

First, as shown in FIG. 2A, for example,
A plurality of chips 6 are formed on the entire surface of an 8-inch wafer 7, and an evaluation wafer is manufactured. In this embodiment, the wafer 7
A plurality of chips 6 are formed in a matrix along the shape of the above, and a device having a MOS capacitor structure is formed on each of these chips 6, for example. The MOS capacitor structure of this device is shown in FIG. A field insulating film 2 is selectively formed on a surface of a p-type silicon substrate 1 serving as a lower electrode, thereby defining an element region. A field insulating film 2 is formed on the surface of the partitioned element region.
A thinner gate insulating film 3 having a thickness of 10 to 300 mm is formed. Further, an upper electrode 4 made of polysilicon is formed on the gate insulating film 3 over a wider area than the gate insulating film 3. Thus, a MOS capacitor structure is formed.

In this embodiment, as shown in FIG. 2B, the upper electrode 4 is formed by processing the polysilicon film so that a plurality of separated electrodes having different areas are formed.
Thereby, each evaluation device A1, A2, A3, A4,
P1, P2, P3, S1 and S2 are formed on the chip 6. This assumes devices with various shapes and sizes by changing the ratio (antenna ratio) of the area of the upper electrode (antenna) 4 to the area of the gate portion (gate insulating film 3) of the insulating film. . Table 1 below shows the antenna ratio of each evaluation device.

[0018]

[Table 1]

Next, a part of the plurality of chips 6 (device group) arranged in a matrix on the entire surface of the wafer 7 is covered with a protective insulating film. FIG. 3 is a plan view showing a wafer in which some chips 6 are covered with a protective insulating film. this,
In FIG. 3, the uppermost row of the plurality of chips 6 arranged in a matrix is set as the first row, and the second row, the third row,.
The 16th row, the leftmost column is the first column, the second column, the third column,... The 16th column.

FIG. 4A is a sectional view showing a device not covered with a protective insulating film, and FIG. 4B is a sectional view showing a device whose surface is covered with a protective insulating film. In the device shown in FIG. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. As shown in FIG. 4A, in the device on the chip 6 that is not covered with the protective insulating film 20a, the upper electrode 4 on the surface is exposed.
As shown in FIG. 4B, when the surface of the chip 6 is covered with the protective insulating film 20a, the upper electrode 4 of the device on the chip 6 is completely protected by the protective insulating film 20a. In this embodiment, an organic resist film is used as the protective insulating film 20a covering the chip 6, but a film made of quartz such as SOG (SPIN on GLASS) may be used.

In this embodiment, first, as shown in FIG. 3, even-numbered rows, that is, the second, fourth, sixth,.
.. And the surface of the chip 6 arranged in the 16th row is covered with the protective insulating film 20a, and the even-numbered columns, ie, the second, fourth, sixth,. The surface of the chip 6 placed on the eye was covered with the protective insulating film 20a.

Next, as a process using ions or electrons on the wafer 7, a first plasma process is performed assuming an LSI manufacturing process. That is, the wafer 7 is set in a plasma etching apparatus, and the wafer 7 is subjected to an etching process under the first condition (gas type, gas pressure, high-frequency plasma power, and bias electrode).

Then, the etched wafer 7 is set in a prober evaluation apparatus, and the IV (current-current) of each device is set.
Measure the voltage) characteristics. It is known that when the conditions of the plasma processing are constant, the magnitude of the charge-up damage to the gate insulating film 3 of each device is proportional to the antenna area (antenna ratio). Therefore, in the present embodiment, the result is the same as the result of evaluating the IV characteristics of the gate insulating film subjected to the plasma treatment under different conditions and having received the charge-up damage of different sizes.

As shown in FIG. 4A, the protective insulating film 20
Since the upper electrode 4 (polysilicon film or metal layer) is not covered with the protective insulating film 20a in a region not covered with a, the gate insulating film 3 is damaged by dielectric breakdown if plasma treatment is performed in this state. Receive. On the other hand, as shown in FIG.
In the region covered with, the upper electrode 4 (polysilicon film or metal layer) is covered with the protective insulating film 20a, so that the gate insulating film 3 does not suffer charge-up damage even if the plasma processing is performed. Therefore, the magnitude of the charge-up damage when the wafer 7 is etched under the first condition is measured by measuring the IV characteristics of each chip 6 not covered with the protective insulating film 20a. be able to.

Next, in the same manner, all the protective insulating film 20a coated before the first plasma treatment is removed. Thereafter, as shown in FIG. 5, after only the chips 6 located in the even-numbered rows and the odd-numbered columns are covered with the protective insulating film 20b, the wafer 7 is subjected to the second plasma treatment under the second condition. Then, as in the case of the first plasma processing, only the devices formed on the chip 6 not covered with the protective insulating film 20b are damaged by the second plasma processing. Thereafter, the damage of the gate insulating film of the device not covered with the protective insulating film 20b is measured.

Next, the protective insulating film 20b coated before the second plasma treatment is entirely removed. Thereafter, as shown in FIG. 6, after only the chips 6 located in the odd-numbered rows and the even-numbered columns are covered with the protective insulating film 20c, the third plasma treatment is performed on the wafer 7 under the third condition. Thereafter, the damage of the gate insulating film of the device not covered with the protective insulating film 20c is measured.

Next, similarly, all the protective insulating film 20c coated before the third plasma treatment is peeled off. Thereafter, as shown in FIG. 7, after only the chips 6 located in the odd-numbered rows and the odd-numbered columns are covered with the protective insulating film 20d, the wafer 7 is subjected to the fourth plasma treatment under the fourth condition. After that, the damage of the gate insulating film of the device not covered with the protective insulating film 20d is measured.

As described above, in the present embodiment, as shown in FIGS. 3 and 5 to 7, the protection step of forming a protective insulating film, the processing step by plasma, and the measurement step are repeated four times on the same wafer. Evaluation test can be conducted. By changing the coating pattern in the protection step, the damage of the gate insulating film can be measured a plurality of times on one wafer.

Further, the structure of the evaluation device is not limited to the structure shown in FIG. 1. In the present invention, evaluation devices having various structures can be used.

FIGS. 8 and 9 are cross-sectional views showing examples of the structure of an evaluation device that can be used in the semiconductor device evaluation method according to the present invention. In the devices shown in FIGS. 8 and 9, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the evaluation device shown in FIG. 8, a photoresist 9 is selectively formed on the polysilicon film 8 before the upper electrode 4 shown in FIG. 1 is processed. Also,
In the evaluation device shown in FIG. 9, an interlayer insulating film 10 is formed on the entire surface including the upper electrode 4 and the field insulating film 2, and the interlayer insulating film 10 has a contact hole 10 a in a region matching the gate insulating film 3. And a metal film 11 filling the contact hole 10a is formed on the interlayer insulating film 10.

With the evaluation device thus configured, the degree of dielectric breakdown damage in the insulating film can be evaluated, similarly to the evaluation device shown in FIG. In this case, as shown in FIGS. 10 (b) and 11 (b), a protective insulating film 20a which covers the photoresist 9 or the metal film 11 is formed by coating, as in the protection step shown in FIG. Even if the plasma treatment is performed, the gate insulating film 3 is not subjected to charge-up damage, and the dielectric breakdown strength can be measured a plurality of times.

In this embodiment, the charge-up damage during the etching process was measured using a plasma etching apparatus. However, in the present invention, other plasma processing, such as a resist removal (ashing) apparatus or an ion It is possible to measure charge-up damage at the time of removing a resist using an implantation apparatus or at the time of ion implantation.

As shown in this embodiment, every time a process using ions or electrons is performed, a process for measuring the damage to the gate insulating film may be performed immediately after the process. Alternatively, the pattern after this processing may be covered with a protective insulating film, and finally, all the protective insulating films may be peeled off, and the measurement may be performed on all the patterns collectively.

[0035]

Hereinafter, test results obtained by evaluating a semiconductor device by a semiconductor device evaluation method according to an embodiment of the present invention will be described.
This will be specifically described.

First, as shown in FIG.
Was prepared, a part of the chips 6 was covered with a protective insulating film 20a, and then the wafer was subjected to a first plasma treatment. Next, the protective insulating film 20a
The charge-up damage of the gate insulating film 3 was measured for the device on the chip 6 which was not covered with. Thereafter, the protective insulating film 20a is peeled off from the wafer 7, and again,
As a protection step, the surface of the wafer 7 is selectively covered with the protective insulating film 2.
After coating with Ob, the wafer 7 was subjected to a second plasma treatment as a processing step. Then, as a measurement step, after measuring the charge-up damage of the gate insulating film 3 in the same manner as in the first plasma treatment, the protective insulating film 20b was peeled off from the wafer.

Thereafter, the protection step, the processing step, and the measurement step were repeated in the same manner to evaluate the charge-up damage four times in total. In this embodiment, the shape of the protective insulating film is the same as the shapes shown in FIGS. In the first to fourth plasma treatment steps, etching was performed under the same conditions in order to investigate the reliability by the evaluation method according to the present embodiment.

FIGS. 12 to 15 are plan views showing the evaluation results of the charge-up damage after the first to fourth plasma treatments, respectively. 12 to 15,
The chip 6 is indicated by three types of hatching according to the magnitude of the charge-up damage.

As shown in FIG. 12, the device group which was not covered with the protective insulating film 20a was hardly damaged by the gate insulating film near the center of the wafer 7, The damage to the gate insulating films of the group has increased.

In the second protection step, the chips 6 arranged in the corner rows and the odd columns are covered with the protective insulating film 2b. Therefore, in the measurement step after the second plasma processing, It is possible to evaluate the degree of damage to the gate insulating film only for the chip arranged at the position where the odd-numbered row and the corner-numbered column intersect. As shown in FIG. 13, even after the second plasma treatment, the degree and variation of damage to the gate insulating film were substantially the same as those shown in FIG.

As shown in FIGS. 14 and 15, the distribution of damage to the gate insulating film is distributed in the same manner as the result of the first plasma treatment. Table 2 below shows the degree of charge-up damage to the gate insulating film after the first to fourth plasma treatments. In Table 2, (A) indicates the number of devices that did not receive the charge-up damage, (B) indicates the number of devices that received the charge-up damage to some extent, and (C) indicates the number of devices that had a large degree of the charge-up damage. .

[0042]

[Table 2]

As shown in Table 2, when the plasma treatment was performed under the same conditions by the four protection steps shown in FIGS. 12 to 15, the charge-up damage distribution due to the breakdown voltage of the thin insulating film was almost the same. It became. That is, according to the evaluation method of the semiconductor device according to the present example, high reliability could be obtained even if one wafer was used plural times.
Therefore, the plasma processing conditions in the actual semiconductor device manufacturing process can be appropriately designed by performing various measurements using a single wafer and varying the plasma processing conditions.

[0044]

As described in detail above, according to the present invention,
A protection step of exposing a part of a plurality of semiconductor device patterns formed on one wafer and covering the remaining pattern with a protective insulating film, a processing step of treating with ions or electrons, The measurement step of measuring damage is repeatedly performed or the protection step and the processing step are repeatedly performed, and then the protection insulating film is repeatedly measured. The dielectric breakdown strength, which can be directly compared with the charge-up damage received by a device formed in a semiconductor device, can be measured under various conditions. Therefore, it is possible to appropriately set processing conditions of ions or electrons to be performed on the semiconductor device. Further, the cost of a test device manufactured for measuring the charge-up damage can be significantly reduced, and a practical evaluation device can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a device having a MOS capacitor structure used for evaluating a semiconductor device according to an embodiment of the present invention.

FIG. 2A is a plan view showing a wafer on which a chip (device group) is formed, and FIG. 2B is an enlarged plan view showing the chip.

FIG. 3 is a plan view showing a wafer in which some chips are covered with a protective insulating film.

4A is a cross-sectional view showing a device not covered with a protective insulating film, and FIG. 4B is a cross-sectional view showing a device whose surface is covered with a protective insulating film.

FIG. 5 is a diagram showing a covering arrangement of a protective insulating film during a second plasma treatment.

FIG. 6 is a diagram showing a covering arrangement of a protective insulating film during a third plasma treatment.

FIG. 7 is a diagram showing a covering arrangement of a protective insulating film when performing a fourth plasma treatment.

FIG. 8 is a cross-sectional view showing a structural example of an evaluation device that can be used in the semiconductor device evaluation method according to the example of the present invention.

FIG. 9 is a cross-sectional view showing another example of the structure of an evaluation device that can be used in the semiconductor device evaluation method according to the example of the present invention.

10A is a cross-sectional view illustrating a device not covered with a protective insulating film, and FIG. 10B is a cross-sectional view illustrating a device whose surface is covered with a protective insulating film.

11A is a cross-sectional view showing a device not covered with a protective insulating film, and FIG. 11B is a cross-sectional view showing a device whose surface is covered with a protective insulating film.

FIG. 12 is a plan view showing a damage distribution of the gate insulating film after the first plasma processing.

FIG. 13 is a plan view showing a damage distribution of the gate insulating film after the second plasma processing.

FIG. 14 is a plan view showing a damage distribution of the gate insulating film after the third plasma treatment.

FIG. 15 is a plan view showing a damage distribution of the gate insulating film after the fourth plasma processing.

[Explanation of symbols]

 Reference Signs List 1; substrate 2: field insulating film 3: gate insulating film 4: upper electrode 6; chip 7; wafer 8; polysilicon film 9; photoresist 10; interlayer insulating film 10a; , 20d; insulating film (resist) A1, A2, A3, A4; device P1, P2, P3; device S1, S2; device

Claims (4)

[Claims] A thin insulating film having a thickness of 10 to 300 mm and a thicker insulating film are formed on a semiconductor substrate, and a conductive film is formed on the thin insulating film at an area ratio of 1 to 10000000 times that of the thin insulating film. Providing a wafer on which a plurality of patterns of the formed semiconductor device are arranged, covering a part of the pattern on the wafer with a protective insulating film, treating the wafer with ions or electrons, Measuring the damage of the thin insulating film of the pattern not covered with the insulating film, and peeling off the protective insulating film for all or part of the pattern covered with the protective insulating film, or all or other of the patterns; A protection step of covering a part with a protective insulating film, a processing step of treating the wafer with ions or electrons, and a processing of the thin insulating film in a pattern not covered with the protective insulating film. A measuring step of measuring damage, wherein a series of steps including the protection step, the processing step, and the measuring step is repeated one or more times. 2. A thin insulating film having a thickness of 10 to 300 ° and a thicker insulating film are formed on a semiconductor substrate, and a conductive film is formed on the thin insulating film at an area ratio of 1 to 10000000 times that of the thin insulating film. Providing a wafer on which a plurality of patterns of the formed semiconductor device are arranged, covering a part of the pattern on the wafer with a protective insulating film, treating the wafer with ions or electrons, A protection step of peeling off the protective insulating film for all or a part of the pattern covered with the insulating film and covering the entire other pattern with a protective insulating film, and a processing step of treating the wafer with ions or electrons, Removing the protective insulating film and measuring damage to the thin insulating film, wherein the protecting step and the processing step are repeated one or more times. Evaluation methods. 3. The method according to claim 1, wherein the protective insulating film is an insulating film selected from the group consisting of silicon oxide, silicon nitride, and resist. 4. The method according to claim 1, wherein the measurement of the damage to the thin insulating film comprises measuring a current-voltage characteristic or a voltage-capacitance characteristic by applying a voltage between the semiconductor substrate and the conductive film. The method for evaluating a semiconductor device according to claim 1, wherein: