JPH11317080A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which the internal clock signals, that are synchronized with external clock signals, are supplied to a functional block arranged at an arbitrary position on a semiconductor chip. SOLUTION: A semiconductor integrated circuit 100 is formed on a semiconductor chip 1. The circuit 100 is provided with a first synchronous circuit 15, which outputs first internal clock signals INTCLK 1 that are synchronized with external clock signals EXTCLK supplied from the external of the chip 1, a DLL circuit 6, which outputs second internal clock signals INTCLK 2 synchronized with the signals INTCLK 1, and a functional block 2 which operates in synchronism with the signals INTCLK 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit formed on a semiconductor chip, and more particularly to a semiconductor integrated circuit that operates in synchronization with an external clock signal supplied from outside the semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, when a semiconductor integrated circuit formed on a semiconductor chip operates in synchronization with an external clock signal supplied from outside the semiconductor chip, an internal clock signal synchronized with the external clock signal is output. For output, a synchronous circuit such as a PLL (Phase-Locked Loop) circuit is used. The internal clock signal output from the synchronization circuit is supplied to each of a plurality of functional blocks formed on a semiconductor chip.

[0003]

However, due to various restrictions in laying out a synchronous circuit and a plurality of functional blocks on a semiconductor chip, the distance between the synchronous circuit and each functional block must be completely the same. It is difficult to do that. If the distance between the synchronization circuit and each functional block is different, a difference occurs in the transmission delay of the internal clock signal. This difference causes a skew of the internal clock signal. The skew of the internal clock signal becomes more serious as the frequency of the external clock signal increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and does not cause a skew of an internal clock signal, but allows a functional block disposed at an arbitrary position on a semiconductor chip to synchronize an internal clock synchronized with an external clock signal. It is an object to provide a semiconductor integrated circuit which can supply a clock signal.

Another object of the present invention is to provide a semiconductor integrated circuit which can operate at high speed in synchronization with an external clock signal.

Another object of the present invention is to provide a low power consumption semiconductor integrated circuit which can operate in synchronization with an external clock signal.

[0007]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit formed on a semiconductor chip. The semiconductor integrated circuit receives an external clock signal supplied from outside the semiconductor chip, and receives the external clock signal. And a first synchronizing circuit that outputs a first internal clock signal used inside the semiconductor chip, receives the first internal clock signal, synchronizes with the first internal clock signal, and A second synchronous circuit that outputs a second internal clock signal used inside the semiconductor chip; and a functional block that operates in synchronization with the second internal clock signal, thereby achieving the above object. Is done.

The first synchronization circuit has a first setup time required from an operation start request until the first synchronization circuit starts a synchronization operation, and the second synchronization circuit has an operation start time. It preferably has a second setup time required from the request until the second synchronization circuit starts the synchronization operation, and the second setup time is preferably shorter than the first setup time.

Preferably, the first synchronization circuit has a function of adjusting a duty ratio of the first internal clock signal.

[0010] The second synchronization circuit may be a mirror delay type DLL circuit including a circuit for advancing the phase of the second internal clock signal.

The semiconductor integrated circuit includes a plurality of second synchronization circuits, a plurality of function blocks, and at least one of the plurality of function blocks according to a function block selection signal.
And a selection circuit for selecting one of the plurality of second synchronization circuits, wherein each of the plurality of second synchronization circuits receives the first internal clock signal, synchronizes with the first internal clock signal, and is used inside the semiconductor chip. Outputting a second internal clock signal, wherein each of the plurality of functional blocks operates in synchronization with the second internal clock signal output from a corresponding one of the plurality of second synchronization circuits; And
The plurality of second synchronization circuits may be selectively activated according to the function block selection signal.

The plurality of functional blocks include a memory cell array block having a row circuit for receiving a row address and a column circuit for receiving a column address, wherein the row circuit responds to the function block selection signal. And the column-related circuits may operate in synchronization with the second internal clock signal.

The operation will be described below.

According to the first aspect of the present invention, the first internal clock signal synchronized with the external clock signal is output by the first synchronous circuit, and the second internal clock synchronized with the first internal clock signal by the second synchronous circuit. Signal is output,
A second internal clock signal is provided to the function block. The second synchronization circuit can be arranged at any position on the semiconductor chip. By arranging the second synchronization circuit near the functional block, it is possible to prevent the skew of the second internal clock signal from occurring regardless of the position of the functional block on the semiconductor chip.

According to the second aspect of the present invention, the first synchronization circuit having the first setup time and the second synchronization circuit having the second setup time shorter than the first setup time are used. Thus, by combining a synchronous circuit with a long setup time (for example, a PLL circuit) and a synchronous circuit with a short setup time (for example, a mirror delay type DLL circuit), the same type of synchronous circuit with a long setup time is combined. As compared with the case, the semiconductor integrated circuit can be operated at higher speed.

According to the third aspect of the invention, the duty ratio of the first internal clock signal can be adjusted to an appropriate value (typically, 1: 1) by the first synchronization circuit. Once the duty ratio of the first internal clock signal is adjusted to an appropriate value inside the semiconductor chip, the duty ratio of the second internal clock signal based on the first internal clock signal can further vary inside the semiconductor chip. Sex can be ignored in practice. Therefore, by adjusting the duty ratio of the first internal clock signal by the first synchronization circuit, the adjustment of the duty ratio of the second internal clock signal by the second synchronization circuit can be omitted. This makes it possible to use a synchronization circuit having no function of adjusting the duty ratio of the second internal clock signal as the second synchronization circuit.

According to the present invention, the phase of the second internal clock signal is advanced by the mirror delay type DLL circuit. Thereby, the phase of the second internal clock signal at a specific location on the semiconductor chip to which the second internal clock signal is supplied and the phase of the first internal clock signal input to the second synchronizing circuit can be matched. Will be possible.

According to the fifth aspect of the present invention, the plurality of second
The synchronization circuit is selectively activated according to the function block selection signal. Thus, the number of activated second synchronization circuits can be minimized. As a result, an increase in power consumption of the semiconductor integrated circuit can be prevented.

According to the invention, a semiconductor integrated circuit having a memory cell array block and capable of preventing an increase in power consumption can be obtained.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor integrated circuit 100 according to an embodiment of the present invention. The semiconductor integrated circuit 100 is formed on the semiconductor chip 1.

The semiconductor integrated circuit 100 includes a semiconductor chip 1
Operates in synchronization with an external clock signal EXTCLK supplied from the outside. The external clock signal EXTCLK is
For example, a system clock signal. The external clock signal EXTCLK is supplied to the external clock signal input (IN) 1
4 to the PLL circuit 15.

The PLL circuit 15 has an external clock signal EX.
It receives TCLK and outputs a first internal clock signal INTCLK1 synchronized with the external clock signal EXTCLK. Here, the first internal clock signal INTCLK1 is
This is a clock signal used inside the semiconductor chip 1.

The first internal clock signal INTCLK1 output from the PLL circuit 15 is connected to the internal clock signal line 10
Are supplied to the DLL circuits 6 and 7 via the internal clock signal line 11, and are supplied to the DLL circuits 8 and 9 via the internal clock signal line 11. First
Internal clock signal INTCLK1 is input to PLL circuit 15 via feedback line 27.

As described above, the first internal clock signal INTCLK1 input via the feedback line 27 is used for synchronizing with the external clock signal EXTCLK. Thereby, the first internal clock signal INTCLK
1 (for example, a point 1 near the DLL circuits 6 and 7 shown in FIG. 1)
02), the frequency and phase of the first internal clock signal INTCLK1 can be matched with the frequency and phase of the external clock signal EXTCLK.

Each of the DLL circuits 6 to 9 receives the first internal clock signal INTCLK1, and outputs a second internal clock signal INTCLK2 synchronized with the first internal clock signal INTCLK1. Here, the second internal clock signal INTCLK2 is a clock signal used inside the semiconductor chip 1.

The second internal clock signal INTCLK2 output from the DLL circuit 6 is supplied to the memory cell array block (MAB) 2 via the internal clock signal line 23. The second internal clock signal INTCLK2 output from the DLL circuit 7 is supplied to the memory cell array block (MAB) 3 via the internal clock signal line 24.
Second internal clock signal IN output from DLL circuit 8
TCLK2 is supplied to a memory cell array block (MAB) 4 via an internal clock signal line 25. DLL
Second internal clock signal INTCL output from circuit 9
K2 is supplied to the memory cell array block (MAB) 5 via the internal clock signal line 26.

Each of the memory cell array blocks 2 to 5 operates in synchronization with the second internal clock signal INTCLK2.

The memory cell array block 2 includes a memory cell array (MA) 2a including a plurality of memory cells and a row circuit (ROW) 2 operating in response to a row address.
b and a column-related circuit (COL) 2c that operates in response to a column address. Row-related circuit 2b includes a row address decoder, a word line drive circuit, and a sense amplifier (not shown). Column-related circuit 2c includes a column address decoder, a column selection circuit, and a data router circuit (not shown). Of the plurality of memory cells included in the memory cell array 2a, a memory cell at a position determined by the row-related circuit 2b and the column-related circuit 2c is accessed.

Each of the memory cell array blocks 3 to 5 has the same configuration as the memory cell array block 2.

As described above, according to semiconductor integrated circuit 100, external clock signal EXTC is generated by PLL circuit 15.
A first internal clock signal INTCLK1 synchronized with LK is output, and a second internal clock signal INTCLK2 synchronized with first internal clock signal INTCLK1 is output by each of DLL circuits 6 to 9. DLL circuit 6 ~
9, the second internal clock signal INTCLK2
Are supplied to the memory cell array blocks 2 to 5, respectively. The DLL circuits 6 to 9 can be arranged at arbitrary positions on the semiconductor chip 1. By arranging the DLL circuits 6 to 9 near the memory cell array blocks 2 to 5, the memory cell array blocks 2 to
5, the second internal clock signal INTC
The occurrence of skew of LK2 can be prevented.

The first internal clock signal INTCLK1 output from the PLL circuit 15 is connected to the internal clock signal line 17
Is supplied to the data input / output unit (DATA I / O) 20 via the. The data input / output unit 20 operates in synchronization with the first internal clock signal INTCLK1.

The data input / output unit 20 transmits data read from any one of the memory cell array blocks 2 to 5 to the external data bus 120 via the internal data signal line 21.
Or is used to input data from the external data bus 120 to any one of the memory cell array blocks 2 to 5 via the internal data signal line 21.

Further, the first internal clock signal INTCL
K1 is supplied to an address information input section (ADD) 12 and a block selection information input section (SEL) 13. The address information input unit 12 and the block selection information input unit 13
It operates in synchronization with the first internal clock signal INTCLK1.

The address information input section 12 receives address information from the packet input circuit 112 (PAC) in response to the first internal clock signal INTCLK1. The address information is, for example, 16-bit data. The address information input unit 12 outputs an address AD based on the address information. The address AD is supplied to the memory cell array blocks 2 to 5 via the address bus 19.
Address AD includes a row address and a column address.

The block selection information input section 13 receives block selection information from the packet input circuit 112 in response to the first internal clock signal INTCLK1. The block selection information is, for example, 2-bit data. The block selection information input unit 13 outputs a block selection signal BL based on the block selection information. Block selection signal B
L is supplied to the memory cell array blocks 2 to 5 and the DLL circuits 6 to 9 via the block selection signal line 18.

The packet input circuit 112 is connected to the external bus 11
0 to a predetermined number of packets (for example, 4 packets)
And analyze the contents of the predetermined number of packets. As a result, the packet input circuit 112 provides the address information to the address information input unit 12 and provides the block selection information to the block selection information input unit 13. The external bus 110 is, for example, a 5-bit bus. Thus, by inputting information to the semiconductor chip 1 using a predetermined number of packets, the bit width of the external bus 110 can be reduced.

Table 1 shows the relationship between the block selection information and the memory cell array block selected by the block selection signal BL. In this example, the block selection information is 2
Bit data. In Table 1, the 0th bit of the block selection information is described as B0, and the first bit of the block selection information is described as B0.
The bit is denoted as B1.

[0039]

[Table 1]

For example, block selection information (B0, B1)
When = (0,0), the memory cell array block 2 is selected by the block selection signal BL. As described above, one of the memory cell array blocks 2 to 5 is selected according to the value of the block selection information (B0, B1).

Further, block selection information (B0, B1)
, One of DLL circuits 6 to 9 is activated. The DLL circuit activated among the DLL circuits 6 to 9 is a DLL circuit corresponding to a memory cell array block selected from the memory cell array blocks 2 to 5.

For example, when the memory cell array block 2 is selected by the block selection signal BL, the DLL circuit 6 corresponding to the selected memory cell array block 2 is activated. The activated DLL circuit 6 starts operating. Thus, the DLL circuit 6 starts operating in response to the level change of the block selection signal BL.
As a result, the DLL circuit 6 outputs the first internal clock signal IN
Second internal clock signal INTCL synchronized with TCLK1
K2, and its second internal clock signal INTCLK
2 starts output. On the other hand, DLL circuits 7 to corresponding to memory cell array blocks 3 to 5 other than memory cell array block 2 selected by block select signal BL.
9 is not activated. That is, the DLL circuits 7 to 9 are stopped. Therefore, the second internal clock signal INTCLK2 is not output from the DLL circuits 7 to 9.

As described above, DLL circuits 6 to 9 are selectively activated in accordance with block select signal BL. That is, the DLL circuit corresponding to the memory cell array block selected in response to the block selection signal BL (that is, the memory cell array block in the operating state) is activated, and the memory cell array blocks other than the selected memory cell array block (that is, standby). The DLL circuit corresponding to the state memory cell array block) is not activated. Thus, the number of DLL circuits in the activated state can be minimized. As a result, an increase in power consumption of the semiconductor integrated circuit 100 can be prevented.

The setup time required to set up the PLL circuit 15 (ie, the time from the operation start request to the actual start of the synchronous operation of the PLL circuit 15) is T _S1 , and the DLL circuits 6 to 9 are set up. Assuming that the required setup time (that is, the time from the operation start request until the DLL circuits 6 to 9 actually start synchronous operation) is T _S2 , T _S2 <T _S1 . That is, the setup time of the DLL circuits 6 to 9 is shorter than the setup time of the PLL circuit 15. For example, while the setup time of the PLL circuit 15 is several hundred clock cycles, the setup time of the mirror delay type DLL circuit described later with reference to FIG. 4 is only two clock cycles.

As described above, by combining a synchronous circuit having a long setup time (for example, a PLL circuit) and a synchronous circuit having a short setup time (for example, a mirror delay type DLL circuit), the same type of synchronous circuit having a long setup time can be obtained. The semiconductor integrated circuit 100 can be operated at a higher speed than in a case where circuits are combined.

It should be noted that combining the same type of synchronous circuit with a short set-up time requires
Although it is advantageous in operating 0 at high speed, in the current state of the art, a synchronous circuit having a short setup time (for example,
The mirror delay type DLL circuit) has a disadvantage that it does not have a function of adjusting the duty ratio of the internal clock signal. The duty ratio of the internal clock signal is 1: 1
Therefore, it is preferable that the synchronization circuit has a function of adjusting the duty ratio of the internal clock signal. Therefore, in the current state of the art, the optimal combination is a combination of a synchronous circuit having a function of adjusting the duty ratio of the internal clock signal with a long setup time and a short setup time.

The PLL circuit 15 has a function of adjusting the duty ratio of the first internal clock signal INTCLK1 (ie, the ratio of the period during which the first internal clock signal INTCLK1 is at “H” level to the period during which the first internal clock signal INTCLK1 is at “L” level). Have. According to the PLL circuit 15, the duty ratio of the first internal clock signal INTCLK1 can be adjusted to an appropriate value (typically 1: 1).

Once the duty ratio of the first internal clock signal INTCLK1 is adjusted to an appropriate value inside the semiconductor chip 1, the second internal clock signal INTCLK2 based on the first internal clock signal INTCLK is adjusted inside the semiconductor chip 1. The possibility that the duty ratio further fluctuates can be ignored in practical use. Therefore, the PLL circuit 15
By adjusting the duty ratio of the first internal clock signal INTCLK1, the adjustment of the duty ratio of the second internal clock signal INTCLK2 by the DLL circuits 6 to 9 can be omitted. This makes it possible to use DLL circuits that do not have a function of adjusting the duty ratio of the second internal clock signal INTCLK2 as the DLL circuits 6 to 9.

For example, the DLL circuit of the mirror delay type differs from the PLL circuit 15 in that the second internal clock signal I
It does not have a function of adjusting the duty ratio of NTCLK2. However, by using a mirror delay type DLL circuit as the DLL circuits 6 to 9 and further combining the PLL circuit 15 and the mirror delay type DLL circuits 6 to 9, the above-mentioned mirror delay type of the setup time is extremely short. The advantages of the DLL circuit can be utilized.

For example, according to the mirror delay type DLL circuit described later with reference to FIG.
, The second internal clock signal INTCLK2 can be synchronized with the first internal clock signal INTCLK1 in two clock cycles after the operation starts.
As described above, the synchronous circuit having a short setup time is
By using as the circuits 6 to 9, the DLL circuits 6 to
9 can be started up at high speed.

FIG. 2 shows the operation timing of the semiconductor integrated circuit 100. As described above, the first internal clock signal INTCLK1 is synchronized with the external clock signal EXTCLK by the PLL circuit 15.

[0052] from the time T _1, the external clock signal EXTC
The four packets PACKET are input from the external bus 110 to the packet input circuit 112 in synchronization with the LK. The four packets PACKET include address information, block selection information, and other information (for example, Read / Write).
e indicating control).

At time T ₂ , the packet input circuit 11
2 is N based on the contents of the four packets PACKET
Commands COMMAND # 1 to COMMAND # N
Generate Here, N is an arbitrary integer of 1 or more.
Commands COMMAND # 1 to COMMAND # N are:
Used to access memory cell array blocks 2-5. For example, the command COMMAND # 1 is “address information” and the command COMMAND # 2
Is “block selection information”.

[0054] At time T _3, the block selection signal BL
Changes from “L” level to “H” level.
In response to the level change of the block selection signal BL, one of the memory cell array blocks 2 to 5 and the DLL circuits 6 to 9 corresponding to the selected memory cell array block.
Is selected. As a result, the operation of the row-related circuits included in the selected memory cell array block is started, and the operation of the selected DLL circuit is started.

If the selected DLL circuit is the above-mentioned mirror delay type DLL circuit, the selected DLL circuit
L circuit, from the time T ₃ after two clock cycles, first
The output of the second internal clock signal INTCLK2 synchronized with the internal clock signal INTCLK1 is started.

The operation of the column related circuit included in the selected memory cell array block is such that the selected DLL circuit operates in synchronization with the first internal clock signal INTCLK1.
The operation is started after the output of the internal clock signal INTCLK2 is started.

As described above, in the selected memory cell array block, the operation of the row-related circuit is started, and thereafter, the operation of the column-related circuit is started. The operation of the row-related circuit is started in response to the block selection signal BL.
This is because the operation of the row circuit does not need to be synchronized with a high-speed clock signal. On the other hand, the operation of the column-related circuit is such that the selected DLL circuit operates on the second internal clock signal INT synchronized with the first internal clock signal INTCLK1.
It starts after the output of CLK2 is started. This is because the column circuit needs to operate in synchronization with the second internal clock signal INTCLK2.

The operation of the selected DLL circuit is started in response to the block selection signal BL.

The selected memory cell array block
In order for the circuit to operate normally, the selected DLL circuit
Setup time (in FIG. 2, time T_SIs written as
The operation marker of the selected memory cell array block
Gin time (in FIG. 2, time T _MThan written)
It is necessary to satisfy the condition that it is short. Where selected
The setup time of the DLL circuit is the selected DL
After the L circuit starts operating, the first internal clock signal IN
Second internal clock signal INTCL synchronized with TCLK1
Supply K2 to selected memory cell array block
The time required by Also selected note
The operation margin time of the recell array block is
Column circuits start operating after the other circuits start operating.
Time to start.

Since a row-related circuit activates a memory cell connected to a row (word line) to which an address is input, a desired time is required until the operation of the row-related circuit is completed. A column circuit selects an activated memory cell to read and write data. For this reason, the operation of the column circuit cannot be started until after the operation of the row circuit is completed.

As described above, the mirror delay type DL
If an L circuit is used, time T _S is only two clock cycles. Therefore, it is easy to satisfy the condition of time T _S <time T _M. As a result, the selected memory cell array block can operate normally.

As described above, the memory cell array block 2
When any one of the operations (1) to (5) starts operation, the address AD has already been input from the address information input unit 12 via the address bus 19 to the memory cell array block. Therefore, a memory cell corresponding to the address AD can be accessed.

FIG. 3 shows memory cell array blocks 2 to 5
3 shows the transition of the operation state of FIG.

[0064] At the time T _21, the block selection signal BL
When the memory cell array block 2 and the DLL circuit 6 are selected, the operation of the row circuit 2b included in the memory cell array block 2 and the operation of the DLL circuit 6 (setup operation) are started.

[0065] At time T _22, the operation of the circuit 2c of the column system included in the memory cell array block 2 is started. At time T ₂₂ (more preferably, prior to the time T _22), the first internal clock signal from the DLL circuit 6 IN
Second internal clock signal INTCL synchronized with TCLK1
The output of K2 is started.

[0066] At time T _23, the operation of the operation and the DLL circuit 6 of the memory cell array block 2 is completed.

[0067] In the time T ₂₁ ~ time T _23, does not operate the memory cell array blocks 3-5 and DLL circuit 7-9.

Similarly, one set of a memory cell array block and a DLL circuit can be selected by a block selection signal BL. Note that the order in which the memory cell array blocks 2 to 5 are selected is arbitrary.

As described above, only the DLL circuit selected among the DLL circuits 6 to 9 is operated, and the unselected DLL circuit is selected.
By stopping the LL circuits, the number of operating DLL circuits can be minimized. Thus, it is possible to prevent unnecessary power consumption by the DLL circuit in the standby state. As a result, the semiconductor integrated circuit 10
0 can be significantly reduced. This power reduction effect is particularly remarkable when the setup time of the DLL circuits 6 to 9 is short. This is because the operation time of the DLL circuits 6 to 9 can be shortened.

FIG. 4 shows a DLL circuit 4 of a mirror delay type.
00 is shown. Mirror delay type DLL circuit 40
0 may be used as DLL circuits 6-9 shown in FIG.

Such a mirror delay type DLL circuit is, for example, “A 2.5 ns Clock Access”.
ss 250MHz 256Mb SDRAM wit
ha Synchronous Mirror Del
ay, 1996 IEEE International
al Solid-State CircuitsCo
nreference pp. 374-375 ".

The DLL circuit 400 of the mirror delay type comprises:
It includes a clock signal input unit 31, a phase adjustment unit 32, a mirror delay circuit 33, and a clock signal output unit.

The clock signal input section 31 is, for example, an input buffer. The clock signal output unit 34 is, for example,
Output driver. Here, the clock signal input unit 31
The delay amount of the clock signal by the clock signal output unit 34 is d ₁ , and the delay amount of the clock signal by the clock signal output unit 34 is d ₂ .

A predetermined delay amount can be set in advance in the phase adjustment unit 32. Here, it is assumed that the delay amount of the clock signal by the phase adjustment unit 32 is set to (d ₁ + d ₂ ).

The mirror delay circuit 33 includes 2m unit delay elements 40a-1 to 40a-m and 40b-1 to 40b-4.
0b-m, and a delay setting circuit 41 that controls on / off of the m switching elements 42-1 to 42-m according to the output from the clock signal input unit 31. Here, m is an arbitrary integer of 1 or more.

The delay setting circuit 41 includes m unit delay elements 40a-1 to 40a included in the mirror delay circuit 33.
One of the switching elements 42-1 to 42-m is turned on so that the amount of delay of the clock signal by one or more unit delay elements of −m becomes (tCK− (d ₁ + d ₂ )), The other (m-1) switching elements are turned off. Here, tCK indicates one clock cycle of the clock signal.

For example, unit delay elements 40a-1 and 40a-1
The delay amount of the clock signal due to 0a-2 is (tCK- (d
₁ + d ₂ )), as shown in FIG.
The delay setting circuit 41 turns on the switching element 42-2, and switches the switching elements 42-1 and 42-3 to 42-m
Turn off. In this case, the unit delay element 40b-1
And the delay amount of the clock signal due to 40b-2 is also (t
CK− (d ₁ + d ₂ )). That is, in the mirror delay circuit 33, the clock signal is transmitted in the order of the unit delay element 40a-1, the unit delay element 40a-2, the switching element 42-2, the unit delay element 40b-2, and the unit delay element 40b-1. This is because that.

The total amount of delay D caused by the transmission of the clock signal from the input terminal 36 to the output terminal 35
Is obtained by (Equation 1).

[0079]

D = d₁+ (D₁+ D_Two) + ｛TCK− (d₁+ D
_Two)｝ + ｛TCK− (d₁+ D _Two)｝ + D_Two= 2 · tCK (Equation 1) is the clock signal input to the input terminal 36.
A clock signal delayed by two clock cycles
Is output from the output terminal 35.

According to the DLL circuit 400 of the mirror delay type, after the clock signal is input to the input terminal 36,
After the clock cycle, a clock signal having the same phase as that of the clock signal can be output from the output terminal 35. Mirror delay type DLL circuit 40
Reference numeral 0 denotes a DLL circuit of the type that requires the shortest time (ie, the setup time) required to synchronize the input clock signal and the output clock signal among the existing DLL circuits.

The DLL circuit 400 of the mirror delay type comprises:
It does not have a function to adjust the duty ratio of the clock signal. However, by combining a synchronous circuit (for example, PLL circuit 15) having a function of adjusting the duty ratio of a clock signal with a mirror delay type DLL circuit 400, this disadvantage can be compensated. For example,
The first internal clock signal INTC is generated by the PLL circuit 15.
After adjusting the duty ratio of LK1 to an appropriate value, the adjusted first internal clock signal INTCLK1 may be input to the mirror delay type DLL circuit 400. Thus, the advantage of the mirror delay type DLL circuit 400 that the setup time is extremely short can be utilized.

By using the mirror delay type DLL circuit 400 as the DLL circuits 6 to 9, the second internal clock signal INTCLK2 synchronized with the first internal clock signal INTCLK1 is supplied to the memory cell array blocks 2 to 5.
Can be supplied to

In an actual design, the delay amount of the phase adjustment unit 32 is not (d ₁ + d ₂ ) but (d ₁ + d ₂ −
α). This means that the mirror delay type D
The phase of the clock signal output from the LL circuit is represented by a delay amount α
Means to advance by the amount corresponding to. Where α
Is predetermined in consideration of the transmission delay from the mirror delay type DLL circuit to the memory cell array block.
This makes it possible to make the phase of the first internal clock signal INTCLK1 input to the mirror delay type DLL circuit coincide with the phase of the second internal clock signal INTCLK2 supplied to the memory cell array block.

The phase of the clock signal output from the mirror delay type DLL circuit is
3 may be advanced.

FIG. 5 shows a DLL circuit 5 of a mirror delay type.
00 is shown. Mirror delay type DLL circuit 50
0 may be used as DLL circuits 6-9 shown in FIG. 5, the same components as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.

The mirror delay type DLL circuit 500
The clock signal is output from a connection point P between the unit delay element 40b-1 and the unit delay element 40b-2 of the mirror delay circuit 33. The clock signal from the connection point P is output from the output terminal 38 via the clock signal output unit 37. The clock signal output unit 37
For example, an output driver. Here, it is assumed that the amount of delay of the clock signal by the clock signal output unit 37 is d ₂ , similarly to the clock signal output unit 34.

When the clock signal output from the output terminal 35 and the clock signal output from the output terminal 38 are compared, the phase of the latter clock signal is
The phase of the former clock signal is advanced by the amount corresponding to the delay amount due to b-1. This is because the former clock signal passes through the unit delay element 40b-1, whereas the latter clock signal does not pass through the unit delay element 40b-1.

Connection point P in mirror delay circuit 33
By adjusting the position, the amount of advance of the phase of the clock signal output from the output terminal 38 can be adjusted. Here, the position of the connection point P is a mirror delay type D
It is predetermined in consideration of the transmission delay from the LL circuit 500 to the memory cell array block.

By supplying the clock signal output from the output terminal 38 to the memory cell array block as the second internal clock signal INTCLK2, the phase of the first internal clock signal INTCLK1 input to the mirror delay type DLL circuit 500 and the memory The phase of the second internal clock signal INTCLK2 supplied to the cell array block can be matched.

Alternatively, both the clock signal output from output terminal 35 and the clock signal output from output terminal 38 may be supplied to the memory cell array block. In this case, of the plurality of circuits included in the memory cell array block, a mirror delay type D
The circuit arranged near the LL circuit 500 operates in synchronization with the clock signal output from the output terminal 35,
A circuit located far from the mirror delay type DLL circuit 500 may operate in synchronization with a clock signal output from the output terminal 38. Such control increases the operation margin in each circuit included in the memory cell array block. As a result, data can be transmitted at higher speed.

Alternatively, data is read from the memory cell array block in synchronization with the clock signal output from the output terminal 38, and data is read from the memory cell array block to the data input / output unit 20 in synchronization with the clock signal output from the output terminal 35. May be transmitted. Such an operation increases an operation margin in each circuit included in the semiconductor integrated circuit 100. As a result, data can be transmitted at higher speed.

Table 2 shows combinations of the first synchronization circuit and the second synchronization circuit to which the present invention can be applied. Here, the first synchronization circuit refers to a synchronization circuit that outputs a first internal clock signal INTCLK1 synchronized with the external clock signal EXTCLK, and the second synchronization circuit refers to a first internal clock signal ICLK.
Second internal clock signal INTC synchronized with NTCLK1
It refers to a synchronous circuit that outputs LK2.

[0093]

[Table 2]

Here, in Table 2, “PLL” means PL
L indicates an L circuit, “DLL” indicates a DLL circuit, and “MD”
"-DLL" indicates a mirror delay type DLL circuit.

The PLL circuit indicated by “PLL” in Table 2 is obtained by changing the frequency of the oscillation circuit according to the comparison result between the phase of the reference clock signal and the phase of the clock signal output from the oscillation circuit. A circuit that outputs a clock signal synchronized with the reference clock signal.
A typical configuration of the PLL circuit is shown in FIG. 6A. For example, the PLL circuit 15 shown in FIG. 1 can have the configuration shown in FIG. 6A.

The DLL circuit indicated by "DLL" in Table 2 is obtained by adjusting the delay amount of the delay circuit according to the result of comparison between the phase of the reference clock signal and the phase of the clock signal output from the delay circuit. , A circuit that outputs a clock signal synchronized with a reference clock signal. D
A typical configuration of the LL circuit is shown in FIG. 6B. For example, the DLL circuits 6 to 9 shown in FIG. 1 can have the configuration shown in FIG. 6B.

In Table 2, the mirror delay type DLL circuit indicated by "MD-DLL" refers to a DLL circuit having a mirror delay circuit. A typical configuration of a mirror delay type DLL circuit is shown in FIG. 4 or FIG. For example, the DLL circuits 6 to 9 shown in FIG. 1 can have the configuration shown in FIG. 4 or FIG.

In the above-described embodiment, a combination in which a PLL circuit (PLL) is used as the first synchronization circuit and a mirror delay type DLL circuit (MD-DLL) is used as the second synchronization circuit (that is, Table 2). Combination # 3). However, the invention is not limited to this combination.

For example, in order to achieve the purpose of “supplying an internal clock signal synchronized with an external clock signal to a functional block disposed at an arbitrary position on a semiconductor chip”, an arbitrary combination shown in Table 2 is required. (That is,
Combination # 1 to combination # 6) may be used.

In order to achieve the purpose of "operate at high speed in synchronization with an external clock signal", it is preferable to use the combination # 3, # 5 or # 6 in Table 2. This is because it is appropriate to use a mirror delay type DLL circuit having a short setup time in order to perform high-speed operation. Further, the combination # 2 or # 4 in Table 2 can be adopted. These combinations are
Although the operation speed is lower than the combination # 3, # 5 or # 6 of Table 2, the operation speed is faster than the combination # 1 of Table 2.

Combination # 6 in Table 2 is the best combination from the viewpoint of high-speed operation, but in combination # 6 in Table 2, the duty ratio of the clock signal is adjusted to an appropriate value (for example, 1: 1). Can not do it. This is because the mirror delay type DLL circuit does not have a function of adjusting the duty ratio of the clock signal. Therefore,
Considering the two viewpoints of high-speed operation and stable supply of the clock signal, it is preferable to use the combination # 3 or # 5 in Table 2.

Needless to say, if a synchronous circuit having a short setup time and a function of adjusting the duty ratio of the clock signal is developed in the future, two viewpoints, that is, high-speed operation and stable supply of the clock signal will be considered. Therefore, the combination of the same type of synchronous circuits is the best combination.

FIG. 6A shows a typical configuration example of a PLL circuit. The PLL circuit includes a phase comparison circuit 130, a charge pump 132, and an oscillation circuit (VCO) 134.

The phase comparison circuit 130 compares the phase of the reference clock signal F _{REF with} the phase of the clock signal F _O output from the oscillation circuit 134, and according to the result of the comparison, the voltage rise signal V _U or the voltage fall signal. charge the V _D pump 1
32. The charge pump 132 increases the control voltage V _CTRL in response to the voltage increase signal V _U, lowers the control voltage V _CTRL in response to the voltage falling signal V _D. The oscillating circuit 134 changes the frequency of the clock signal according to the control voltage _VCTRL . By such feedback control, the clock signal F _O synchronized with the reference clock signal F _REF is output from the oscillation circuit 134.

FIG. 6B shows a typical configuration example of a DLL circuit. The DLL circuit includes a phase comparison circuit 140, a charge pump 142, and a delay circuit (VCDL) 144.

The phase comparison circuit 140 compares the phase of the reference clock signal F _{REF with} the phase of the clock signal F _O output from the delay circuit 144, and according to the result of the comparison, the voltage rise signal _VU or the voltage fall signal. charge the V _D pump 1
42. The charge pump 142 increases the control voltage V _CTRL in response to the voltage increase signal V _U, lowers the control voltage V _CTRL in response to the voltage falling signal V _D. The delay circuit 144 varies a delay amount according to the control voltage _VCTRL . Thereby, with respect to the reference clock signal F _REF ,
Delay amount of the clock signal F _O output from the delay circuit 144 varies. With such feedback control,
A clock signal F _O synchronized with the reference clock signal F _REF is output from the delay circuit 144.

FIG. 7 shows a modification of the semiconductor integrated circuit of the present invention. In FIG. 7, the semiconductor integrated circuit is designated by reference numeral 70.
Represented by 0. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 7, a clock signal distribution unit (DST) 16 is inserted between the PLL circuit 15 and the internal clock signal lines 10 and 11. An OR circuit (OR) 30 is inserted between the PLL circuit 15 and the feedback lines 27 and 28.

Clock signal distribution section 16 outputs first internal clock signal INTCLK1 to one of internal clock signal line 10 and internal clock signal line 11 in accordance with block select signal BL.

When a set of memory cell array block 2 and DLL circuit 6 or a set of memory cell array block 3 and DLL circuit 7 is selected by block select signal BL, clock signal distribution unit 16 sets PLL.
The first internal clock signal INTC supplied from the circuit 15
LK1 is output to the internal clock signal line 10 and is not output to the internal clock signal line 11. As a result, the first internal clock signal INTCLK1 is supplied to the DLL circuits 6 and 7 connected to the internal clock signal line 10.

When a set of memory cell array block 4 and DLL circuit 8 or a set of memory cell array block 5 and DLL circuit 9 is selected by block select signal BL, clock signal distribution unit 16 sets PLL
The first internal clock signal INTC supplied from the circuit 15
LK1 is output to the internal clock signal line 11 and is not output to the internal clock signal line 10. As a result, the first internal clock signal INTCLK1 is supplied to the DLL circuits 8 and 9 connected to the internal clock signal line 11.

The first signal output to the internal clock signal line 10
The internal clock signal INTCLK1 is input to the OR circuit 30 via the feedback line 27. First internal clock signal INTC output to internal clock signal line 11
LK1 is connected to an OR circuit 30 via a feedback line 28.
Is input to The OR circuit 30 includes a feedback line 27
An OR operation is performed on the above signal and the signal on the feedback line 28, and a signal indicating the result of the operation is output to the PLL circuit 15.

Thus, the internal clock signal line 10
When the first internal clock signal INTCLK1 is output to the PLL via the feedback line 27 and the OR circuit 30,
This is fed back to the circuit 15. When the first internal clock signal INTCLK1 is output to the internal clock signal line 11, the first internal clock signal INTCLK1
Through the feedback line 28 and the OR circuit 30
This is fed back to the LL circuit 15. PLL circuit 15
Internal clock signal INTC fed back to
LK1 is used to synchronize with external clock signal EXTCLK.

FIG. 8 shows another modification of the semiconductor integrated circuit of the present invention. In FIG. 8, the semiconductor integrated circuit is represented by reference numeral 800. 8, the same components as those shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 8, the frequency dividing circuit (DI
V) 51 is inserted between the PLL circuit 15 and the clock signal distribution unit 16.

The frequency dividing circuit 51 forms a frequency-divided internal clock signal INTCLK1 'by dividing the frequency of the first internal clock signal INTCLK1 supplied from the PLL circuit 15. The divided internal clock signal INTCLK1 ′ is
The clock signal distribution unit 16 controls the internal clock signal line 1
0 or output to the internal clock signal line 11.

The dynamic random access memory (D
RAM), it takes time to read data from a memory cell.
The frequency of an internal clock signal is made lower than the frequency of an external clock signal. Therefore, lowering the frequency of the first internal clock signal INTCLK1 using the frequency dividing circuit 51 as shown in FIG.
It is suitable for a semiconductor chip having a memory which operates relatively slowly as described above.

In the embodiment described above, one memory cell array block and one memory cell array block are controlled by the block selection signal.
And two DLL circuits. However, the present invention is not limited to this. A plurality of memory cell arrays and a plurality of DLL circuits may be selected by a block selection signal.

Further, in the above-described embodiment, the memory cell array block has been described as an example of a functional block for executing a predetermined function. However, the present invention is not limited to this. The present invention can be applied to any semiconductor integrated circuit other than a memory. Second internal clock signal INTCLK2
Can be supplied to any functional block other than the memory cell array block.

[0120]

According to the present invention, an internal clock signal synchronized with an external clock signal can be supplied to a functional block disposed at an arbitrary position on a semiconductor chip without causing skew of the internal clock signal. it can.

Further, according to the present invention, it becomes possible to operate a semiconductor integrated circuit at high speed in synchronization with an external clock signal.

Further, according to the present invention, it is possible to reduce the power consumption of a semiconductor integrated circuit that operates in synchronization with an external clock signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing operation timings of the semiconductor integrated circuit shown in FIG.

FIG. 3 is a timing chart showing a transition of an operation state of a memory cell array block in the semiconductor integrated circuit shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration of a mirror delay type DLL circuit that can be used in the semiconductor integrated circuit shown in FIG. 1;

FIG. 5 is a block diagram showing another configuration of the mirror delay type DLL circuit.

FIG. 6A is a block diagram illustrating a typical configuration example of a PLL circuit.

FIG. 6B is a block diagram illustrating a typical configuration example of a DLL circuit.

FIG. 7 is a block diagram showing a modification of the semiconductor integrated circuit shown in FIG.

FIG. 8 is a block diagram showing a further modification of the semiconductor integrated circuit shown in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2-5 Memory cell array block 2a, 3a, 4a, 5a Memory cell array 2b, 3b, 4b, 5b Row system circuit 2c, 3c, 4c, 5c Column system circuit 6-9 DLL circuits 10, 11, 17 Internal clock signal line 12 Address information input unit 13 Block selection information input unit 14 External clock signal input unit 15 PLL circuit 18 Block selection signal line 19 Address bus 20 Data input / output unit 21 Data bus 23 to 26 Internal clock signal line 27, 28 Feedback line 30 OR circuit 100 Semiconductor integrated circuit 110 External bus 112 Packet input circuit 120 External data bus

Claims (6)

[Claims] 1. A semiconductor integrated circuit formed on a semiconductor chip, comprising: receiving an external clock signal supplied from outside the semiconductor chip, synchronizing with the external clock signal, and
A first synchronizing circuit for outputting a first internal clock signal used inside the semiconductor chip, receiving the first internal clock signal, synchronizing with the first internal clock signal, and inside the semiconductor chip A semiconductor integrated circuit comprising: a second synchronization circuit that outputs a second internal clock signal to be used; and a functional block that operates in synchronization with the second internal clock signal. 2. The first synchronization circuit has a first set-up time required from an operation start request to a time when the first synchronization circuit starts a synchronization operation, and the second synchronization circuit includes: 2. The apparatus according to claim 1, further comprising a second setup time required from an operation start request to a time at which the second synchronization circuit starts a synchronization operation, wherein the second setup time is shorter than the first setup time. A semiconductor integrated circuit as described in the above. 3. The first synchronization circuit has a function of adjusting a duty ratio of the first internal clock signal.
The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein said second synchronization circuit is a DLL circuit of a mirror delay type including a circuit for advancing the phase of said second internal clock signal. 5. A semiconductor integrated circuit comprising: a plurality of second synchronization circuits; a plurality of function blocks; and a selection circuit for selecting at least one of the plurality of function blocks according to a function block selection signal. Wherein each of the plurality of second synchronization circuits receives the first internal clock signal, and outputs a second internal clock signal synchronized with the first internal clock signal and used inside the semiconductor chip. And each of the plurality of functional blocks includes the plurality of second blocks.
The synchronous circuit operates in synchronization with the second internal clock signal output from the corresponding one of the second synchronous circuits, and the plurality of second synchronous circuits are selectively activated according to the functional block selection signal. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is integrated. 6. The plurality of functional blocks include a memory cell array block having a row-related circuit for receiving a row address and a column-related circuit for receiving a column address, wherein the row-related circuit includes a function block selection signal. 6. The semiconductor integrated circuit according to claim 5, wherein said column-related circuit operates in synchronization with said second internal clock signal.