JPH11316712A - Cache device, consistency controller, protocol conversion device and multiprocessor device connecting the same and plural processors - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor device permitting the existence of a plurality of writing rights for the same memory block. SOLUTION: A plurality of cache devices 2a and 2b connected to a plurality of processors 1a and 1b, a consistency control part 5 connected to a plurality of cache devices 2a and 2b and a main storage 3 are installed in a multiprocessor device. The cache devices 2a or 2b caches data accessed by the cache device 2a or 2b, manages cached data in a memory block unit and emits a pertinent memory block to the consistency control part 5 when the rewriting request of the memory block is given from the consistency control part 5. The consistency control part 5 synthesizes data in the memory block, which is received from the cache 2a or 2b, and stores the synthesized memory block in the main storage 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor which performs processing while exchanging information between processors via a main memory, and more particularly to a multiprocessor which employs a weak memory consistency model and is used in the multiprocessor. The present invention relates to a cache device, a consistency control device, and a protocol conversion device.

[0002]

2. Description of the Related Art In various fields such as multimedia processing and high-definition image processing, demands for improving processor performance have been increasing in recent years. However, the current LSI (La
rge Scale Integration) Manufacturing technology has a limit to the speed of devices. Therefore, a multiprocessor device of a distributed processing system is receiving attention and is being actively researched and developed.

[0003] A processor device equipped with a single processor often stores data that is highly likely to be referenced by the processor, and is provided with a cache so that it can respond to the memory access of the processor at high speed. For example, there is a microprocessor in which a cache having a capacity of 8 Kbytes is integrated, and the performance of the system can be improved. In this microprocessor, the memory space of the cache is divided into 16 bytes, and the cache is managed in units of 16 bytes. Such a memory fragment divided into a predetermined number of bytes, for example, 16 bytes, is hereinafter referred to as a memory block. In a processor device that employs a write-back cache, an update process by a store instruction of the processor is completed only by updating a copy of a memory block in the cache. The updated copy of the memory block in the cache is written back to the main memory by an instruction from the processor or a replacement process caused by a shortage of the cache capacity. Therefore, performance is generally improved as compared with a processor device employing a write-through cache that directly updates the main memory every time a processor executes a store instruction. However, until the write-back occurs, the contents of the data of the memory block in the main memory and the updated copy of the memory block in the cache do not match.

[0004] A cache is similarly employed in a multiprocessor device equipped with a plurality of processors. In a multiprocessor device, two types of caches are employed: a cache unique to each processor and a cache shared by a plurality of processors. Hereinafter, a cache unique to each processor is simply called a cache, and a cache shared by a plurality of processors is called an auxiliary cache. The cache in the multiprocessor device not only responds to memory access at high speed, but also has a function of reducing traffic on the interconnection network interconnecting the processor and the main memory.

However, the use of the cache means that a copy of the same memory block exists in a plurality of caches. Therefore, when data in the cache is updated by the processor, the copy between the data in the main memory and the copy in the cache is performed. This causes a problem of so-called cache consistency. In order for a multiprocessor device to operate properly, an update of data in a cache by one processor must be correctly reflected in a reference to data by another processor. Here, a state in which data update by one processor is correctly reflected in reference by another processor is called a state in which memory consistency is maintained, and what kind of result is obtained by a series of memory accesses by a plurality of processors. Is defined as a memory consistency model, and a model on which a program is written so as to maintain a memory consistency is called a memory consistency model.

[0006] Conventionally, there are many methods for guaranteeing memory consistency. One of the classifications of the method of guaranteeing the memory consistency is to classify the method into a method by invalidation and a method by update. The invalidation method is a method in which, when a copy of a memory block in a cache is updated by one of the processors, the other copy of the cache is erased. Thereafter, when the processor attempts to reference the invalidated memory block from the cache, it is supplied directly from the cache having the updated copy of the memory block to the latest value, or via the main memory or the auxiliary cache. You. The update method is a method in which, when a copy of a memory block in any cache is updated, a copy of a memory block in another cache is also updated. In either method, the processor can refer to the contents of the new memory block by reading the memory block from the cache.

As another classification method, there is a classification into a method using a snoop mechanism and a method using a directory mechanism. The snoop mechanism is a mechanism widely used in a bus-coupled multiprocessor device, and broadcasts a request over a bus when a cache updates a memory block or reads from a main memory.
Other caches then monitor the request and write back, invalidate, or update the copy of the memory block as needed. On the other hand, the directory mechanism
It manages which cache has a copy of each memory block and writes back, invalidates, or updates as needed.

FIG. 50 is a diagram showing a structure of an entry provided in a cache in a multiprocessor device disclosed in Japanese Patent Application Laid-Open No. 5-61770. In this entry, the write right flag is used for exclusive write right management. For each memory block, two or more cache entries in which this write right flag is set in the multiprocessor device. Control is performed so that it does not exist. Further, the processor cannot update this copy of the memory block unless the write right flag in the cache entry in the cache is set. Therefore, in this multiprocessor device, before the processor updates the copy of the memory block in the cache, the processor acquires the exclusive write right to the memory block, and acquires the exclusive write right to the memory block. Invalidate the copy of the memory block stored in the cache that does not have it. This guarantees that the updated copy of the memory block exists only in one cache having exclusive write right, thereby guaranteeing the memory consistency.

[0009] The size of the data accessed by the processor is in most cases smaller than the size of the memory block. Therefore, a false sharing state occurs in which different processors access different data in the same memory block. In the above-mentioned multiprocessor device, when this false sharing occurs, even if it accesses different data, a process for guaranteeing consistency is performed in memory block units.

[0010] Further, "Memory Consistency and Event O
rdering in Scalable Shared-Memory Multiprocessors
(Pp. 15-26, 17th Annual International Symposiu
Focusing on the flow of programs in the mon on Computer Architecture), it has been shown that a strong memory consistency model that guarantees memory consistency for each memory access of a processor is not always necessary, and a weak memory consistency model was adopted. Multiprocessor devices have been proposed. However, in the conventional multiprocessor described above, a strong memory consistency model that guarantees a memory consistency for each memory access is employed.

[0011]

However, when false sharing occurs in the above-described conventional multiprocessor device, the exclusive write right of the memory block containing the data to be updated is moved, and this write right is transferred. The data which is not related to the data updated by the movement of the data is invalidated. Such invalidation of unnecessary data increases the average access time of the memory. Therefore, the conventional multiprocessor has a problem that the processing performance is reduced due to false sharing.

Also, in a multiprocessor device which maintains consistency by updating a copy of a memory block stored in another cache, when false sharing occurs, a message for updating a memory block in each cache is generated. There has been a problem that a large number of such cases occur and the processing performance deteriorates. These problems occur in a multiprocessor device employing either the snoop mechanism or the directory mechanism when guaranteeing memory consistency by exclusive writing right to a memory block.

Further, in the above-described multiprocessor device, since a program is created based on a weak memory consistency model, even if no problem occurs even if the consistency is not maintained, each memory access A process for maintaining consistency is performed every time. Therefore, an unnecessary message is generated, and there is a problem that the processing performance is reduced as in the case of false sharing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention described in claims 1 and 2 is to provide the same memory block under a weak memory consistency model. An object of the present invention is to provide a cache device capable of constructing a multiprocessor device that allows the existence of a plurality of write rights.

[0015] It is an object of the present invention to construct a multiprocessor device which allows a plurality of write rights to the same memory block under a weak memory consistency model. It is to provide a possible consistency control device.

An object of the present invention described in claims 10 and 11 is to provide a multiprocessor device which permits the existence of a plurality of write rights to the same memory block even when an existing processor unit is used. An object of the present invention is to provide a protocol conversion device that can be constructed.

The objects of the invention described in claims 12 to 17 are:
An object of the present invention is to provide a multiprocessor device that allows the existence of a plurality of write rights to the same memory block under a weak memory consistency model.

An object of the invention described in claim 18 is to provide a multiprocessor device which allows the existence of a plurality of write rights to the same memory block using an existing processor unit.

[0019]

According to a first aspect of the present invention, there is provided a cache device for managing a cache memory for caching data accessed by a processor, and managing the cache memory in units of memory blocks, and updating data words by the processor. Holds the identification information indicating which data word in the memory block has been updated, and when there is a write-back request for the memory block from the outside, the identification information is added to the memory block and transmitted. A cache management unit; and a communication unit for receiving a write-back instruction from the processor and transmitting a write-back start message to the outside.

Since the cache management means adds the identification information to the memory block and transmits the same, it is possible to externally receive the identification information and integrate the memory blocks. Further, the communication means receives the write-back instruction from the processor and transmits a write-back start message to the outside, so that it is possible to easily know the start of the memory block write-back processing outside.

According to a second aspect of the present invention, there is provided a consistency control apparatus for integrating data of a memory block based on a memory block received from outside and identification information indicating which data word in the memory block has been updated. It includes data integration means and storage means for storing the memory block integrated by the data integration means in the main memory.

Since the data integrating means integrates the data in the memory block based on the memory block and the identification information, each processor can update the contents of another data in the same memory block in the cache.

According to a third aspect of the present invention, there is provided a consistency control device for integrating data received from outside in a memory block, and for storing the memory block integrated by the data integration unit in a main memory. Storage means.

Since the data integration means integrates the data in the received memory block, each processor can update the contents of another data in the same memory block in the cache.

According to a fourth aspect of the present invention, there is provided the consistency control apparatus according to the second or third aspect, wherein the consistency control apparatus further includes an externally-received memory block that has received all updated memory blocks. Detecting means for detecting the

Since the detecting means detects that all the updated memory blocks have arrived from the outside, the data integrating means can easily start data integration.

A consistency control device according to a fifth aspect is the consistency control device according to the fourth aspect,
The consistency control device further includes a communication unit for receiving a memory block write-back start message from outside and transmitting a write-back request to the outside.

The communication means receives the memory block write-back start message from the outside and issues a write-back request to the outside, so that the communication means responds to the write-back start message from the external cache to the plurality of caches. A write-back request can be sent. In addition, even when the connection network itself does not have a broadcast or multicast function, it is possible to broadcast or multicast a write-back request.

A consistency control device according to a sixth aspect is the consistency control device according to the fourth or fifth aspect, wherein the data integration means writes the contents of the memory block received from the outside for each data word. Register means for comparing the contents of the memory block received from the outside with the contents of the memory block held by the register means for each data word, and when the data words are not matched by the comparing means, Mask means for masking the subsequent writing of the data word into the register means.

The mask means masks the subsequent writing of the data word into the register means when the data word is not matched by the comparing means, so that only the contents of the memory block received from the outside are used to mask the data of the memory block. Can be integrated. Therefore, the cache does not need to manage the data update in word units.

According to a seventh aspect of the present invention, there is provided the consistency control apparatus according to the fourth or fifth aspect, wherein the data integration means receives the operation result from the outside and the register means for holding the operation result. Counting means for counting the number of memory blocks; calculating means for calculating an exclusive OR for each bit of the content held in the register means and the content of the memory block received from the outside, and outputting the result as a calculation result; When the counting by the counting means is an even number, a main memory reading means for reading the memory block of the main memory and inputting the read memory block to the calculating means is included.

The arithmetic means obtains an exclusive OR for each bit of the content held in the register means and the content of the memory block received from the outside, and sets the result as an arithmetic result. Since the memory reading means reads the memory block of the main memory and causes the calculating means to perform the calculation, it is possible to accurately integrate the data of the memory block only with the contents of the memory block. Therefore, the cache does not need to manage the data update in word units.

The consistency control device according to claim 8 is the consistency control device according to any one of claims 3 to 7, wherein the consistency control device further includes a copy of the memory block received by the data integration means. Invalidation request means for externally requesting invalidation of the program.

Since the invalidation requesting unit requests the external cache unit to invalidate the copy of the memory block received by the data integration unit, the cache unit can easily recognize that the copy of the memory block is invalid. Can be.

A consistency control device according to claim 9 is the consistency control device according to any one of claims 3 to 8, wherein the consistency control device further updates the memory block received by the data integration means. Update request means for requesting externally.

The update request unit requests the external cache unit to update the memory block received by the data integration unit, so that the cache unit can easily update the memory block. In particular, in the case of the combination with claim 8, it is possible to perform consistency control by appropriately switching between invalidation and update.

According to a tenth aspect of the present invention, the protocol conversion apparatus is processed by transaction processing means for processing a transaction on a snoop bus, connection network interface means for transmitting / receiving a message via a connection network, and transaction processing means. Protocol conversion control means for mutually converting a transaction and a message transmitted and received by the connection network interface means.

The protocol conversion control means converts between the transaction processed by the transaction processing means and the message transmitted / received by the connection network interface means, so that it is connected to the snoop cache connected to the snoop bus and to the connection network. It is possible to transmit and receive the memory block to and from the consistency control device.

According to a eleventh aspect of the present invention, in the protocol conversion apparatus of the tenth aspect, when a write transaction occurs, the snooping is performed until the processing of the write transaction is completed. Take the right to use the bus.

When the write transaction occurs, the transaction processing means occupies the right to use the snoop bus until the processing of the write transaction is completed, so that the processor unit cannot generate a new bus transaction. Therefore,
Even when an existing processor unit having no mechanism for receiving a write-back response is used, the same operation as when the processor unit receives the notification of the completion of the write-back process can be performed.

According to a twelfth aspect of the present invention, there is provided a multiprocessor device comprising: a plurality of processors; a plurality of cache devices connected to each of the plurality of processors; and a consistency control device connected to the plurality of cache devices and the main memory. Wherein each of the plurality of cache devices manages a cache memory for caching data accessed by a connected processor, the cache memory is managed in memory block units, and the When a word is updated, identification information indicating which data word in the memory block has been updated is held, and when there is a write-back request for the memory block, the identification information is added to the memory block and consistency control is performed. Cache management for sending to devices The consistency control device mainly includes a memory integrating unit for integrating data of the memory block based on the memory block and the identification information received from the cache managing unit, and a memory block integrated by the data integrating unit. Storage means for storing in a storage.

Since the consistency control device integrates the data of the memory block based on the memory block and the identification information received from the cache management means, each cache device individually updates another data of the same memory block. Becomes possible.

According to a thirteenth aspect of the present invention, there is provided a multiprocessor device, comprising: a plurality of processors; a plurality of cache devices connected to each of the plurality of processors; and a consistency control connected to the plurality of cache devices via a connection network. A multiprocessor device including a device and a main memory connected to a consistency control device, wherein each of the plurality of cache devices caches data accessed by a connected processor, and a cache memory. Is managed in memory block units,
A cache management unit for transmitting the memory block to the consistency control device when there is a write-back request for the memory block, wherein the consistency control device integrates the data in the memory block received from the cache management unit. And data storage means for storing the memory block integrated by the data integration means in the main memory.

Since the consistency control device integrates the data in the memory blocks received from the cache management means, each cache device can update another data in the same memory block.

A multiprocessor device according to claim 14 is the multiprocessor device according to claim 12 or 13, wherein the multiprocessor device is further provided between the consistency control device and the main memory, and The storage means includes an auxiliary cache device for caching data accessed by the device, and the storage means stores the memory block integrated by the data integration means in the auxiliary cache device.

Since the auxiliary cache device is provided between the consistency control device and the main memory, the consistency control device can access data from the auxiliary cache at high speed, and the processing performance of the multiprocessor device is improved. .

A multiprocessor device according to a fifteenth aspect is the multiprocessor device according to any one of the twelfth to twelfth aspects, wherein the multiprocessor device further monitors a connection network and provides a cache for each memory block. A directory unit for holding a state of the memory block in the device, wherein the data integration unit issues a write-back request only to the cache device updating the content of the memory block based on the content held in the directory unit. The data in the memory block transmitted and received from the cache management unit is integrated.

The data integration means integrates the data in the memory block received from the cache management means based on the contents held in the directory means, so that the integration processing of the data in the memory block is facilitated.

A multiprocessor device according to claim 16 is the multiprocessor device according to claim 15,
The directory means further includes auxiliary cache means for storing memory blocks accessed by the consistency control device, and auxiliary cache control means for caching data accessed by the consistency control device in the auxiliary cache means. .

Since the directory means includes the auxiliary cache means, the consistency control device can access data from the auxiliary cache means at high speed. Further, since the associative memory tags required for both the directory means and the auxiliary cache can be integrated, the circuit scale can be reduced.

A multiprocessor device according to a seventeenth aspect is the multiprocessor device according to any one of the twelfth to twelfth aspects, wherein the cache device further executes a special store instruction by a connected processor. Special store instruction processing means for detecting and transmitting a memory block writeback start message updated by the special store instruction to the consistency control device is included.

The special store instruction processing means detects that the special store instruction is executed by the processor, and sends a write back start message of the memory block updated by this instruction to the consistency control device. It is not necessary to transmit a write-back instruction, and the processing can be speeded up.

[0053] The multiprocessor device according to the eighteenth aspect includes a plurality of processor units, a plurality of protocol converters connected to each of the plurality of processor units, and a controller connected to the plurality of protocol converters and the main memory. A multi-processor device including a latency control device, wherein each of the plurality of processor units includes a processor and a snoop cache connected to the snoop bus, and each of the plurality of protocol conversion devices performs a transaction on the snoop bus. , A network interface for transmitting / receiving a message via a network, and a transaction processed by the transaction processor and a message transmitted / received by the network interface. And a protocol conversion control unit for converting the data into a memory.The consistency control device includes a data integration unit for integrating data of a memory block received from a plurality of protocol conversion devices via a connection network, and a data integration unit. Storage means for storing the integrated memory block in the main memory.

Since the protocol conversion device converts a transaction generated on the snoop bus and a message transmitted and received between the consistency control devices into and out of each other, the protocol conversion device converts the snoop cache connected to the snoop bus and the consistency cache connected to the connection network. It is possible to transmit and receive the memory block to and from the tension control device.

[0055]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below, but these are exemplifications of the present invention, and the present invention is not limited to these embodiments.

[First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a multiprocessor according to a first embodiment of the present invention. The multiprocessor device includes a processor 1a and 1b and a cache 2a for caching data accessed by the processor 1a or 1b.
And 2b, a consistency control unit 5 connected to the caches 2a and 2b via the connection network 4 and controlling to maintain memory consistency, and a main memory 3. Each of the caches 2a and 2b is composed of a write-back cache.

FIG. 2 is a diagram for explaining types of messages used in the multiprocessor device according to the present embodiment shown in FIG. FIG. 3 is a diagram showing information added to the message shown in FIG. The “write-back instruction” is transmitted from the processor 1a or 1b to the cache 2a.
Alternatively, the message is transmitted to 2b, and is a message for instructing the start of the write-back process. The address information of the memory block to be subjected to the write-back process is added to the “write-back instruction”.

The "write-back response" is a message transmitted from the cache 2a or 2b to the processor 1a or 1b, and is a response message to the "write-back instruction". This message is sent when all the write-back processing is completed.

The "write-back start message" is a message transmitted from the cache 2a or 2b to the consistency control unit 5, and is transmitted to the consistency control unit 5 when the cache 2a or 2b receives the "write-back instruction". This is a message for requesting the start of the write-back data integration process. The identifier of the processor that has issued the “write-back instruction” and the address information of the memory block to be subjected to the write-back process are added to the “write-back start message”.

The "write-back completion message" is a message transmitted from the consistency control unit 5 to the cache 2a or 2b, is a response message to the "write-back start message", and completes the integration processing of the write-back data. This is a message transmitted to the cache 2a or 2b when it is done.

The "rewrite request" is a message transmitted from the consistency control unit 5 to the cache 2a or 2b, and is a message for requesting transmission of a memory block updated in the cache 2a or 2b. The address information of the memory block to be subjected to the write-back processing is added to the “write-back request”.

The "write-back data" is a message transmitted from the cache 2a or the cache 2b to the consistency control unit 5, and is a message transmitted in response to the "write-back request". The “write-back data” includes an updated memory block in the cache 2a or 2b and information (update status) indicating which data word in the memory block has been updated.

The "read request" is sent to the cache 2a or 2
b is a message transmitted to the consistency control unit 5 to request reading of a memory block from the main memory 3. The identifier of the processor 1a or 1b that has requested reading and the address information of the memory block to be read are added to the "read request".

The "read data" is a message transmitted from the consistency control unit 5 to the cache 2a or 2b, and is a response message to the "read request". The data of the memory block read from the main memory 3 is added to “read data”.

When the cache 2a or 2b receives a "write-back instruction" from the processor 1a or 1b,
Alternatively, when data replacement is required due to lack of cache capacity or the like, a “write back start message” is transmitted to the consistency control unit 5. When the cache 2a or 2b receives the "write-back instruction" from the processor 1a or 1b, the cache 2a or 2b transmits a "write-back start message" to the consistency control unit 5 even if it does not hold the specified memory block.

When the cache 2a or 2b receives the "write-back request" from the consistency control unit 5, if the cache 2a or 2b holds the updated copy of the memory block by itself, it sends the "write-back data" to the consistency control unit 5. " Further, the cache 2a or 2b does not hold the copy of the memory block by itself, or if the cache block is not updated even if it holds the copy of the memory block, an update status indicating that no word has been updated is added. Return data ”(hereinafter referred to as clean“ write-back data ”)
Is transmitted to the consistency control unit 5. In subsequent processing,
Since the data in the message is not used, an arbitrary value (for example, “0”) can be set. The data in the clean “write back data” message is not used,
Since the consistency control unit 5 detects that all the caches have responded to the "write-back request", it is necessary to transmit a message from the cache.

Although the message transfer method may be a message exchange or circuit exchange method, the multiprocessor in this embodiment does not depend on the message transfer method. Also, as the form of the connection network,
Although a bus or a multistage switch is assumed, the multiprocessor device in the present embodiment does not depend on the form of the connection network. However, if the connection network has a broadcast function, it is possible to substitute a write-back request by broadcasting a write-back start message. In this case, the consistency control unit issues a write-back request. You don't have to.

FIG. 4 is a block diagram showing a schematic configuration of the cache 2a or 2b of the multiprocessor device according to the present embodiment. The cache 2a or 2b includes the processor interface 21 connected to the processor bus 620a or 620b, the cache 2a or 2b.
b, the cache control unit 22 for controlling the entire network 4 via the cache bus 610a or 610b.
And a cache set group (cache memory) 24.

The cache 2a or 2b basically controls by a write-back method. However, the write-back method is a well-known technique, and therefore will not be described in detail here. However, the cache control unit 22
The function of transmitting / receiving a message described with reference to FIGS. 2 and 3 and the function of controlling a cache entry described later are added.

FIG. 5 is a diagram for explaining cache entries in the cache 2a or 2b of the multiprocessor device according to the present embodiment. The cache entry includes the address tag of the memory block, the valid bit (V), the update bits M0 to M3, and the LRU (Least Receive).
ntly Used) fields and data words 0-3. The LRU field is information used at the time of exchanging data, and is a well-known technique, and thus will not be described in detail. Cache entries are grouped by the number of associativities to form a cache set. Furthermore, the cache sets are put together to form a cache set group.

FIG. 6 is a diagram for explaining a state of an entry indicated by a valid bit (V) and update bits M0 to M3 in the cache entry shown in FIG.
When the valid bit V is “0”, the update bits M0 to M3
Is invalid, indicating that the entry is invalid. When the valid bit V is “1”, it indicates that the entry is valid, and each of the update bits M0 to M0
When the value of M3 is "0", it indicates that the content of the data word corresponding to the update bit has not been updated, and when it is "1", it indicates that the corresponding data word has been updated. Therefore, when the valid bit V is “1” and the updates M0 to M3 are all “0”, it indicates that the cache entry is in a clean state. The number of words and the size of words in one memory block are determined by the requirements of the system, and are not limited to the sizes and numbers shown in FIG.

FIG. 7 is a flowchart showing a processing procedure when the cache receives a "write-back instruction" from the processor. When the cache 2a or 2b receives the "write-back instruction", it sends a "write-back start message" to the consistency control unit 5 (S701). The cache 2a or 2b waits for a "write-back request" to be transmitted from the consistency control unit 5 (S702). When the "write-back request" is received, the cache 2a or 2b sends the "write-back data" to the consistency control unit 5. Outgoing. The cache 2a or 2b waits until a "write back completion message" is transmitted from the consistency control unit 5 (S70).
4) The processor 1a or 1b which has transmitted the "write-back instruction" when receiving the "write-back completion message"
A "write back response" is transmitted to the server (S705), and the process ends. Even when the replacement process is performed due to insufficient cache capacity, the same process is performed except that a process start condition and a “write back response” are not transmitted.

FIG. 8 is a flowchart showing a processing procedure when a “write-back request” is received from the consistency control unit 5 in a cache that has not received a “write-back instruction”. When the cache 2a or 2b receives the "write-back request" from the consistency control unit 5, it sends "write-back data" to the consistency control unit 5 (S801).

It should be noted that the cache 2a or 2b
If a "write-back request" for a memory block at another address is received while waiting for the "write-back request" shown in step S702, the process shown in FIG. 7 is temporarily suspended and shown in FIG. The transmission process of the memory block at the different address is performed.

FIG. 9 is a block diagram showing a schematic configuration of the consistency control unit 5 of the multiprocessor device according to the present embodiment. Consistency control unit 5 transmits a message to sequencer 501 for performing overall control of consistency control unit 5, message receiving unit 502 for receiving messages from caches 2a and 2b, and caches 2a and 2b. And a write-back data integration unit 504 for integrating the write-back data received from the caches 2a and 2b and storing them in the main memory 3.

The message receiving unit 502
When the “write-back start message” is received from a or 2b, the sequencer 501 is started. If the message receiving unit 502 receives the “write-back start message” while the sequencer is already performing write-back processing for another memory block, the sequencer 501 ends the ongoing write-back processing. Until the sequencer 501 finishes the ongoing write-back process, the message receiving unit 502 sets the sequencer 5
01 is started.

FIG. 10 is a flowchart showing a processing procedure of the consistency control unit 5 of the multiprocessor device according to the first embodiment. The message receiving unit 502
When a "write-back start message" is received from the cache 2a or 2b, it is determined whether there is a write-back process of another memory block currently in progress (S101). If there is a write-back process in progress (S101, Yes),
The processing is suspended until the ongoing write-back processing ends. If there is no ongoing write-back processing (S10
1, No), the message receiving unit 502
Start 1

In response to an instruction from the sequencer 501, the message sending unit 503 sends a "write back request" to all the caches 2a and 2b (S102).
Wait for "write back data" to be transmitted from a and 2b.

When the sequencer 501 activates the write-back data integration section 504, the write-back data integration section 5
04 performs the integration process of the "write-back data" received from the caches 2a and 2b (S103). This write-back data integration process will be described later.

Further, the write-back data integration unit 504
The integrated write-back data is stored in the main memory 3 via the main memory bus 640 (S104). And sequencer 5
01 activates the message transmission unit 503,
The message sending unit 503 sends a “writeback start message”
Is sent to the cache 2a or 2b that sent the message (S105), and the process ends.

FIG. 11 is a diagram for explaining the processing in step S103 of FIG. Write-back data integration unit 5
04 removes clean “write-back data” from the received “write-back data” group and then writes the write-back data based on the contents of the update bits M0 to M3 and the data words 0 to 3 shown in FIG. Perform integration processing. For example, by referring to the update bits M0 to M3 of the “write-back data” received from the cache 2a, it can be seen that the data words 1 and 3 have been updated.
Also, the “write-back data” received from the cache 2b
Of these, it can be seen that only data word 2 has been updated by referring to update bits M0 to M3. Therefore, the write-back data integration unit 504 sets the cache 2
Data word 1 and data word 3 are extracted from "write-back data" from a, and data word 2 is extracted from "write-back data" received from cache 2b.
By integrating them, the write-back data is integrated. Since data word 0 has not been updated, it may be extracted from either “write-back data”. Alternatively, a method of not writing the word in the main memory is also conceivable.

FIG. 12 is a diagram for explaining combinations that are not possible in the integration process. For example, data word 1 and data word 3 of “write-back data” received from cache 2a have been updated, and data word 2 and data word 3 of “write-back data” received from cache 2b have been updated. Suppose you have In this case, both data words 3 have been updated, and the data word 3 cannot be integrated. However, the weak memory consistency model prohibits different processors from updating the same data word in the same memory block within the process delimited by the synchronization point. Therefore, the combination shown in FIG. 12 cannot occur at all.

Although the size of the memory block shown in FIGS. 11 and 12 is set to 4 words and the integration processing is performed in word units, the present invention is not limited to this. Further, the word size may be any of 8, 16, 32 bits, and the like.

When the cache entries of a certain cache are to be written back to the main memory 3 by the operations of the caches 2a and 2b and the consistency control unit 5 described above, the same applies to the other caches in the multiprocessor device. The cache entry of the memory block is written back at the same time. That is, when a cache entry of a certain cache is written back, all the updates up to that point are reflected in the memory block of the main memory 3.

FIG. 13 is a flowchart showing the processing procedure of the latest data acquisition processing by the processor 1a or 1b. When the processor 1a or 1b acquires the latest data, the processor 1a or 1b first sends a "write-back instruction" corresponding to the memory block from which the latest data is to be acquired to the cache 2a or 2b (S131), and the cache 2a or 2b.
b, after receiving a “writeback response” from
a or 2b is instructed to invalidate the cache entry of the memory block (S132). Through this processing, the processor 1a or 1b can refer to the latest data in the memory block at the time when the circle in FIG.

As described above, in the multiprocessor device according to the present embodiment, when a plurality of data words are included in the same memory block, different processors are included in the same memory block even if false sharing occurs. Data words can be updated independently. Therefore, it is possible to prevent a processing delay due to invalidation of unnecessary data caused by false sharing, and to provide a multiprocessor device capable of performing high-speed processing while guaranteeing memory consistency. became.

Although the present embodiment has been described assuming that the number of processors is two, a multiprocessor device can be constructed in a similar manner when three or more processors are used.

[Second Embodiment] The multiprocessor device according to the second embodiment is different from the multiprocessor device according to the first embodiment shown in FIG. 1 in that functions are added to caches 2a and 2b and consistency. The only difference is that a function is added to the control unit 5. Therefore, detailed description of the same configurations and functions will not be repeated. It is to be noted that the reference numerals of the cache in the second embodiment are 2a 'and 2b', and the reference numeral of the consistency control unit is 5 '.

FIG. 14 and FIG. 15 are diagrams showing the contents of a message newly added in the multiprocessor device according to the second embodiment. The "invalidation request" is transmitted from the consistency control unit 5 'to the cache 2a' or 2
b 'is a message transmitted to the cache 2a'
Alternatively, this is a message for requesting invalidation of the cache entry of the memory block in 2b '. The address information of the memory block to be invalidated is added to the “invalidation request”.

The "invalidation response" is a message transmitted from the cache 2a 'or 2b' to the consistency control unit 5 ', and is a response message to the "invalidation request".

"Update data" is a message transmitted from the consistency control unit 5 'to the cache 2a' or 2b '.
This is a message for requesting an update of the cache entry of the memory block in b '. The “update data” is added with the update data of the memory block and the address information of the memory block to be updated.

The “update response” is stored in the cache 2
This is a message transmitted from a ′ or 2b ′ to the consistency control unit 5 ′, and is a response message to “update data”.

FIG. 16 shows the cache 2a 'or 2b'
FIG. 9 is a flowchart showing a processing procedure when receives a “write-back instruction” from the processor 1a or 1b. When the cache 2a 'or 2b' receives the "write-back instruction", it sends a "write-back start message" to the consistency control unit 5 '(S161). Then, it waits for a "write back request" to be transmitted from the consistency control unit 5 '(S162).

When the cache 2a 'or 2b' receives the "write-back request" from the consistency control unit 5 ', it sends "write-back data" to the consistency control unit 5' (S163). Then, it waits for the consistency control unit 5 'to transmit an "invalidation request" or "update data" (S164).

When the cache 2a 'or 2b' receives an "invalidation request" or "update data" from the consistency control unit 5 ', it performs a corresponding process. That is, when an “invalidation request” is received, the valid bit V (see FIG. 5) of the cache entry of the target memory block is set to “0”, and the cache entry is invalidated. When the "update data" is received, the cache entry of the target memory block is rewritten with the update data received from the consistency control unit 5 '(S165).

Next, the cache 2a 'or 2b' sends an "invalidation response" or "update response" to the consistency control unit 5 '(S166), and the "write back completion message" is sent from the consistency control unit 5'. Is transmitted (S167).

When the cache 2a 'or 2b' receives the "write-back completion message" from the consistency control unit 5 ', it sends a "write-back response" to the processor 1a or 1b (S168), and ends the processing.

FIG. 17 is a flowchart for explaining a processing procedure when the cache 2a 'or 2b' which has not received the "write back instruction" receives the "invalidation request" or "update data". Cache 2
When a 'or 2b' receives the "invalidation request" or "update data", it performs the corresponding processing. That is, when receiving the "invalidation request", the cache 2a 'or 2b' sets the valid bit V (see FIG. 5) of the cache entry of the target memory block to "0", and invalidates the cache entry. .
When the "update data" is received, the cache 2a 'or 2b' rewrites the cache entry of the target memory block with the update data received from the consistency control unit 5 '(S17).
1). Then, an "invalidation response" or "update response" is transmitted to the consistency control unit 5 '(S17).
2), end the process.

FIG. 18 is a block diagram showing a schematic configuration of a consistency control unit 5 'of the multiprocessor device according to the present embodiment. Compared with the consistency control unit 5 in the first embodiment shown in FIG. 9, the message receiving unit 502 'receives an "invalidation response" or an "update response", and the message transmitting unit 503' receives an "invalidation request". "Or" update data ",
And only the control of the sequencer 501 'is different. Therefore, detailed description of the same configurations and functions will not be repeated.

FIG. 19 is a flowchart for explaining a processing procedure when consistency control unit 5 'in the present embodiment receives a "writeback start message". When the message receiving unit 502 'receives the "write-back start message" from the cache 2a' or 2b ', it determines whether or not a write-back process of another memory block currently in progress is being performed (S191). If there is a write-back process in progress (S191, Yes), the process is suspended until the write-back process ends. If there is no write-back process currently in progress (S191, N
o), the message receiving unit 502 'is the sequencer 501'
Is activated, the sequencer 501 'causes the message transmission unit 503' to send all the caches 2a 'and 2a.
A “write back request” is transmitted to b ′ (S192).

Next, the sequencer 501 'activates the write-back data integration unit 504, so that the write-back data integration unit 504 performs the write-back data integration process described with reference to FIG. 11 (S193). The rewritten data is stored in the main memory 3 via the main memory bus 640 (S194). Then, the sequencer 501 'sends all the caches 2a' and 2
b ”is sent an“ invalidation request ”or“ update data ”(S195), and waits for an“ invalidation response ”or“ update response ”to be sent from all caches 2a ′ and 2b ′ (S196).

When the message receiving section 502 'receives an "invalidation response" or an "update response" from all the caches 2a' and 2b ', the sequencer 50
1 'sends a "writeback completion message" to the message sending unit 503' to the cache that sent the "writeback start message" (S197), and ends the processing.

FIG. 20 is a flowchart showing the processing procedure of the latest data acquisition processing by the processor. The processor 1a or 1b has a cache 2a 'or 2
By transmitting a "write-back instruction" of the target memory block to b 'and receiving a "write-back response" from the cache 2a' or 2b '(S201), the process is terminated. By this processing, the processor 1a or 1b
It is possible to refer to the latest data in the memory block at the time when a circle is added in FIG.

If only one of the write-back data obtained as a response to the "write-back request" has been updated, the consistency control unit 5 'transmits the updated write-back data. Cache 2a 'or 2
Since it is clear that b ′ holds the latest data, the number of messages is reduced without sending an “invalidation request” or “update data” to the cache in step S195 of FIG. It is also possible. Similarly, for a cache that has started write-back processing due to replacement of a memory block due to a cache miss, it is clear that a copy of the memory block is discarded upon completion of the write-back processing. 'Can also reduce the number of messages without sending an "invalidation request" or "update data" to the cache.

As described above, in the multiprocessor according to the present embodiment, the memory block in the cache is invalidated or updated during the write-back processing of the consistency control unit 5 '.
When the data in the memory block is accessed by the processor, the processing load on the cache can be reduced.

[Third Embodiment] The multiprocessor device according to the third embodiment has the same configuration as the multiprocessor device according to the first or second embodiment.
However, the function of the write-back data integration unit 504 in the consistency control unit 5 or 5 'is different. Therefore, the reference numeral of the write-back data integration unit will be described as 504 ', and detailed description of other overlapping configurations and functions will not be repeated.

FIG. 21 is a block diagram showing a schematic configuration of write-back data integration section 504 'in the present embodiment. The write-back data integration unit 504 'is a register unit 51 for holding data of four words of write-back data.
0, a mask unit 511 for masking the EN signal of the D flip-flop array in the register unit 510, and a comparing unit 512 for comparing a word output from the register unit 510 with a word of write-back data. The D flip-flop in the register unit 510 takes in input data from D in synchronization with the input timing signal CK when the EN signal is “0”.

The register section 510 stores the data word D
It includes four flip-flop arrays. The comparing unit 512 includes four comparators for comparing the data word output from the register unit 510 with the data word of the write-back data.

FIG. 22 is a diagram for explaining the operation of write-back data integration section 504 'shown in FIG. First,
The contents of the memory block from the main memory 3 are loaded into the register unit 510. As shown in FIG. 22A, the values of the D flip-flops in the mask unit 511 are all reset, and the value of the memory block in the main memory 3 corresponding to the write-back data is loaded into the register unit 510. ing.

When the write-back data is input from the cache to the write-back data integration unit 504 ', the output of the comparator in the comparison unit 512 that has become inconsistent becomes "1". For example, as shown in FIG. 22B, assuming that only the data word 0 does not match, the output of the comparator 515 becomes “1” and the OR circuit 517
Also becomes “1”. When the input timing signal is input, the contents of the write-back data are held in the D flip-flop array in the register unit 510, and the output Q of the D flip-flop 516 in the mask unit 511 becomes “1”. Therefore, when the EN signal of the D flip-flop array 514 becomes “1”, even when an input timing signal is subsequently input to the D flip-flop array 514, the held content is not updated, and the first write-back is performed. The contents of data word 0 of the data will continue to be retained. FIG. 22B shows the contents of the mask unit 511 and the register unit 510 at this time.

Similarly, in FIG. 22C, data word 3 is updated, and as shown in FIG. 22D, data word 1 is updated, and the integration of the write-back data is completed.
As described above, since information indicating which data word in each write-back data has been updated is unnecessary, FIG.
As shown in (1), the contents of the management information section of the cache entry in the cache can be reduced. That is, it is not necessary to indicate which data word is being updated by the update bit, and it is sufficient that the update bit M can indicate that any of the data words is being updated.

Further, it is not necessary to include the update status of each word in the “write-back data”, and it is sufficient to include information on whether or not the entire cache entry has been updated. Therefore, the information added to the message shown in FIG. 4 is changed as shown in FIG.

As described above, according to the multiprocessor device of the present embodiment, the update bit corresponding to each data word in the cache is not required, and the data capacity of the cache can be effectively used. The processing in the write-back data integration unit in the consistency control unit can be easily implemented in hardware.

[Fourth Embodiment] A multiprocessor device according to a fourth embodiment has the same configuration as the multiprocessor device according to the first or second embodiment.
However, only the configuration and function of the write-back data integration unit 504 in the consistency control unit 5 or 5 'are different.
Therefore, detailed description of the same configurations and functions will not be repeated. It is to be noted that the description will be made assuming that the reference numeral of the write-back data integration unit in this embodiment is 504 ″.

FIG. 25 is a block diagram showing a schematic configuration of a write-back data integration section 504 "in the present embodiment. The write-back data integration section 504" has a register for holding the contents of four data words. A selector 510 for selecting and outputting the write-back data and the memory block read from the main memory 3 for each data word
1a to 521d, an operation unit 520 for performing an exclusive OR operation on the data words output from the register unit 510 and the data words output from the selectors 521a to 521d for each bit, and a counting unit including a 1-bit counter 522, and an AND circuit 523.

The register unit 510 and the counting unit 522
At the start of the write-back data integration process, all of them are reset. The main memory timing signal is "0", and the selectors 521a to 521d select and output write-back data. Consistency control unit 5
Or 5 'receives the write-back data, the selector 5'
Write-back data is input to 21a to 521d, and an input timing signal is input to the register unit 510 and the counting unit 522 in synchronization with the input of the write-back data.

FIG. 26 is a diagram for explaining the operation of write-back data integration unit 504 ″ shown in FIG.
As shown in (a), “0” is set in all bits in the register unit 510 as an initial value. When the first write-back data is received from the cache, the selector 5
The write-back data is selected by 21a to 521d, and the write-back data is input to the arithmetic unit 520. For example,
The exclusive OR 522 to which the data word 0 is input performs an exclusive OR operation for each bit of the data word 0 of the write-back data and the data word output by the D flip-flop array 514 in the register unit 510, The result is held in D flip-flop array 514 by the rise of the input timing signal. The calculation result is shown in FIG.

When the second write-back data is received, the same processing as when the first write-back data is received is performed, and the operation result becomes the value shown in FIG. 26 (c). Further, when the third write-back data is received, the same processing is performed, and the operation result becomes the value shown in FIG.

After receiving all the write-back data, the main memory timing signal becomes "1" and the selector 521a
521d select and output the main storage data. However, the output of the counting unit 522 at this time is “1”.
Since the main memory timing signal is also “1”, A
The ND circuit 523 outputs “1”, and the EN signal of each D flip-flop array in the register unit 510 becomes “1”. Therefore, even if the input timing signal rises,
The contents of the register unit 510 are not updated, and the value shown in FIG. 26D is finally the value of the integrated write-back data, which is output from the write-back data integrating unit 504 ″.

FIG. 27 is a diagram for explaining the operation of the write-back data integration unit 504 ″ when the number of write-back data is two. Similar to the processing described with reference to FIG. 26, FIG. a) shows the initial value of the register unit 510,
FIG. 27B shows the operation result of the operation unit 520 when the first write-back data is received, and FIG. 27C shows the operation result of the operation unit 520 when the second write-back data is received. Is shown in

However, after receiving the second write-back data, the output of counter 522 is "0", and even if the main memory timing signal is "1", AND circuit 523 is output.
Outputs "0". Therefore, the main storage data is selected and output by the selectors 521a to 521d, and the data word output from the register unit 510 and the data word of the main storage data are subjected to an exclusive OR operation for each bit by the operation unit 520. The result is determined by the rise of the input timing signal.
Is held. The calculation result at this time is shown in FIG. 27D, and the calculation result is output from the write-back data integration unit 504 ″.

According to the multiprocessor of the present embodiment, the cache entries can be those shown in FIG. 23, similarly to the multiprocessor of the third embodiment. Therefore, each cache can effectively use the capacity of the cache memory, and the write-back data integration unit 504 ″ in the consistency control unit.
Can be realized by simple hardware.

[Embodiment 5] FIG. 28 shows Embodiment 5 of the present invention.
1 is a block diagram illustrating a schematic configuration of a multiprocessor device in FIG. The configuration of the multiprocessor according to the present embodiment is the same as the configuration of the multiprocessor according to the third or fourth embodiment. However, the processors 1a and 1b are provided in the processor units 700a and 700b, the caches 2a and 2b are provided in the protocol converters 702a and 702b, and the processor bus 620 is provided.
a and 620b are snoop buses 703a and 703
b differs only in that each is substituted. Therefore, detailed description of the same components and functions will not be repeated.

Many existing microprocessors integrate not only the processor itself but also a snoop cache on a chip or module. Although this snoop cache does not allow the existence of a plurality of write rights, it is integrated in the same chip or the same module of the processor, and thus is superior in operation speed, power consumption, and cost.

Processor units 700a and 700
b assumes an existing microprocessor with integrated snoop cache, and processors 701a and 701a
01b and snoop caches 704a and 704b
And are respectively integrated. Protocol converter 702
a and 702b are snoop buses 703a and 703b.
3b and the cache bus 61
0a and 610b, respectively. Usually, the processor unit 700a or 7
Snoop cache 704a or 704b integrated in 00b has no update bit per data word, only one update bit per cache entry. Therefore, the consistency control unit 5 must have the write-back data integration unit 504 ′ or 504 ″ as shown in the third or fourth embodiment.

FIG. 29 is a block diagram showing a schematic configuration of protocol conversion units 702a and 702b. The protocol converters 702a and 702b are connected to the snoop bus 7
A transaction processing unit 710 that performs a process corresponding to a transaction generated on the transaction 03a and the transaction 703b;
A protocol conversion control unit 711 for performing overall control of protocol conversion; and a cache bus 610a or 610b.
Network interface 7 connected to network 4 via
12 is included.

In the present embodiment, the processor 70
It is assumed that the write-back instruction 1a or 701b generates a write-back instruction by writing, as data, an address of a memory block to be written to a specific address in an I / O (Input / Output) area.

FIG. 30 shows that a write transaction to this specific address is executed by snoop bus 703a or 703b.
Protocol conversion unit 702a or 7 when it occurs above
FIG. 18 is a flowchart for explaining the processing procedure of FIG. 02b, and shows processing equivalent to FIG.

Protocol converter 702a or 702b
Exchanges messages necessary for the write-back process, and executes a snoop bus 703a or 703b until the write-back process is completed after the write transaction occurs.
Occupy the right to use. Snoop bus 703a or 703b by protocol converter 702a or 702b
Is occupied, the processor unit 700a or 700b cannot generate a new bus transaction. In this way, even when an existing processor unit that does not have a mechanism for receiving a write-back response is used, the same operation as when the processor unit receives a notification of completion of the write-back process can be performed. I have.

When a write transaction occurs, the transaction processing unit 710 acquires the right to use the snoop bus 703a or 703b, and suppresses the occurrence of a new bus transaction (S1001). The protocol conversion control unit 711 sends a “write back start message” including the address of the specified memory block to the consistency control unit 5 via the connection network interface 712 (S1002). Then, the protocol conversion control unit 711 waits for the transmission of the “write-back request” from the consistency control unit 5 (S1003).

Upon receiving the “write-back request” from the consistency control unit 5, the protocol conversion control unit 711 causes the transaction processing unit 710 to generate an inquiry transaction (S1004). The inquiry transaction is a transaction for giving the address of a memory block to the snoop caches 704a and 704b and inquiring information about a corresponding cache entry. Upon receiving the inquiry transaction, snoop caches 704a and 704b return whether or not the cache entry exists, and if there is a cache entry, also return whether or not the cache entry has been updated. Furthermore, snoop caches 704a and 704b also output cache entry data if the cache entry exists and has been updated.

If there is no cache entry in the snoop cache 704a or 704b, or if the cache entry exists but has not been updated, the protocol conversion control unit 711 sends clean "write-back data" to the consistency control unit. Call 5 When a cache entry exists in the snoop cache 704a or 704b and is updated, the protocol conversion control unit 711 transmits “write-back data” including the updated data to the consistency control unit 5. (S1005). Then, the protocol conversion control unit 711 waits for the consistency control unit 5 to transmit an “invalidation request” or “update data” (S1).
006).

When the protocol conversion control unit 711 receives an “invalidation request” or “update data” from the consistency control unit 5, it performs a corresponding process. That is, when the protocol conversion control unit 711 receives the “invalidation request”, the transaction processing unit 7
Numeral 10 gives the address of the memory block to the snoop caches 704a and 704b, and invalidates the corresponding cache entry. When the protocol conversion control unit 711 receives the “update data”, the transaction processing unit 710 gives the address of the memory block and the update data to the snoop caches 704a and 704b to update the corresponding cache entry ( S1007).

Next, the protocol conversion control unit 711 sends an “invalidation response” or an “update response” to the consistency control unit 5 (S1008), and sends a “write back completion message” from the consistency control unit 5. It is waited for (S1009). Protocol conversion control unit 711
Receives the “write-back completion message” from the consistency control unit 5, the transaction processing unit 710 releases the right to use the snoop buses 703a and 703b (S1010), and ends the processing.

FIG. 31 is a flowchart for explaining the processing procedure of protocol conversion units 702a and 702b when a write-back transaction occurs on snoop bus 703a or 703b. The write-back transaction is a transaction generated when the snoop cache 704a or 704b runs out of capacity, and outputs the address of the memory block to be rewritten by the snoop cache 704a or 704b and updated data. It is done by doing.

When the transaction processing unit 710 detects the occurrence of a write-back transaction on the snoop bus 703a or 703b, the protocol conversion control unit 7
11 sends a "writeback start message" to the consistency control unit 5 (S1101). Then, the protocol conversion control unit 711 waits for the transmission of the “write-back request” from the consistency control unit 5 (S1102).

Upon receiving the "write-back request" from the consistency control unit 5, the protocol conversion control unit 711 transmits "write-back data" including the updated data to the consistency control unit 5 (S1103). Then, the protocol conversion control unit 711 controls the consistency control unit 5
Waits for an “invalidation request” or “update data” (S1104).

Upon receiving the “invalidation request” or “update data” from the consistency control unit 5, the protocol conversion control unit 711 sends an “invalidation response” or “update response” to the consistency control unit 5 ( S1106), and waits for the transmission of the “write-back completion message” from the consistency control unit 5 (S110).
7). Since the cache entry targeted for the write-back transaction is discarded, invalidation or update processing is unnecessary. Then, upon receiving the “write-back completion message” from the consistency control unit 5, the protocol conversion control unit 711 ends the processing.

FIG. 32 is a flowchart for explaining the processing procedure of protocol conversion section 702a or 702b when a "write back request" occurs on cache bus 610a or 610b, and is equivalent to the processing of FIG. Is shown.

When the protocol conversion control unit 711 receives a “write-back request” from the consistency control unit 5, it causes the transaction processing unit 710 to generate an inquiry transaction (S1201). The protocol conversion control unit 711 sends clean “write-back data” to the consistency control unit 5 if there is no cache entry corresponding to the “write-back request” or the memory block has not been updated. If the cache entry corresponding to the “write-back request” exists and the memory block has been updated, the protocol conversion control unit 711 sends the “write-back data” including the updated data to the consistency control unit. 5 (S1202), and the process ends.

FIG. 33 shows that the "invalidation request" or "update data" is stored in the cache bus 610a or 610.
protocol conversion unit 702a when the error occurs on
19 is a flowchart for explaining the processing procedure of 702b, and shows processing equivalent to the processing of FIG.

When the protocol conversion control unit 711 receives an “invalidation request” or “update data” from the consistency control unit 5, it performs a corresponding process. That is, when the protocol conversion control unit 711 receives the “invalidation request”, the transaction processing unit 7
Numeral 10 gives the address of the memory block to the snoop cache 704a or 704b, and invalidates the corresponding cache entry. The protocol conversion control unit 7
11 receives the “update data”, the transaction processing unit 710 sends the snoop cache 70
The address of the memory block and the update data are given to 4a or 704b, and the corresponding cache entry is updated (S1301). Then, the protocol conversion control unit 711 sends an “invalidation response” or an “update response” to the consistency control unit 5 (S130).
2), end the process.

As described above, in the multiprocessor device according to the present embodiment, an existing processor unit in which a processor and a snoop cache are integrated is used to exchange a transaction on the snoop bus and a message on the cache bus. Since a protocol conversion unit for replacement is provided, a multiprocessor device excellent in operation speed, power consumption and cost can be constructed.

[Embodiment 6] FIG. 34 shows a sixth embodiment.
1 is a block diagram illustrating a schematic configuration of a multiprocessor device in FIG. Compared with the multiprocessor device according to the first embodiment or the multiprocessor devices according to the second to fourth embodiments shown in FIG. 1, a shared auxiliary cache 7 is provided between the consistency control unit 5 or 5 'and the main memory 3. The only difference is that it was done. Therefore, detailed description of the same configurations and functions will not be repeated.

In the multiprocessor devices according to the first to fourth embodiments, consistency control unit 5 or 5 '
Performs the processing by accessing data in the main memory 3, but the consistency control unit 5 or 5 ′ in the present embodiment accesses the data to the shared auxiliary cache 7. Shared auxiliary cache 7
Accesses the main memory 3 via the shared auxiliary cache bus 660 only when a cache miss occurs.
Generally, the access speed of the shared auxiliary cache 7 is higher than the access speed of the main memory 3, so that the performance of the entire multiprocessor device is improved. In addition, the consistency control unit 5 or 5 ′ of the multiprocessor in the third and fourth embodiments reads the data from the main memory 3 in the integration process of the write-back data, and thus the shared auxiliary cache 7 is added. It is also possible to speed up the integration processing. The shared auxiliary cache 7 may be of a write-back or write-through type, but is preferably a write-back cache in order to reduce the number of times of writing to the main memory 3.

In the relationship between the caches 2a, 2a ', 2b or 2b' and the shared auxiliary cache 7, a method for controlling a memory block stored in the cache so as to be surely stored in the auxiliary cache is also described. A control method in which the stored memory block is not always stored in the shared auxiliary cache 7 can be considered.
Hereinafter, the shared auxiliary cache that uses the former control method is called a complete auxiliary cache, and the shared auxiliary cache that uses the latter control method is called a partial auxiliary cache. In a multiprocessor device employing a complete auxiliary cache, the consistency control unit 5 or 5 'can always obtain data from the shared auxiliary cache 7 in the process of integrating write-back data, so the contents of the main memory 3 are referred to. And the speed of the integration process is increased. Further, in a multiprocessor device employing the partial auxiliary cache, the capacity of the shared auxiliary cache 7 can be made smaller than the total capacity of the cache, so that the circuit size of the shared auxiliary cache 7 can be reduced.

[Seventh Embodiment] FIG.
1 is a block diagram illustrating a schematic configuration of a multiprocessor device in FIG. The difference from the multiprocessor device according to the first embodiment shown in FIG. 1 lies only in that a directory unit 8 is added and the function of the consistency control unit 5 is added. Therefore, detailed description of the same configurations and functions will not be repeated. The description of the consistency control unit in the present embodiment will be made with a reference numeral of 5 ″. The directory unit 8 is provided between the cache 2a or 2b passing through the consistency control unit bus 630 and the consistency control unit 5 ″. By monitoring transmitted and received messages, the state of the memory block in each cache is maintained.

FIG. 36 is a block diagram showing a schematic configuration of a consistency control unit 5 ″ according to the present embodiment.
The consistency control unit 5 ″ of the present embodiment is different from the consistency control unit 5 ′ of the second embodiment shown in FIG. 18 in that the sequencer 501 ″ assigns an address corresponding to a memory block to the directory unit 8. The only difference is that the function of outputting the status of each memory block of the memory block via the directory part output bus 680 is added. Therefore, detailed description of the same configurations and functions will not be repeated.

FIG. 37 is a block diagram showing a schematic configuration of directory section 8 in the present embodiment. Directory section 8 includes a plurality of directory entries 800 and directory control section 803 for performing overall control of directory section 8. Directory control unit 803
Monitors messages passing through the consistency control unit bus 630 via the directory unit input bus 670 (see FIGS. 2, 3, 14, and 15).
The address and state of the memory block held in each of the caches 2a and 2b are stored in the directory entry 8
00 is stored in the address tag 802 and the status display unit A and the status display unit B in the address 00. Then, when the contents of the directory entry are referred to by the consistency control unit 5 ″, the state of the memory block corresponding to the address output 690 is output via the directory unit output bus 680.

FIG. 38 is a diagram for explaining the state of the memory block in the cache corresponding to the contents of state display section A or B. When the content of the status display section is "invalid", it indicates that the cache does not have a copy of the memory block corresponding to the address tag. When the content of the status display section is "clean", it indicates that the cache has a copy of the memory block corresponding to the address tag and the content of the memory block has not been updated. When the content of the status display section is "updated", a copy of the memory block corresponding to the address tag is held in the cache, indicating that the content of the memory block has already been updated. .

FIG. 39 shows that the directory control unit 803 receives the message when the directory control unit 803 receives the message.
FIG. 7 is a diagram for explaining the contents of the status display unit updated by the process. The directory control unit 803 sets an “invalidation request”
Is received, the contents of the status display unit 801a or 801b of the memory block of the cache are referred to, and if the content is “invalid” or “clean”, the content of the status display unit is updated to “invalid”. I do.

When the directory control unit 803 receives the "update data", the directory control unit 803 refers to the status display unit of the directory entry corresponding to the memory block, and if the content of the status display unit corresponding to the cache is "clean". Changes the content of the status display section to "clean".

When directory control section 803 receives the "write-back request", it refers to the status display section in directory entry 800 corresponding to the memory block, and sets the contents of the status display section corresponding to the cache to "invalid". In this case, it is set to “invalid”. When the content of the status display section is “clean” or “updated”, the content of the status display section is updated to “clean”.

When directory control unit 803 determines “read request”
Is received, the status display section in the directory entry 800 corresponding to the memory block is referred to, and when the content of the status display section corresponding to the cache is “invalid”, the content of the status display section is “cleaned”. To ".

When directory control section 803 receives the "write right acquisition message", it refers to the state display section in directory entry 800 corresponding to the memory block, and reads the contents of the state display section corresponding to the cache. Is "clean", the content of the status display section is updated to "updated".

FIGS. 40 and 41 are diagrams for explaining the contents of the “write right acquisition request” and the information to be added. The “write right acquisition request” is sent to the cache 2a or 2
b is a message transmitted to the consistency control unit 5 ″, and the content of the status display unit corresponding to the cache in the directory entry 800 corresponding to the memory block in the directory unit 8 is changed to “updated”. The "write right acquisition request" is added with address information of the memory block to be subjected to the write right acquisition processing.

FIG. 42 is a diagram showing the relationship between the contents of the directory entry 800 in the directory section 8 and the contents of the cache entry in the cache. FIG. 42 (a)
As shown in FIG. 7, when the contents of the directory entry are, there is no corresponding memory block in the cache A, and there is a corresponding memory block in the cache B as shown by ". When the directory entry in the directory section 8 shown in FIG. 42A has the content shown in FIG. 42A, the corresponding memory block exists in the cache A as shown in FIG. Has already been updated. In the cache B, there is a corresponding memory block as shown by "", indicating that the contents have been already updated. Similarly, the contents of to in FIG.
2 (b) and ",", "", respectively.

FIG. 43 is a diagram showing the correspondence between the contents of the status display section and the messages transmitted by the consistency control section 5 ". The consistency control section 5" has the content of the status display section of "invalid". In this case, no message is sent to the cache. When the content of the status display section is "clean", the consistency control section 5 "sends an" invalidation request "or" update data "corresponding to the memory block to the cache.
If the contents of the status display section are "updated", the consistency control section 5 "sends an" invalidation request "or" update data "corresponding to the memory block to the cache after the" writeback request ". I do.

FIG. 44 is a flowchart for explaining the processing procedure of consistency control unit 5 ″ in the present embodiment. Consistency control unit 5 ″ transmits a “write back start message” from cache 2a or 2b. Upon reception, it is determined whether or not there is a write-back process currently in progress (S371). If there is a write-back process in progress (S371, Yes), the process is suspended. If there is no ongoing write-back processing (S371, No), the sequencer 501 ″ is started. The sequencer 501 ″ outputs an address to the directory section 8, and the contents of the directory entry of the memory block corresponding to this address. (Status display section). And the sequencer 501 ″
The message sending unit 503 'is instructed to send a "write-back request" to the cache whose corresponding content of the status display unit is "updated" (S372).

When the write-back data is received by the consistency control unit 5 ″, the sequencer 501 ″ causes the write-back data integration unit 504 to perform the integration processing of the write-back data (S373). The integrated write-back data is stored in the main memory 3 via the main memory bus 640 (S374). Then, the consistency control unit 5 ″ sends a “write-back completion message” to the cache that sent the “write-back start message” (S
(375), and terminate the process.

FIG. 45 is a flowchart for explaining another process when the consistency control unit 5 ″ according to the present embodiment receives a “write-back start message”. Upon receiving the "write-back start message" from the cache 2a or 2b, it is determined whether or not there is a write-back process currently in progress (S381). When there is a write-back process in progress (S3
81, Yes), suspend the processing. If there is no ongoing write-back process (S381, No), the message receiving unit 502 'activates the sequencer 501 ". The sequencer 501" outputs an address to the directory unit 8, and outputs the address to the directory unit 8. The contents (status display section) of directory entry 800 corresponding to this address are received via directory section output bus 680.

The sequencer 501 ″ has a directory section 8
, And instructs the message transmission unit 503 'to transmit a "write-back request" to the cache whose corresponding status display unit is "updated" (S382). Then, the sequencer 501 ″ activates the write-back data integration unit 504, so that the write-back data integration unit 504 integrates the received write-back data (S383), and transfers the integrated write-back data to the main storage bus 6.
The data is stored in the main memory 3 via 40 (S384).

Next, the sequencer 501 ″ refers to the status display section received from the directory section 8, and
An "invalidation request" or "update data" is transmitted to a cache whose corresponding content of the status display section is "clean" (S385). Then, "Invalidation request"
Alternatively, it waits for an “invalidation response” or “update response” to be transmitted from the cache of the destination that has transmitted “update data” (S386), and when all “invalidation response” or “update response” are received. ,
A “write-back completion message” is sent to the cache that sent the “write-back start message” (S38).
7), the process ends.

In the relationship between the cache 2a or 2b and the directory section 8, the cache 2a or 2b
b, so that the entry of the memory block stored in the cache 2a or 2b is not always stored in the directory unit 8. A control method is conceivable. Hereinafter, the directory part that adopts the former control method is called a complete directory,
The directory part that adopts the latter control method is called a partial directory. In a multiprocessor device employing a partial directory, when a directory entry cannot be read, the consistency control unit 5 "sends a" write-back request "," invalidation request ", or" update data "to all caches. And an LRU field for determining which directory entry should be discarded when the directory capacity is insufficient is included in the directory entry.

FIG. 46 is a diagram showing the relationship between the control method of the directory unit 8 and the processing procedure of the consistency control unit 5 ″. When the directory unit 8 is a complete directory,
If the consistency control unit 5 "does not transmit the" invalidation request "and" update request ", the processing is performed according to the flowchart shown in Fig. 44. The consistency control unit 5" performs the "invalidation request" or " When an "update request" is transmitted, processing is performed according to the flowchart shown in FIG.

If the directory section 8 is a partial directory, there is a directory entry corresponding to the directory section 8, and if the consistency control section 5 ″ does not send “invalidation request” and “update request”, The process is performed in accordance with the flowchart shown in Fig. 44. If there is a corresponding directory entry in the directory section 8 and the consistency control section 5 "issues an" invalidation request "or" update request ", the consistency control is performed. The unit 5 ″ performs processing according to the flowchart shown in FIG.

Furthermore, if the directory section 8 is a partial directory, there is no directory corresponding to the directory section 8 and the consistency control section 5 ″ does not send out “invalidation request” and “update request”, The tension control unit 5 ″ performs processing according to the flowchart shown in FIG. Also, the directory section 8
Does not exist and the consistency control unit 5 ″ issues an “invalidation request” or an “update request”, the consistency control unit 5 ″ performs processing according to the flowchart shown in FIG.

As described above, according to the multiprocessor of this embodiment, provision of the directory section 8 prevents unnecessary messages from being transmitted to the cache having no copy of the memory block. Thus, the load on the connection network 4 can be reduced. Further, it is possible to reduce the overhead caused by a cache having no copy of a memory block and searching for a nonexistent address tag by receiving a message. Furthermore, when the write-back data integration unit 504 in the consistency control unit 5 ″ has the circuit configuration shown in FIG. 25, the counting unit 522 counts the number of status display units indicating “updated”. As a result, the same result as described above can be obtained, and the number of counting units 522 can be reduced.

[Eighth Embodiment] FIG. 47 shows an eighth embodiment.
1 is a block diagram illustrating a schematic configuration of a multiprocessor device in FIG. The multiprocessor device according to the present embodiment is different from the multiprocessor device according to the seventh embodiment shown in FIG. 35 in that the directory section 8 is replaced with a directory section / shared auxiliary cache 9, and the directory section / shared auxiliary cache 9 is further provided. 9 only controls the consistency control unit 5 ″ and the main memory 3. Therefore, the detailed description of the overlapping configuration and functions will not be repeated.

FIG. 48 is a block diagram showing a schematic configuration of the directory unit / shared auxiliary cache 9. As shown in FIG. The directory part / shared auxiliary cache 9 is different from the directory part 8 shown in FIG. 37 in that the directory entry 800 is replaced with a directory / cache entry 800 ′ and that a shared auxiliary cache control unit 805 is added. Only differ. Therefore, detailed description of the same configurations and functions will not be repeated. The directory / cache entry 800 ′ includes an address tag 802, a status display A, a status display B, and an auxiliary cache 80.
4 inclusive. If the main directory is controlled as a partial directory, it is necessary to add the LRU field as described above. The address tag 802, the status display section A and the status display section B are the same as those included in the directory section 8 shown in FIG. The auxiliary cache unit 804 is obtained by deleting the address tag and the LRU field from the cache entry shown in FIG.

The consistency control unit 5 ″ is connected to the main memory bus 6
When the data is accessed via 40, the shared auxiliary cache control unit 805 checks the valid bit V in the directory / cache entry 800 'of the corresponding memory block to determine whether or not a cache hit has occurred. When a cache hit occurs, the shared auxiliary cache control unit 805 sends the memory block of the auxiliary cache unit 804 to the consistency control unit 5 ″.
In the case of a cache miss, the memory block is read from the main memory 3 via the shared auxiliary cache bus, and
The memory block is transmitted to the consistency control unit 5 ″.

As described above, according to the multiprocessor of the present embodiment, the directory entry and the cache entry in the shared auxiliary cache can be integrated, and the circuit size can be reduced.

Ninth Embodiment A multiprocessor according to a ninth embodiment has the same configuration as the multiprocessor according to the second embodiment. However, only the function of the cache control unit 22 'in the cache shown in FIG. 4 is different. Therefore, detailed description of the same configurations and functions will not be repeated. It is to be noted that a description will be made assuming that the reference numeral of the cache control unit in the present embodiment is 22 ″.

The cache according to the present embodiment detects a special store instruction executed by processor 1a or 1b. The special store instruction is an instruction that stores data in the cache and also has a function of immediately reflecting the data in the main memory 3.

FIG. 49 is a flow chart for explaining a cache processing procedure according to the present embodiment.
When the processor 1a or 1b executes the special store instruction, the cache detects the special store instruction and determines whether or not the data word has hit the cache (S
421). If the cache is hit (S421,
Yes), proceed to step S424. In the case of a cache miss (S421, No), a "read request" is transmitted to the consistency control unit 5 '(S422), and read data is received via the consistency control unit 5' (S422).
423).

In step S424, the cache control unit 22 ″ updates the cache entry of the memory block including the data word in the cache set group 24 (S424), and the consistency control unit 5 ′ via the connection network interface 23. (S425), and receives a "writeback request" from the consistency control unit 5 '(S42).
6), "write-back data" to the consistency control unit 5 '
Is transmitted (S427). Then, an "invalidation request" is received from the consistency control unit 5 '(S428), the cache entry is invalidated (S429), and a "write-back completion message" is received from the consistency control unit 5' (S430). , And the process ends.

As described above, according to the multiprocessor of this embodiment, when the processor executes the special store instruction, the cache transmits a "write back start message" to consistency control unit 5 '. As a result, the data word that the processor writes to the cache is immediately reflected in the main memory 3, and all other processors can refer to the contents of this memory block.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a multiprocessor device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the contents of a message used in the multiprocessor device according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining information added to a message used in the multiprocessor device according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a schematic configuration of a cache according to the first embodiment of the present invention.

FIG. 5 is a diagram for explaining the contents of a cache entry.

FIG. 6 is a diagram for explaining a state of a cache entry.

FIG. 7 is a flowchart illustrating a processing procedure of a cache that has received a write-back instruction;

FIG. 8 is a flowchart illustrating a processing procedure when a cache that has not received a write-back instruction receives a write-back request.

FIG. 9 is a block diagram illustrating a schematic configuration of a consistency control unit 5 according to the first embodiment of the present invention.

FIG. 10 is a flowchart for explaining a processing procedure of a consistency control unit 5;

FIG. 11 is a diagram for explaining a write-back data integration process.

FIG. 12 is a diagram illustrating a combination of write-back data that cannot occur.

FIG. 13 is a diagram illustrating a processing procedure of a processor according to the first embodiment of the present invention.

FIG. 14 is a diagram for explaining the content of a message added in the multiprocessor device according to the second embodiment of the present invention.

FIG. 15 is a diagram for explaining information added to a message added in the multiprocessor device according to the second embodiment of the present invention.

FIG. 16 is a flowchart illustrating a cache processing procedure according to the second embodiment of the present invention.

FIG. 17 is a flowchart illustrating a cache processing procedure when an invalidation request or an update request is received.

FIG. 18 is a block diagram illustrating a schematic configuration of a consistency control unit 5 ′ according to the second embodiment of the present invention.

FIG. 19 is a flowchart illustrating a processing procedure of a consistency control unit 5 ′.

FIG. 20 is a diagram for describing a processing procedure of a processor according to the second embodiment of the present invention.

FIG. 21 is a block diagram illustrating a schematic configuration of a write-back data integration unit 504 ′ according to Embodiment 3 of the present invention.

FIG. 22 is a diagram for explaining the operation of the write-back data integration unit 504 '.

FIG. 23 is a diagram for describing the contents of a cache entry according to the third embodiment of the present invention.

FIG. 24 is a diagram for explaining a message according to Embodiment 3 of the present invention.

FIG. 25 is a block diagram showing a schematic configuration of a write-back data integration unit 504 ″ according to Embodiment 4 of the present invention.

FIG. 26 is a diagram (part 1) for explaining the operation of the write-back data integration unit 504 ″;

FIG. 27 is a diagram (part 2) for explaining the operation of the write-back data integration unit 504 ″;

FIG. 28 is a block diagram illustrating a schematic configuration of a multiprocessor device according to a fifth embodiment of the present invention.

FIG. 29 is a block diagram illustrating a schematic configuration of a protocol conversion unit.

FIG. 30 is a flowchart illustrating a processing procedure of protocol conversion units 702a and 702b when a write transaction occurs.

FIG. 31 is a flowchart illustrating a processing procedure of protocol conversion units 702a and 702b when a write-back transaction occurs.

FIG. 32 is a flowchart illustrating a processing procedure of protocol conversion units 702a and 702b when a “write back request” occurs.

FIG. 33 is a flowchart illustrating a processing procedure of protocol conversion units 702a and 702b when an “invalidation request” or “update data” occurs.

FIG. 34 is a block diagram illustrating a schematic configuration of a multiprocessor device according to a sixth embodiment of the present invention.

FIG. 35 is a block diagram illustrating a schematic configuration of a multiprocessor device according to a seventh embodiment of the present invention.

FIG. 36 is a block diagram showing a schematic configuration of a consistency control unit 5 ″ according to the seventh embodiment of the present invention.

FIG. 37 is a block diagram showing a schematic configuration of a directory unit 8;

FIG. 38 is a diagram showing the relationship between the contents of the state display section in the directory section 8 and the corresponding cache state.

FIG. 39 is a diagram showing a relationship between messages received by the directory unit 8 and values before and after the change of the status display unit.

FIG. 40 shows the contents of a write right acquisition request.

FIG. 41 is a diagram showing information added to a write right acquisition request.

FIG. 42 is a diagram for explaining a relationship between a directory entry in a directory section and a cache;

FIG. 43 is a diagram showing the relationship between the content of the status display unit and the message transmitted.

FIG. 44 is a flowchart illustrating a processing procedure of a consistency control unit 5 ″ according to the seventh embodiment of the present invention.

FIG. 45 is a flowchart for describing another processing procedure of the consistency control unit 5 ″ according to the seventh embodiment of the present invention.

FIG. 46 is a diagram for explaining a processing procedure determined by a relationship between a complete directory or a partial directory and a consistency control unit not transmitting an invalidation request / update request or a consistency control unit transmitting an invalidation request / update request. It is.

FIG. 47 is a block diagram illustrating a schematic configuration of a multiprocessor device according to an eighth embodiment of the present invention.

FIG. 48 is a block diagram showing a schematic configuration of a directory / shared auxiliary cache 9;

FIG. 49 is a diagram for describing a processing procedure of the cache when the processor executes the special store instruction.

FIG. 50 is a diagram for explaining a conventional cache entry.

[Explanation of symbols]

 1a, 1b, 701a, 701b Processor 2a, 2a ', 2b, 2b' Cache 3 Main memory 4 Connection network 5, 5 ', 5 "Consistency control unit 7 Shared auxiliary cache 8 Directory unit 9 Directory unit / shared auxiliary cache 21 Processor interface 23 Connection network interface 24 Cache set group 501, 501 ', 501 "Sequencer 502, 502' Message receiving unit 503, 503 'Message transmitting unit 504 Write-back data integration unit 510 Register unit 511 Mask unit 512 Comparison unit 520 Operation unit 521a-521d Selectors 700a, 700b Processor Units 702a, 702b Protocol Conversion Units 704a, 704b Snoop Cache 800 Directory Entries 803 Directory System Gobe 805 Shared auxiliary cache control unit

Claims (18)

[Claims] 1. A cache memory for caching data accessed by a processor; and managing the cache memory in units of memory blocks.
When a data word is updated by the processor, the identification information indicating which data word in the memory block has been updated is retained. If there is a write-back request for the memory block from outside, the identification information is stored in the memory block. A cache device comprising: a cache management unit for additionally transmitting a message; and a communication unit for receiving a write-back instruction from the processor and transmitting a write-back start message to the outside. 2. A data integration unit for integrating data of a memory block based on a memory block received from outside and identification information indicating which data word in the memory block has been updated, and the data integration unit And a storage unit for storing the memory block integrated by the main storage in the main storage. 3. Consistency control including data integration means for integrating data in a memory block received from outside, and storage means for storing the memory block integrated by the data integration means in a main memory. apparatus. 4. The consistency control device further comprises:
4. The consistency control device according to claim 2, further comprising a detection unit configured to detect that all updated memory blocks have arrived from outside. 5. The consistency control device further comprises:
5. The consistency control device according to claim 4, further comprising communication means for receiving a memory block write-back start message from outside and transmitting a write-back request to the outside. 6. The data integration means includes: a register for writing the contents of a memory block received from the outside for each data word; and a memory for storing the contents of the memory block received from the outside and the memory block held by the register. Comparing means for comparing the content with each data word, and mask means for masking the subsequent writing of the data word to the register means when the data word is not matched by the comparing means. Claim 4.
Or the consistency control device according to 5. 7. The data integration means includes: a register means for holding a calculation result; a counting means for counting the number of memory blocks received from outside; a content held in the register means; Calculating means for obtaining an exclusive OR for each bit with the contents of the received memory block and outputting the result as the calculation result; and when the counting by the counting means is an even number, the memory block of the main memory is read and the calculation means is read. The consistency control device according to claim 4 or 5, further comprising a main storage reading means for inputting the data to the memory. 8. The consistency control device further includes:
The consistency control device according to any one of claims 3 to 7, further comprising invalidation requesting means for externally requesting invalidation of a copy of the memory block received by the data integration means. 9. The consistency control device further includes:
The consistency control device according to any one of claims 3 to 8, further comprising an update request unit for requesting an external device to update the memory block received by the data integration unit. 10. A transaction processing means for processing a transaction on a snoop bus, a connection network interface means for transmitting and receiving a message via a connection network, and a connection between the transaction processed by the transaction processing means and the connection. A protocol conversion control means for mutually converting a message transmitted and received by the network interface means. 11. The transaction processing means, when a transaction instructing a write-back of a memory block occurs, occupies the right to use the snoop bus until the processing of the transaction ends.
The described protocol converter. 12. A multiprocessor device comprising: a plurality of processors; a plurality of cache devices connected to each of the plurality of processors; and a consistency control device connected to the plurality of cache devices and main storage. Wherein each of the plurality of cache devices manages a cache memory for caching data accessed by a connected processor, and the cache memory in units of memory blocks;
When a data word is updated by the connected processor, the identification information indicating which data word in the memory block has been updated is held. When there is a write-back request for the memory block, the identification information is stored in the memory block. And a cache management means for transmitting the data to the consistency control device, and the consistency control device transmits the data of the memory block based on the memory block and the identification information received from the cache management means. A multiprocessor device, comprising: data integration means for integration; and storage means for storing a memory block integrated by the data integration means in a main storage. 13. A plurality of processors, a plurality of cache devices connected to each of the plurality of processors, a consistency control device connected to the plurality of cache devices via a connection network, and the consistency control A multiprocessor device including a main memory connected to a device, wherein each of the plurality of cache devices is a cache memory for caching data accessed by a connected processor, and a memory block that stores the cache memory. Manage in units,
A cache management unit for transmitting the memory block to the consistency control device when there is a memory block write-back request, wherein the consistency control device transmits the data in the memory block received from the cache management unit. And a storage unit for storing the memory block integrated by the data integration unit in the main storage. 14. The multiprocessor device further comprises:
An auxiliary cache device provided between the consistency control device and a main memory for caching data accessed by the consistency control device, wherein the storage unit is a memory integrated by the data integration unit 14. The multiprocessor device according to claim 12, wherein a block is stored in the auxiliary cache device. 15. The multiprocessor device further comprises:
A directory unit for monitoring the connection network and holding a state of the memory block in each cache device for each memory block, wherein the data integration unit is configured to perform a process based on the content held in the directory unit; Send a write-back request only to the cache device that is updating the contents of the memory block,
15. The multiprocessor device according to claim 12, wherein data in a memory block received from said cache management unit is integrated. 16. The directory means further includes an auxiliary cache means for storing a memory block integrated by the data integration means, and a cache for data accessed by the consistency control device in the auxiliary cache means. 16. The multiprocessor device according to claim 15, further comprising: an auxiliary cache control unit. 17. The cache controller further detects that a special store instruction is executed by the connected processor, and sends a memory block write-back start message updated by the special store instruction to the consistency control device. 17. The multiprocessor device according to claim 12, further comprising a special store instruction processing means for transmitting the special store instruction. 18. A multi-processor comprising: a plurality of processor units; a plurality of protocol conversion devices connected to each of the plurality of processor units; and a consistency control device connected to the plurality of protocol conversion devices and main storage. A processor device, wherein each of the plurality of processor units includes a processor and a snoop cache connected to a snoop bus, and each of the plurality of protocol conversion devices processes a transaction on the snoop bus. Transaction processing means, a connection network interface means for transmitting / receiving a message via a connection network, and mutually changing a transaction processed by the transaction processing means and a message transmitted / received by the connection network interface means. A data conversion unit for integrating data of a memory block received from the plurality of protocol conversion devices via the connection network, and the data integration unit. Storage means for storing the memory block integrated by the means in the main memory.