JPH1131398A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the degree of freedom of a circuit design by serially transmitting state information of short circuits/open circuits of arbitrarily set conduction state selection elements to a circuit operation changing circuit part changing circuit operations on the basis of state information to enable formation areas of the conduction state selection elements and the circuit operation changing circuit part to be arranged at arbitrary positions being in the integrated circuit device by being separated. SOLUTION: A first shift register 41 stores state information of short circuits/ open circuits of the conduction state selection elements in flip-flops 41a-41n by cutting fuses 16a-16n constituting the conduction state selection elements with a laser device or the like corresponding to the address of a normal word line in which a bit failure is caused. In a reset, the register 41 serially transmits the state information of the conduction state selection elements to flip-flops 51a-51n of a relief word line address decoding circuit 50. Then, a decode address setting circuit 52 determines the address of a word line which is failed, based on the information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective when applied to a redundancy repair circuit of a semiconductor memory.

[0002]

As described in BACKGROUND ART following literature (a), generally, a dynamic random access memory (DRAM; D ynamic R andom A cces
The s M emory) semiconductor memories such as a wafer manufacturing when the bit line failure and a word line failure occurs in the memory cell array, and for the bit failure, may be provided in advance spare redundant bit lines and redundant word lines, a failure portion To improve the production yield.

(A) Super LSI memory Kiyoo Ito Baifukan Chapter 2.8 Defect relief circuits P181 to P183 FIG. 9 shows a decoder control method using an inactive pulse described in the above document (A). FIG. 3 is a circuit diagram illustrating a redundancy repair circuit.

Referring to FIG. 9, if a memory cell 10 in normal memory cell array 5 has failed and normal word line W
The operation in the case where La is replaced with a redundant word line RWLa to perform repair will be described.

The redundant word line RWLa is controlled by a redundant word line decoder circuit 2. Redundant word line decoder circuit 2
A fuse 16 for setting a decode address freely is provided therein. The fuse 16 is cut by a laser device or the like in accordance with the failure address, so that the address matches the address of the normal word line WLa in which a bit failure has occurred. In order to prevent the failed normal word line WLa from being activated, the normal word line decoder circuit 4
A passivation transistor (n-type MOS transistor) 20 is provided therein.

FIG. 10 is a diagram showing a timing chart at the time of redundancy word line relief in the redundancy relief circuit shown in FIG.

FIG. 10 shows a case where an address signal of a failed word line is selected at a timing 30. An address signal input from the outside is input to both address terminals of the redundant word line decoder circuit 2 and the normal word line decoder circuit 4 via the internal address bus 1.

The redundant word line decoder circuit 2 has a fuse 1
6, the same address as that of the normal word line WLa is set, and the decoder output 17 of the redundant word line is supplied to the inactivation control transistor (n-type MOS transistor) 11 by the decoder drive pulse applied to the terminal RP at the timing 32. And the inactivation signal Φda goes high (hereinafter simply referred to as H level). Therefore,
The decoder output 23 of the normal word line goes low at the timing 33 when the inactivation transistor 20 is turned on (hereinafter, simply referred to as L level).

After the outputs of both the normal and redundant decoders are determined, a word line drive pulse is applied to the terminal RX at a timing 34. As a result, the normal word line driver (n-type M
OS transistor) 19 is not turned on, and normal word line WL
“a” remains at the L level as at timing 35. On the other hand, a redundant word line driver (n-type MOS transistor)
18 turns on, and the redundant word line RWLa goes to the H level as at timing 36. Thus, the normal word line WLa is replaced with the redundant word line RWLa.

As a result, the redundant relief memory cell array 3
Normal memory cells 10 can be operated via the read / write circuit 6 connected to the data line 9.
When the redundancy repair is not performed, the inactivation signal Φda output from the redundant word line decoder circuit 2 becomes L level, the redundant word line driver 18 is not turned on, and the operation of the normal word line decoder circuit 4 is not performed. Not suppressed.

[0011]

However, in the redundancy relieving circuit shown in FIG. 9, the fuse 16 for the redundant word line decoder must be arranged in the redundant word line decoder circuit 2, which restricts the layout. . This is a great limitation in the floor plan and impairs the degree of freedom in circuit design.

If only the fuse 16 is to be arranged outside the redundant word line decoder circuit 2, a wiring area twice as large as the address signal to be decoded is required, and the chip size becomes large. As a result, the feature of the semiconductor memory that the chip size can be reduced with a large memory capacity is lost, which is not desirable.

Further, the redundant word line decoder circuit 2 needs to be arranged adjacent to the normal word line decoder circuit 4 due to limitations on the operation speed and the like. Therefore, the degree of freedom in arrangement of the redundant word line decoder circuit 2 itself is small.

Further, the fuse 16 needs to be arranged independently of a normal transistor region in order to perform cutting by a laser device in a manufacturing process. For this reason, a normal transistor area is restricted, and as a result, it may be a factor to increase the chip size.

Further, when the fuse regions are discrete in the chip, the time required for fuse cutting by the laser device increases, which may cause a reduction in production throughput.

As described above, there are a plurality of conduction state selection elements (for example, the fuse 16 shown in FIG. 9) in which the short-circuit or open state of the element itself can be arbitrarily set. In a semiconductor integrated circuit device having a circuit part whose circuit function or circuit operation is changed based on a short circuit or an open state, a plurality of conduction state selection elements must be arranged in the circuit part, so that layout restrictions are imposed. And the degree of freedom in circuit design is impaired.

Further, the plurality of conduction state selecting elements need to be arranged independently of a normal transistor region, for example, in order to perform cutting by a laser device in a manufacturing process. For this reason, the normal transistor area is limited, which results in an increase in the size of the semiconductor integrated circuit device (chip size). Further, the formation regions of the plurality of conduction state selection elements are discrete in the semiconductor integrated circuit device. In this case, there is a problem that the time required for short-circuiting or opening of the plurality of conduction state selection elements increases, which causes a decrease in productivity.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to set a short circuit or open state of an element itself in a semiconductor integrated circuit device. The conduction state selection element can be arranged at any position in the semiconductor integrated circuit device,
It is an object of the present invention to provide a technique capable of improving the degree of freedom in circuit design.

Another object of the present invention is to provide a semiconductor integrated circuit device in which a conduction state selecting element whose element itself can be arbitrarily set to a short circuit or an open state is concentrated at a specific position in the semiconductor integrated circuit device. It is an object of the present invention to provide a technology that can improve the productivity by enabling the arrangement.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0021]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A plurality of conduction state selection elements whose short-circuit or open state of the element itself can be set arbitrarily are provided, and a circuit function or circuit operation is changed based on the short-circuit state or the open state of the plurality of conduction state selection elements. In a semiconductor integrated circuit device having a circuit unit, a first shift register circuit including a plurality of flip-flops each storing state information indicating a short-circuit state or an open state of the plurality of conductive state selection elements; By the transfer operation,
The second shift register including a plurality of flip-flops each storing the state information of the plurality of conduction state selection elements stored in the first shift register circuit, and the second shift register circuit. Circuit operation changing means for changing a circuit function or a circuit operation based on the stored state information of the plurality of conduction state selection elements, and a serial transfer operation between the first shift register circuit and the second shift register circuit Control means for controlling the
A region where the plurality of conduction state selection elements are formed and a region where circuit elements other than the plurality of conduction state selection elements are formed are separated.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to a semiconductor memory (D).
An embodiment applied to a redundancy relief circuit (RAM) will be described in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[First Embodiment] FIG. 1 is a circuit diagram showing a redundancy repair circuit of a semiconductor memory (DRAM) according to an embodiment of the present invention.

In the figure, the same parts as those of the redundancy repair circuit shown in FIG. 9 are denoted by the same reference numerals as in FIG.
The description of that part is omitted.

The redundancy repair circuit of this embodiment is, for example,
Fuse information indicating address information of a repair word line such as a failed word line (information indicating a short or open state of a plurality of conductive state selection elements of the present invention) is stored.
And the first shift register 4
1, a relief word line address decode circuit 50 to which a serial output FD is input, a stop signal ST for serial transfer control (hereinafter referred to as ST signal), and a clock signal CLK (hereinafter referred to as CLK signal). Is input to a NOR circuit 49.

The first shift register 41 includes a flip-flop (FF1) (41a to 41n) and a fuse (1
6a to 16n), and the Q output is fixed at the H level,
A flip-flop (FF1) 44 for the first bit of the transfer, which outputs H-level flag information when the serial transfer is completed.

Relief word line address decode circuit 50
Are flip-flops (FF2) (51a to 51n, 5
4) and a decode address setting circuit 52. Flip-flop (FF
2) The ST signal is output from 54.

The fuses (16a to 16n) constitute a conduction state selecting element according to the present invention in which the short-circuit or open state of the element itself can be arbitrarily set.

FIG. 2 is a circuit diagram showing a circuit configuration of decode address setting circuit 52 shown in FIG.

As shown in FIG. 3, the decode address setting circuit 52 supplies address signals (Ai, / Ai, Aj, / A
j; / represents an inverted signal. ) Is input to a gate electrode (hereinafter, simply referred to as a gate) of an n-type MOS transistor (hereinafter, referred to as an NMOS) (54a to 54).
n) and flip-flops (FF2) (51a-51)
n) NMOSs (53a-53) whose Q output is input to the gate
53n).

FIG. 3 is a diagram showing a timing chart of the redundancy repair circuit of the present embodiment.

The operation of the redundancy repair circuit according to the present embodiment will be described below.

A reset signal RST (hereinafter, referred to as an RST signal) is a signal which becomes H level for a certain period at power-on. The CLK signal is a clock signal from an oscillator that starts a clock operation using the RST signal as a trigger, for example, a clock signal from a ring oscillator used for self-refresh.

The serial transfer clock signal SCK (hereinafter, referred to as SCK signal) is an output signal from the NOR circuit 49, and is a signal obtained by taking NOR logic of the ST signal and the CLK signal.

When the RST signal is output at power-on, the Q outputs of the flip-flops (FF2) (51a to 51n, 54) in the relief word line address decode circuit 50 are all reset to L level. At the same time, the flip-flops (FF1) (41a to 41n) in the first shift register 41 that store the fuse information have the fuse information (short or open of the fuse 16) of the connected fuse (16a to 16n). (Information indicating a state) are simultaneously latched.

After the logics of all the flip-flops are determined, the CLK signal which has been fixed at the H level starts the clock operation.

The ST signal input to the NOR circuit 49 is
The flag (H level) information from the transfer head bit flip-flop (FF1) 44 is maintained at L level until it reaches the last flip-flop 54 of the shift register 51.

Therefore, the SCK signal becomes an inverted signal of the CLK signal, and this SCK signal is input to each shift register. Each shift register continues the operation of shifting the latch data in synchronization with the rising edge of the SCK signal. This shift operation is performed by flip-flop (FF1) 4
The flag (H level) information from No. 4 passes through all the shift registers 51 in the relief word line address decode circuit 50, and is repeated until it is latched by the flip-flop 54 at the last stage.

As a result, the flip-flops (41a to 41a-4)
The fuse information latched in 1n) is entirely taken into the flip-flops (51a to 51n). Based on the fuse information, predetermined NMOSs (53a to 53n) in the decode address setting circuit 52 are turned on, and the address of the word line in which the decode address setting circuit 52 has a failure is determined.

The operation after the determination of the decoder output 17 of the redundant word line is the same as that of FIG. 9, so that the detailed description is omitted here. As a result, the normal word line WLa and the redundant word line RWLa are replaced, and a normal memory operation can be performed.

FIG. 4 shows the flip-flop (F) shown in FIG.
FIG. 2 is a circuit diagram illustrating a circuit configuration of F1) and a diagram illustrating a truth table thereof.

In the figure, PM1 to PM4 are PMO
S, NM1 to NM5 are NMOS, INV1 to INV6 are inverters, TG1 and TG2 are transfer gates, N
AND1 is a NAND circuit, and NOR1 is a NOR circuit. C is a clock terminal to which the SCK signal is input,
R is a reset terminal to which an RST signal is input, D is a latch data input terminal to which latch data (serial output FD) is input, Q is a latch data output terminal to which latch data (serial output FD) is output, and F is a fuse. An initial data terminal 16 is connected.

Next, the flip-flop (FF) shown in FIG.
The operation of 1) will be briefly described.

First, an H-level RS is applied to the reset terminal R.
When the T signal is input, the NMOS (NM5) turns on, and the inverter (INV4) and the inverter (INV5)
And the initial data terminal F
Is latched.

For example, when the fuse 16 is not connected to the initial data terminal F, the inverter (IN
The output of V4) goes low, the output of the inverter (INV6) goes high, and the transfer gate (TG1) turns on. Here, the NAND circuit (NAND1) has the L-level R inverted by the inverter (INV2).
Since the ST signal is input, the NAND circuit (NAND)
The output of 1) becomes H level.

As a result, the NMOS (NM3) is turned on, and the SCK signal input to the clock terminal C is at the L level.
(NM4) is turned on, the node to which the input terminal of the inverter (INV3) is connected becomes L level, and the inverter (INV3) outputs H level.

On the other hand, when the fuse 16 is connected to the initial data terminal F, the inverter (INV
The output of 4) becomes H level, the output of the inverter (INV6) becomes L level, and the transfer gate (TG2) is turned on. Here, since the RST signal at the H level is input to the NOR circuit (NOR1), the NOR circuit (NO
The output of R1) becomes L level.

As a result, the PMOS (PM3) is turned on, and the SCK signal input to the clock terminal C is at L level.
(NM4) is turned on, the node to which the input terminal of the inverter (INV3) is connected becomes H level, and the inverter (INV3) outputs L level.

Even if the RST signal falls to the L level,
The above state is maintained by the latch circuit composed of the inverter (INV4) and the inverter (INV5).

Next, when the CLK signal starts the clock operation, the SCK signal also starts the clock operation. When the SCK signal input to the clock terminal C goes high,
The MOS (PM2) and the NMOS (NM2) are turned on, and the node to which the input terminal of the inverter (INV3) is connected to the L level according to the H level or the L level of the latch data input to the latch data input terminal D. Level or H level, and the inverter (INV3)
Outputs the H level or the L level of the latch data input to the latch data input terminal D. That is, the latch data is synchronized with the SCK signal and the shift register 4
1 is transferred.

During the period of this transfer operation, the SCK signal becomes L
Level, the NAND circuit (NAND1) and the transfer gate (TG1) (or the NOR circuit (NO
R1) and the transfer gate (TG2))
The PMOS (PM3) or NMOS (NM3) is turned on, and the voltage level of the node to which the input terminal of the inverter (INV3) is connected is maintained at H level or L level.

FIG. 5 shows the flip-flop (F) shown in FIG.
FIG. 2 is a circuit diagram illustrating a circuit configuration of F2) and a diagram illustrating a truth table thereof.

In the figure, PM11 to PM14 are PM
OS, NM11 to NM14 are NMOS, INV11 to I
NV12 is an inverter, and NOR11 is a NOR circuit.

Next, the flip-flop (FF) shown in FIG.
The operation 2) will be briefly described.

First, an H level RS is applied to the reset terminal R.
When the T signal is input, the output of the NOR circuit (NOR11) becomes L level, and the PMOS (PM13) turns on. The SCK signal input to the clock terminal C is L
Level, and the PMOS (PM14) and NMOS (NM
14) is turned on, the inverter (INV12)
Is connected to the H level, and the inverter (INV12) outputs the L level.

Even if the RST signal falls to the L level,
Since the H level is input to one terminal of the NOR circuit (NOR11), the L level is output from the NOR circuit (NOR11).
The level is output.

Next, when the CLK signal starts the clock operation, the SCK signal also starts the clock operation. When the SCK signal input to the clock terminal C goes high,
The MOS (PM12) and the NMOS (NM12) are turned on, and the node to which the input terminal of the inverter (INV12) is connected to the L level according to the H level or the L level of the latch data input to the latch data input terminal D. Level or H level, and the inverter (INV1
The H level or the L level of the latch data input to the latch data input terminal D from 2) is output. That is, the latch data is transferred in the shift register 51 in synchronization with the SCK signal.

During the period of this transfer operation, the SCK signal becomes L
Level, the NOR circuit (NOR11) sets the PM
The OS (PM13) or the NMOS (NM13) is turned on, and the voltage level of the node to which the input terminal of the inverter (INV13) is connected is maintained at the H level or the L level.

FIG. 6 shows a conventional semiconductor memory (DRAM).
FIG. 3 is a diagram showing an example of a chip layout.

In the figure, reference numerals 101A to 101D denote memory cell arrays, and each memory cell array (101
A-101D) are provided with a normal memory cell array 5 and a redundant relief memory cell array 3.

Reference numerals 102A to 102D denote regions where data line decoding circuits (not shown) are provided.
103A to 103D are areas where the normal word line decode circuit 4 and the redundant word line decode circuit 2 are provided.

Reference numeral 104 denotes a region where peripheral circuits and external terminals (bonding pads) 105 are provided. The peripheral circuits provided in this region 104 include a read / write circuit 6, a main amplifier circuit, and an input / output buffer circuit. And a clock generation circuit such as a power supply circuit, an address buffer circuit, and a ring oscillator.
(Note that the main amplifier circuit, input / output buffer circuit,
Clock generator circuits such as a power supply circuit, an address buffer circuit, and a ring oscillator are not shown.) In the region 104, each peripheral circuit is connected to an external terminal 10
5 is provided in an area other than the area in which 5 is provided. Therefore, in the conventional semiconductor memory, the area near the external terminal 105 is an invalid area.

However, according to the redundancy repair circuit of the present embodiment, the fuses (16a to 16n) can be freely arranged in the semiconductor chip. Fuse (16
a to 16n) can be reduced in the vicinity of the external terminal (105 shown in FIG. 6) in a portion which was conventionally an invalid area, thereby reducing the chip size.

The fuse (16a to 16n) information is
Redundant word line decoding circuit 50 by serial transfer method
, The signal line for transmitting the fuse (16a to 16n) information may be one, and the fuse (16a to 16n)
It is possible to minimize the increase in the signal wiring area due to the separation of n) from the redundant word line decoding circuit 50.

As a result, according to the present embodiment, it is possible to avoid the restriction in the floor plan of the fuses (16a to 16n) for redundancy relief, and it is possible to improve the degree of freedom in circuit design. . Furthermore, fuses (16a-
16n) to a specific region, for example, an external terminal (1 shown in FIG. 6)
05) By arranging them intensively in the vicinity, it is possible to improve the productivity.

[Second Embodiment] FIG. 7 is a circuit diagram showing a redundancy repair circuit of a semiconductor memory (DRAM) according to another embodiment of the present invention.

In the figure, the description of the same parts as those of the redundancy repair circuit of the embodiment shown in FIG. 1 will be omitted.

The redundancy repair circuit of this embodiment is the same as the redundancy repair circuit of the line spare decoder system with fuse described in the above document (a), except that the fuse section is replaced with a flip-flop, and the fuse information is serialized by a shift register. This is an embodiment to which transfer is applied.

The redundancy rescue circuit of this embodiment includes a shift register 70 storing fuse information for controlling connection or disconnection of a word line, in addition to the rescue address information of a word line, and a serial register from the shift register 70. An output FD is input, a redundant word line decoding circuit 73 including a flip-flop (FF3) 55 for controlling connection or disconnection of the redundant word line RWLa, and an output from the flip-flop (FF3) 55 is input, and a normal word line is input. W
Normal word line decoder circuit 76 including flip-flop (FF3) 56 for controlling connection / disconnection of La
, A flip-flop (FF2) 54 to which an output from the flip-flop (FF3) 56 is input, an output (ST signal) from the flip-flop (FF2) 54, and CL
It comprises a NOR circuit 49 to which the K signal is input.

The basic operation of the redundancy repair circuit of the present embodiment is the same as that of the above-described embodiment. However, in the redundancy repair circuit of the present embodiment, in addition to the redundancy address information of the word line, the redundancy word line Fuse (16o, 16o, 16) for controlling connection or disconnection of RWLa and normal word line WLa.
The 16p) fuse information is taken into the flip-flops (FF3) (55, 56) by serial transfer.

In this embodiment, in the case of the redundancy repair,
When the serial transfer of the fuse information is completed, the flip-flop (FF3) 55 in the redundant word line decode circuit 73
Is at H level and the redundant word line RWLa is in a selected state. On the other hand, the flip-flop (FF3) 56 in the normal word line decoder circuit 76 becomes L level, and the normal word line WLa is in a non-selected state. Therefore, a normal memory operation can be performed as in the above-described embodiment.

FIG. 8 shows the flip-flop (F) shown in FIG.
3 is a circuit diagram showing a circuit configuration of F3) and a truth table thereof.

In the figure, PM21 to PM24 are PM
OS, NM21 to NM24 are NMOS, INV21 to INV21
NV22 is an inverter, NOR21 is a NOR circuit, AN
D21 is an AND circuit. I is a data terminal I to which a word line driving pulse is input, and O is a data output terminal to which a word line driving pulse is output.

Next, the flip-flop (FF) shown in FIG.
3) will be briefly described.

The operation of transferring the latch data in the flip-flop (FF3) shown in FIG. 8 is the same as that of the flip-flop (FF2) shown in FIG.

However, when the flip-flop (FF3) 55 in the redundant word line decoding circuit 73 becomes H level at the time of completion of the serial transfer of the fuse information, the word line driving pulse applied to the terminal RX becomes the AND circuit (A
ND21) to the redundant word line RWLa.
When the serial transfer of the fuse information is completed, the flip-flop (FF) in the normal word line decoder circuit 76 is set.
3) When 56 becomes L level, the AND circuit (AND2
The output of 1) becomes L level, and the word line drive pulse applied to the terminal RX is not output to the normal word line WLa.

In each of the above embodiments, the fuse 1
Although the case of using No. 6 has been described, the present invention is not limited to this, and a semiconductor element such as a diode can be used.

In each of the above embodiments, the case where the present invention is applied to a word line decoder circuit has been described. However, the present invention is not limited to this, and can be applied to a bit line decoder circuit. .

In each of the above-described embodiments, the present invention
Although the case where the present invention is applied to a RAM has been described, the present invention is not limited to this, and it goes without saying that the present invention is applicable to all semiconductor memories including a redundancy repair circuit such as an SRAM.

Further, the present invention provides a circuit for adjusting the timing by cutting the fuse with a laser device or the like (for example, adjusting the operation timing margin of a delay circuit), or a circuit for adjusting the threshold voltage. It is also applicable.

Although the present invention has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and various modifications may be made without departing from the gist of the present invention. It goes without saying that you get it.

[0084]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there are provided a plurality of conductive state selecting elements whose short-circuit or open state of the element itself can be arbitrarily set, and based on the short-circuited or open state of the plurality of conductive state selecting elements. In a semiconductor integrated circuit device provided with a circuit part whose circuit function or circuit operation is changed, it is possible to freely arrange a plurality of conduction state selecting elements at arbitrary positions in the semiconductor integrated circuit device.

(2) According to the present invention, it is possible to arrange a plurality of conduction state selecting elements completely independently of a normal transistor area, for example, in a portion such as the vicinity of a bonding pad, which was a conventionally invalid area. Therefore, the chip size of the semiconductor integrated circuit device can be reduced.

(3) According to the present invention, productivity can be improved by arranging a plurality of conduction state selecting elements intensively in a specific region.

[Brief description of the drawings]

FIG. 1 shows a semiconductor memory (D) according to an embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating a redundancy relief circuit of a (RAM).

FIG. 2 is a circuit diagram showing a circuit configuration of a decode address setting circuit shown in FIG. 1;

FIG. 3 is a diagram showing a timing chart of the redundancy repair circuit according to the first embodiment;

4 is a circuit diagram illustrating a circuit configuration of a flip-flop (FF1) illustrated in FIG. 1 and a diagram illustrating a truth table thereof.

FIG. 5 is a circuit diagram showing a circuit configuration of a flip-flop (FF2) shown in FIG. 1 and a diagram showing a truth table thereof.

FIG. 6 is a diagram showing an example of a chip layout of a conventional semiconductor memory (DRAM).

FIG. 7 is a circuit diagram showing a redundancy repair circuit of a semiconductor memory (DRAM) according to another embodiment of the present invention.

8 is a circuit diagram showing a circuit configuration of a flip-flop (FF3) shown in FIG. 7 and a truth table thereof.

FIG. 9 is a circuit diagram showing a conventional redundancy repair circuit using a decoder control method using an inactive pulse.

10 is a diagram showing a timing chart at the time of redundancy word line relief in the redundancy relief circuit shown in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Internal address bus, 2, 50, 73 ... Redundant word line decode circuit, 3 ... Redundant relief memory cell array, 4,
76: normal word line decode circuit, 5: normal memory cell array, 6: read / write circuit, 9: data line, 1
0: memory cell, 11: inactivation control transistor,
16, 16a to 16p: fuse, 18: redundant word line driver, 19: normal word line driver, 20: inactivating transistor, 41, 51, 70: shift register,
41a-41n, 44, 51a-51n, 55, 56 ...
Flip-flop, 49, NOR1, NOR11... NO
R circuit, 52... Decode address setting circuit, 53a-5
3n, 54a to 54n, NM1 to NM5, NM11 to N
M14, NM21 to NM24... N-type MOS transistors, PM1 to PM4, PM11 to PM14, PM21 to
PM24: p-type MOS transistor, INV1 to INV
6, INV11 to INV12, INV21 to INV22
... Inverter, TG1, TG2 ... Transfer gate,
NAND1 ... NAND circuit, AND21 ... AND circuit,
RX: word line drive pulse application terminal, RP: word line decode pulse application terminal, Vdd: power supply voltage terminal, R
WLa: redundant word line, WLa: normal word line, C: clock terminal, R: reset terminal, D: latch data input terminal, Q: latch data output terminal, F: initial data terminal, I: data input terminal, O: Data output terminal.

Claims (5)

[Claims] 1. A semiconductor device comprising: a plurality of conduction state selection elements in which a short circuit or an open state of an element itself can be arbitrarily set; and a circuit function or a circuit operation is changed based on a short circuit or an open state of the plurality of conduction state selection elements. A semiconductor integrated circuit device comprising: a first shift register circuit including a plurality of flip-flops, each of which stores state information indicating a short circuit or an open state of the plurality of conduction state selection elements; A second shift register configured by a plurality of flip-flops, each of which stores state information of the plurality of conduction state selection elements stored in the first shift register circuit by a serial transfer operation; Circuit function or circuit operation based on the state information of the plurality of conduction state selection elements stored in the second shift register circuit. Circuit operation changing means for changing the operation state; and control means for controlling a serial transfer operation between the first shift register circuit and the second shift register circuit. A semiconductor integrated circuit device, wherein a region where circuit elements other than the plurality of conduction state selection elements are formed is separated. 2. The second shift register is reset to a predetermined logic by a reset operation, and the first shift register has a logic opposite to a reset logic of the second shift register indicating a first bit of serial transfer. 2. The semiconductor integrated circuit according to claim 1, wherein flag information is stored, and said control means stops the serial transfer operation when said flag information has completely moved in said second shift register. apparatus. 3. The semiconductor integrated circuit device according to claim 1, wherein the plurality of conduction state selecting elements are intensively arranged in a specific region in the semiconductor integrated circuit device. 4. The circuit section is a semiconductor memory, the state information of the plurality of conduction state selection elements is address information for redundancy repair, and the circuit operation changing means is a decoder for decoding a redundancy address decoder. 4. The semiconductor integrated circuit device according to claim 1, wherein the device is an address setting unit. 5. The semiconductor according to claim 1, wherein the state information of the plurality of conduction state selection elements is operation timing margin adjustment information or threshold adjustment information. Integrated circuit device.